1 /* 2 * Synopsys DesignWare 8250 driver. 3 * 4 * Copyright 2011 Picochip, Jamie Iles. 5 * Copyright 2013 Intel Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 13 * LCR is written whilst busy. If it is, then a busy detect interrupt is 14 * raised, the LCR needs to be rewritten and the uart status register read. 15 */ 16 #include <linux/device.h> 17 #include <linux/init.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/serial_8250.h> 21 #include <linux/serial_core.h> 22 #include <linux/serial_reg.h> 23 #include <linux/of.h> 24 #include <linux/of_irq.h> 25 #include <linux/of_platform.h> 26 #include <linux/platform_device.h> 27 #include <linux/slab.h> 28 #include <linux/acpi.h> 29 #include <linux/clk.h> 30 #include <linux/pm_runtime.h> 31 32 #include <asm/byteorder.h> 33 34 #include "8250.h" 35 36 /* Offsets for the DesignWare specific registers */ 37 #define DW_UART_USR 0x1f /* UART Status Register */ 38 #define DW_UART_CPR 0xf4 /* Component Parameter Register */ 39 #define DW_UART_UCV 0xf8 /* UART Component Version */ 40 41 /* Component Parameter Register bits */ 42 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) 43 #define DW_UART_CPR_AFCE_MODE (1 << 4) 44 #define DW_UART_CPR_THRE_MODE (1 << 5) 45 #define DW_UART_CPR_SIR_MODE (1 << 6) 46 #define DW_UART_CPR_SIR_LP_MODE (1 << 7) 47 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) 48 #define DW_UART_CPR_FIFO_ACCESS (1 << 9) 49 #define DW_UART_CPR_FIFO_STAT (1 << 10) 50 #define DW_UART_CPR_SHADOW (1 << 11) 51 #define DW_UART_CPR_ENCODED_PARMS (1 << 12) 52 #define DW_UART_CPR_DMA_EXTRA (1 << 13) 53 #define DW_UART_CPR_FIFO_MODE (0xff << 16) 54 /* Helper for fifo size calculation */ 55 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) 56 57 58 struct dw8250_data { 59 int last_lcr; 60 int last_mcr; 61 int line; 62 struct clk *clk; 63 u8 usr_reg; 64 }; 65 66 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 67 { 68 struct dw8250_data *d = p->private_data; 69 70 /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */ 71 if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) { 72 value |= UART_MSR_CTS; 73 value &= ~UART_MSR_DCTS; 74 } 75 76 return value; 77 } 78 79 static void dw8250_serial_out(struct uart_port *p, int offset, int value) 80 { 81 struct dw8250_data *d = p->private_data; 82 83 if (offset == UART_LCR) 84 d->last_lcr = value; 85 86 if (offset == UART_MCR) 87 d->last_mcr = value; 88 89 writeb(value, p->membase + (offset << p->regshift)); 90 } 91 92 static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 93 { 94 unsigned int value = readb(p->membase + (offset << p->regshift)); 95 96 return dw8250_modify_msr(p, offset, value); 97 } 98 99 /* Read Back (rb) version to ensure register access ording. */ 100 static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value) 101 { 102 dw8250_serial_out(p, offset, value); 103 dw8250_serial_in(p, UART_LCR); 104 } 105 106 static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 107 { 108 struct dw8250_data *d = p->private_data; 109 110 if (offset == UART_LCR) 111 d->last_lcr = value; 112 113 if (offset == UART_MCR) 114 d->last_mcr = value; 115 116 writel(value, p->membase + (offset << p->regshift)); 117 } 118 119 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 120 { 121 unsigned int value = readl(p->membase + (offset << p->regshift)); 122 123 return dw8250_modify_msr(p, offset, value); 124 } 125 126 static int dw8250_handle_irq(struct uart_port *p) 127 { 128 struct dw8250_data *d = p->private_data; 129 unsigned int iir = p->serial_in(p, UART_IIR); 130 131 if (serial8250_handle_irq(p, iir)) { 132 return 1; 133 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 134 /* Clear the USR and write the LCR again. */ 135 (void)p->serial_in(p, d->usr_reg); 136 p->serial_out(p, UART_LCR, d->last_lcr); 137 138 return 1; 139 } 140 141 return 0; 142 } 143 144 static void 145 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 146 { 147 if (!state) 148 pm_runtime_get_sync(port->dev); 149 150 serial8250_do_pm(port, state, old); 151 152 if (state) 153 pm_runtime_put_sync_suspend(port->dev); 154 } 155 156 static void dw8250_setup_port(struct uart_8250_port *up) 157 { 158 struct uart_port *p = &up->port; 159 u32 reg = readl(p->membase + DW_UART_UCV); 160 161 /* 162 * If the Component Version Register returns zero, we know that 163 * ADDITIONAL_FEATURES are not enabled. No need to go any further. 164 */ 165 if (!reg) 166 return; 167 168 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n", 169 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); 170 171 reg = readl(p->membase + DW_UART_CPR); 172 if (!reg) 173 return; 174 175 /* Select the type based on fifo */ 176 if (reg & DW_UART_CPR_FIFO_MODE) { 177 p->type = PORT_16550A; 178 p->flags |= UPF_FIXED_TYPE; 179 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); 180 up->tx_loadsz = p->fifosize; 181 up->capabilities = UART_CAP_FIFO; 182 } 183 184 if (reg & DW_UART_CPR_AFCE_MODE) 185 up->capabilities |= UART_CAP_AFE; 186 } 187 188 static int dw8250_probe_of(struct uart_port *p, 189 struct dw8250_data *data) 190 { 191 struct device_node *np = p->dev->of_node; 192 u32 val; 193 bool has_ucv = true; 194 195 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 196 #ifdef __BIG_ENDIAN 197 /* 198 * Low order bits of these 64-bit registers, when 199 * accessed as a byte, are 7 bytes further down in the 200 * address space in big endian mode. 201 */ 202 p->membase += 7; 203 #endif 204 p->serial_out = dw8250_serial_out_rb; 205 p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 206 p->type = PORT_OCTEON; 207 data->usr_reg = 0x27; 208 has_ucv = false; 209 } else if (!of_property_read_u32(np, "reg-io-width", &val)) { 210 switch (val) { 211 case 1: 212 break; 213 case 4: 214 p->iotype = UPIO_MEM32; 215 p->serial_in = dw8250_serial_in32; 216 p->serial_out = dw8250_serial_out32; 217 break; 218 default: 219 dev_err(p->dev, "unsupported reg-io-width (%u)\n", val); 220 return -EINVAL; 221 } 222 } 223 if (has_ucv) 224 dw8250_setup_port(container_of(p, struct uart_8250_port, port)); 225 226 if (!of_property_read_u32(np, "reg-shift", &val)) 227 p->regshift = val; 228 229 /* clock got configured through clk api, all done */ 230 if (p->uartclk) 231 return 0; 232 233 /* try to find out clock frequency from DT as fallback */ 234 if (of_property_read_u32(np, "clock-frequency", &val)) { 235 dev_err(p->dev, "clk or clock-frequency not defined\n"); 236 return -EINVAL; 237 } 238 p->uartclk = val; 239 240 return 0; 241 } 242 243 #ifdef CONFIG_ACPI 244 static int dw8250_probe_acpi(struct uart_8250_port *up) 245 { 246 const struct acpi_device_id *id; 247 struct uart_port *p = &up->port; 248 249 dw8250_setup_port(up); 250 251 id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev); 252 if (!id) 253 return -ENODEV; 254 255 p->iotype = UPIO_MEM32; 256 p->serial_in = dw8250_serial_in32; 257 p->serial_out = dw8250_serial_out32; 258 p->regshift = 2; 259 260 if (!p->uartclk) 261 p->uartclk = (unsigned int)id->driver_data; 262 263 up->dma = devm_kzalloc(p->dev, sizeof(*up->dma), GFP_KERNEL); 264 if (!up->dma) 265 return -ENOMEM; 266 267 up->dma->rxconf.src_maxburst = p->fifosize / 4; 268 up->dma->txconf.dst_maxburst = p->fifosize / 4; 269 270 return 0; 271 } 272 #else 273 static inline int dw8250_probe_acpi(struct uart_8250_port *up) 274 { 275 return -ENODEV; 276 } 277 #endif /* CONFIG_ACPI */ 278 279 static int dw8250_probe(struct platform_device *pdev) 280 { 281 struct uart_8250_port uart = {}; 282 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 283 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 284 struct dw8250_data *data; 285 int err; 286 287 if (!regs || !irq) { 288 dev_err(&pdev->dev, "no registers/irq defined\n"); 289 return -EINVAL; 290 } 291 292 spin_lock_init(&uart.port.lock); 293 uart.port.mapbase = regs->start; 294 uart.port.irq = irq->start; 295 uart.port.handle_irq = dw8250_handle_irq; 296 uart.port.pm = dw8250_do_pm; 297 uart.port.type = PORT_8250; 298 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT; 299 uart.port.dev = &pdev->dev; 300 301 uart.port.membase = devm_ioremap(&pdev->dev, regs->start, 302 resource_size(regs)); 303 if (!uart.port.membase) 304 return -ENOMEM; 305 306 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 307 if (!data) 308 return -ENOMEM; 309 310 data->usr_reg = DW_UART_USR; 311 data->clk = devm_clk_get(&pdev->dev, NULL); 312 if (!IS_ERR(data->clk)) { 313 clk_prepare_enable(data->clk); 314 uart.port.uartclk = clk_get_rate(data->clk); 315 } 316 317 uart.port.iotype = UPIO_MEM; 318 uart.port.serial_in = dw8250_serial_in; 319 uart.port.serial_out = dw8250_serial_out; 320 uart.port.private_data = data; 321 322 if (pdev->dev.of_node) { 323 err = dw8250_probe_of(&uart.port, data); 324 if (err) 325 return err; 326 } else if (ACPI_HANDLE(&pdev->dev)) { 327 err = dw8250_probe_acpi(&uart); 328 if (err) 329 return err; 330 } else { 331 return -ENODEV; 332 } 333 334 data->line = serial8250_register_8250_port(&uart); 335 if (data->line < 0) 336 return data->line; 337 338 platform_set_drvdata(pdev, data); 339 340 pm_runtime_set_active(&pdev->dev); 341 pm_runtime_enable(&pdev->dev); 342 343 return 0; 344 } 345 346 static int dw8250_remove(struct platform_device *pdev) 347 { 348 struct dw8250_data *data = platform_get_drvdata(pdev); 349 350 pm_runtime_get_sync(&pdev->dev); 351 352 serial8250_unregister_port(data->line); 353 354 if (!IS_ERR(data->clk)) 355 clk_disable_unprepare(data->clk); 356 357 pm_runtime_disable(&pdev->dev); 358 pm_runtime_put_noidle(&pdev->dev); 359 360 return 0; 361 } 362 363 #ifdef CONFIG_PM 364 static int dw8250_suspend(struct device *dev) 365 { 366 struct dw8250_data *data = dev_get_drvdata(dev); 367 368 serial8250_suspend_port(data->line); 369 370 return 0; 371 } 372 373 static int dw8250_resume(struct device *dev) 374 { 375 struct dw8250_data *data = dev_get_drvdata(dev); 376 377 serial8250_resume_port(data->line); 378 379 return 0; 380 } 381 #endif /* CONFIG_PM */ 382 383 #ifdef CONFIG_PM_RUNTIME 384 static int dw8250_runtime_suspend(struct device *dev) 385 { 386 struct dw8250_data *data = dev_get_drvdata(dev); 387 388 if (!IS_ERR(data->clk)) 389 clk_disable_unprepare(data->clk); 390 391 return 0; 392 } 393 394 static int dw8250_runtime_resume(struct device *dev) 395 { 396 struct dw8250_data *data = dev_get_drvdata(dev); 397 398 if (!IS_ERR(data->clk)) 399 clk_prepare_enable(data->clk); 400 401 return 0; 402 } 403 #endif 404 405 static const struct dev_pm_ops dw8250_pm_ops = { 406 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 407 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 408 }; 409 410 static const struct of_device_id dw8250_of_match[] = { 411 { .compatible = "snps,dw-apb-uart" }, 412 { .compatible = "cavium,octeon-3860-uart" }, 413 { /* Sentinel */ } 414 }; 415 MODULE_DEVICE_TABLE(of, dw8250_of_match); 416 417 static const struct acpi_device_id dw8250_acpi_match[] = { 418 { "INT33C4", 0 }, 419 { "INT33C5", 0 }, 420 { "80860F0A", 0 }, 421 { }, 422 }; 423 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 424 425 static struct platform_driver dw8250_platform_driver = { 426 .driver = { 427 .name = "dw-apb-uart", 428 .owner = THIS_MODULE, 429 .pm = &dw8250_pm_ops, 430 .of_match_table = dw8250_of_match, 431 .acpi_match_table = ACPI_PTR(dw8250_acpi_match), 432 }, 433 .probe = dw8250_probe, 434 .remove = dw8250_remove, 435 }; 436 437 module_platform_driver(dw8250_platform_driver); 438 439 MODULE_AUTHOR("Jamie Iles"); 440 MODULE_LICENSE("GPL"); 441 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 442