1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Synopsys DesignWare 8250 driver. 4 * 5 * Copyright 2011 Picochip, Jamie Iles. 6 * Copyright 2013 Intel Corporation 7 * 8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 9 * LCR is written whilst busy. If it is, then a busy detect interrupt is 10 * raised, the LCR needs to be rewritten and the uart status register read. 11 */ 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/workqueue.h> 23 #include <linux/notifier.h> 24 #include <linux/slab.h> 25 #include <linux/acpi.h> 26 #include <linux/clk.h> 27 #include <linux/reset.h> 28 #include <linux/pm_runtime.h> 29 30 #include <asm/byteorder.h> 31 32 #include "8250_dwlib.h" 33 34 /* Offsets for the DesignWare specific registers */ 35 #define DW_UART_USR 0x1f /* UART Status Register */ 36 37 /* DesignWare specific register fields */ 38 #define DW_UART_MCR_SIRE BIT(6) 39 40 struct dw8250_data { 41 struct dw8250_port_data data; 42 43 u8 usr_reg; 44 int msr_mask_on; 45 int msr_mask_off; 46 struct clk *clk; 47 struct clk *pclk; 48 struct notifier_block clk_notifier; 49 struct work_struct clk_work; 50 struct reset_control *rst; 51 52 unsigned int skip_autocfg:1; 53 unsigned int uart_16550_compatible:1; 54 }; 55 56 static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data) 57 { 58 return container_of(data, struct dw8250_data, data); 59 } 60 61 static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb) 62 { 63 return container_of(nb, struct dw8250_data, clk_notifier); 64 } 65 66 static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work) 67 { 68 return container_of(work, struct dw8250_data, clk_work); 69 } 70 71 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 72 { 73 struct dw8250_data *d = to_dw8250_data(p->private_data); 74 75 /* Override any modem control signals if needed */ 76 if (offset == UART_MSR) { 77 value |= d->msr_mask_on; 78 value &= ~d->msr_mask_off; 79 } 80 81 return value; 82 } 83 84 static void dw8250_force_idle(struct uart_port *p) 85 { 86 struct uart_8250_port *up = up_to_u8250p(p); 87 88 serial8250_clear_and_reinit_fifos(up); 89 (void)p->serial_in(p, UART_RX); 90 } 91 92 static void dw8250_check_lcr(struct uart_port *p, int value) 93 { 94 void __iomem *offset = p->membase + (UART_LCR << p->regshift); 95 int tries = 1000; 96 97 /* Make sure LCR write wasn't ignored */ 98 while (tries--) { 99 unsigned int lcr = p->serial_in(p, UART_LCR); 100 101 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 102 return; 103 104 dw8250_force_idle(p); 105 106 #ifdef CONFIG_64BIT 107 if (p->type == PORT_OCTEON) 108 __raw_writeq(value & 0xff, offset); 109 else 110 #endif 111 if (p->iotype == UPIO_MEM32) 112 writel(value, offset); 113 else if (p->iotype == UPIO_MEM32BE) 114 iowrite32be(value, offset); 115 else 116 writeb(value, offset); 117 } 118 /* 119 * FIXME: this deadlocks if port->lock is already held 120 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 121 */ 122 } 123 124 /* Returns once the transmitter is empty or we run out of retries */ 125 static void dw8250_tx_wait_empty(struct uart_port *p) 126 { 127 unsigned int tries = 20000; 128 unsigned int delay_threshold = tries - 1000; 129 unsigned int lsr; 130 131 while (tries--) { 132 lsr = readb (p->membase + (UART_LSR << p->regshift)); 133 if (lsr & UART_LSR_TEMT) 134 break; 135 136 /* The device is first given a chance to empty without delay, 137 * to avoid slowdowns at high bitrates. If after 1000 tries 138 * the buffer has still not emptied, allow more time for low- 139 * speed links. */ 140 if (tries < delay_threshold) 141 udelay (1); 142 } 143 } 144 145 static void dw8250_serial_out38x(struct uart_port *p, int offset, int value) 146 { 147 struct dw8250_data *d = to_dw8250_data(p->private_data); 148 149 /* Allow the TX to drain before we reconfigure */ 150 if (offset == UART_LCR) 151 dw8250_tx_wait_empty(p); 152 153 writeb(value, p->membase + (offset << p->regshift)); 154 155 if (offset == UART_LCR && !d->uart_16550_compatible) 156 dw8250_check_lcr(p, value); 157 } 158 159 160 static void dw8250_serial_out(struct uart_port *p, int offset, int value) 161 { 162 struct dw8250_data *d = to_dw8250_data(p->private_data); 163 164 writeb(value, p->membase + (offset << p->regshift)); 165 166 if (offset == UART_LCR && !d->uart_16550_compatible) 167 dw8250_check_lcr(p, value); 168 } 169 170 static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 171 { 172 unsigned int value = readb(p->membase + (offset << p->regshift)); 173 174 return dw8250_modify_msr(p, offset, value); 175 } 176 177 #ifdef CONFIG_64BIT 178 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) 179 { 180 unsigned int value; 181 182 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); 183 184 return dw8250_modify_msr(p, offset, value); 185 } 186 187 static void dw8250_serial_outq(struct uart_port *p, int offset, int value) 188 { 189 struct dw8250_data *d = to_dw8250_data(p->private_data); 190 191 value &= 0xff; 192 __raw_writeq(value, p->membase + (offset << p->regshift)); 193 /* Read back to ensure register write ordering. */ 194 __raw_readq(p->membase + (UART_LCR << p->regshift)); 195 196 if (offset == UART_LCR && !d->uart_16550_compatible) 197 dw8250_check_lcr(p, value); 198 } 199 #endif /* CONFIG_64BIT */ 200 201 static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 202 { 203 struct dw8250_data *d = to_dw8250_data(p->private_data); 204 205 writel(value, p->membase + (offset << p->regshift)); 206 207 if (offset == UART_LCR && !d->uart_16550_compatible) 208 dw8250_check_lcr(p, value); 209 } 210 211 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 212 { 213 unsigned int value = readl(p->membase + (offset << p->regshift)); 214 215 return dw8250_modify_msr(p, offset, value); 216 } 217 218 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value) 219 { 220 struct dw8250_data *d = to_dw8250_data(p->private_data); 221 222 iowrite32be(value, p->membase + (offset << p->regshift)); 223 224 if (offset == UART_LCR && !d->uart_16550_compatible) 225 dw8250_check_lcr(p, value); 226 } 227 228 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) 229 { 230 unsigned int value = ioread32be(p->membase + (offset << p->regshift)); 231 232 return dw8250_modify_msr(p, offset, value); 233 } 234 235 236 static int dw8250_handle_irq(struct uart_port *p) 237 { 238 struct uart_8250_port *up = up_to_u8250p(p); 239 struct dw8250_data *d = to_dw8250_data(p->private_data); 240 unsigned int iir = p->serial_in(p, UART_IIR); 241 unsigned int status; 242 unsigned long flags; 243 244 /* 245 * There are ways to get Designware-based UARTs into a state where 246 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual 247 * data available. If we see such a case then we'll do a bogus 248 * read. If we don't do this then the "RX TIMEOUT" interrupt will 249 * fire forever. 250 * 251 * This problem has only been observed so far when not in DMA mode 252 * so we limit the workaround only to non-DMA mode. 253 */ 254 if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) { 255 spin_lock_irqsave(&p->lock, flags); 256 status = p->serial_in(p, UART_LSR); 257 258 if (!(status & (UART_LSR_DR | UART_LSR_BI))) 259 (void) p->serial_in(p, UART_RX); 260 261 spin_unlock_irqrestore(&p->lock, flags); 262 } 263 264 if (serial8250_handle_irq(p, iir)) 265 return 1; 266 267 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 268 /* Clear the USR */ 269 (void)p->serial_in(p, d->usr_reg); 270 271 return 1; 272 } 273 274 return 0; 275 } 276 277 static void dw8250_clk_work_cb(struct work_struct *work) 278 { 279 struct dw8250_data *d = work_to_dw8250_data(work); 280 struct uart_8250_port *up; 281 unsigned long rate; 282 283 rate = clk_get_rate(d->clk); 284 if (rate <= 0) 285 return; 286 287 up = serial8250_get_port(d->data.line); 288 289 serial8250_update_uartclk(&up->port, rate); 290 } 291 292 static int dw8250_clk_notifier_cb(struct notifier_block *nb, 293 unsigned long event, void *data) 294 { 295 struct dw8250_data *d = clk_to_dw8250_data(nb); 296 297 /* 298 * We have no choice but to defer the uartclk update due to two 299 * deadlocks. First one is caused by a recursive mutex lock which 300 * happens when clk_set_rate() is called from dw8250_set_termios(). 301 * Second deadlock is more tricky and is caused by an inverted order of 302 * the clk and tty-port mutexes lock. It happens if clock rate change 303 * is requested asynchronously while set_termios() is executed between 304 * tty-port mutex lock and clk_set_rate() function invocation and 305 * vise-versa. Anyway if we didn't have the reference clock alteration 306 * in the dw8250_set_termios() method we wouldn't have needed this 307 * deferred event handling complication. 308 */ 309 if (event == POST_RATE_CHANGE) { 310 queue_work(system_unbound_wq, &d->clk_work); 311 return NOTIFY_OK; 312 } 313 314 return NOTIFY_DONE; 315 } 316 317 static void 318 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 319 { 320 if (!state) 321 pm_runtime_get_sync(port->dev); 322 323 serial8250_do_pm(port, state, old); 324 325 if (state) 326 pm_runtime_put_sync_suspend(port->dev); 327 } 328 329 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, 330 struct ktermios *old) 331 { 332 unsigned long newrate = tty_termios_baud_rate(termios) * 16; 333 struct dw8250_data *d = to_dw8250_data(p->private_data); 334 long rate; 335 int ret; 336 337 clk_disable_unprepare(d->clk); 338 rate = clk_round_rate(d->clk, newrate); 339 if (rate > 0) { 340 /* 341 * Premilinary set the uartclk to the new clock rate so the 342 * clock update event handler caused by the clk_set_rate() 343 * calling wouldn't actually update the UART divisor since 344 * we about to do this anyway. 345 */ 346 swap(p->uartclk, rate); 347 ret = clk_set_rate(d->clk, newrate); 348 if (ret) 349 swap(p->uartclk, rate); 350 } 351 clk_prepare_enable(d->clk); 352 353 p->status &= ~UPSTAT_AUTOCTS; 354 if (termios->c_cflag & CRTSCTS) 355 p->status |= UPSTAT_AUTOCTS; 356 357 serial8250_do_set_termios(p, termios, old); 358 } 359 360 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios) 361 { 362 struct uart_8250_port *up = up_to_u8250p(p); 363 unsigned int mcr = p->serial_in(p, UART_MCR); 364 365 if (up->capabilities & UART_CAP_IRDA) { 366 if (termios->c_line == N_IRDA) 367 mcr |= DW_UART_MCR_SIRE; 368 else 369 mcr &= ~DW_UART_MCR_SIRE; 370 371 p->serial_out(p, UART_MCR, mcr); 372 } 373 serial8250_do_set_ldisc(p, termios); 374 } 375 376 /* 377 * dw8250_fallback_dma_filter will prevent the UART from getting just any free 378 * channel on platforms that have DMA engines, but don't have any channels 379 * assigned to the UART. 380 * 381 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the 382 * core problem is fixed, this function is no longer needed. 383 */ 384 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param) 385 { 386 return false; 387 } 388 389 static bool dw8250_idma_filter(struct dma_chan *chan, void *param) 390 { 391 return param == chan->device->dev; 392 } 393 394 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) 395 { 396 if (p->dev->of_node) { 397 struct device_node *np = p->dev->of_node; 398 int id; 399 400 /* get index of serial line, if found in DT aliases */ 401 id = of_alias_get_id(np, "serial"); 402 if (id >= 0) 403 p->line = id; 404 #ifdef CONFIG_64BIT 405 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 406 p->serial_in = dw8250_serial_inq; 407 p->serial_out = dw8250_serial_outq; 408 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 409 p->type = PORT_OCTEON; 410 data->usr_reg = 0x27; 411 data->skip_autocfg = true; 412 } 413 #endif 414 if (of_device_is_big_endian(p->dev->of_node)) { 415 p->iotype = UPIO_MEM32BE; 416 p->serial_in = dw8250_serial_in32be; 417 p->serial_out = dw8250_serial_out32be; 418 } 419 if (of_device_is_compatible(np, "marvell,armada-38x-uart")) 420 p->serial_out = dw8250_serial_out38x; 421 422 } else if (acpi_dev_present("APMC0D08", NULL, -1)) { 423 p->iotype = UPIO_MEM32; 424 p->regshift = 2; 425 p->serial_in = dw8250_serial_in32; 426 data->uart_16550_compatible = true; 427 } 428 429 /* Platforms with iDMA 64-bit */ 430 if (platform_get_resource_byname(to_platform_device(p->dev), 431 IORESOURCE_MEM, "lpss_priv")) { 432 data->data.dma.rx_param = p->dev->parent; 433 data->data.dma.tx_param = p->dev->parent; 434 data->data.dma.fn = dw8250_idma_filter; 435 } 436 } 437 438 static int dw8250_probe(struct platform_device *pdev) 439 { 440 struct uart_8250_port uart = {}, *up = &uart; 441 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 442 struct uart_port *p = &up->port; 443 struct device *dev = &pdev->dev; 444 struct dw8250_data *data; 445 int irq; 446 int err; 447 u32 val; 448 449 if (!regs) { 450 dev_err(dev, "no registers defined\n"); 451 return -EINVAL; 452 } 453 454 irq = platform_get_irq(pdev, 0); 455 if (irq < 0) 456 return irq; 457 458 spin_lock_init(&p->lock); 459 p->mapbase = regs->start; 460 p->irq = irq; 461 p->handle_irq = dw8250_handle_irq; 462 p->pm = dw8250_do_pm; 463 p->type = PORT_8250; 464 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; 465 p->dev = dev; 466 p->iotype = UPIO_MEM; 467 p->serial_in = dw8250_serial_in; 468 p->serial_out = dw8250_serial_out; 469 p->set_ldisc = dw8250_set_ldisc; 470 p->set_termios = dw8250_set_termios; 471 472 p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); 473 if (!p->membase) 474 return -ENOMEM; 475 476 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 477 if (!data) 478 return -ENOMEM; 479 480 data->data.dma.fn = dw8250_fallback_dma_filter; 481 data->usr_reg = DW_UART_USR; 482 p->private_data = &data->data; 483 484 data->uart_16550_compatible = device_property_read_bool(dev, 485 "snps,uart-16550-compatible"); 486 487 err = device_property_read_u32(dev, "reg-shift", &val); 488 if (!err) 489 p->regshift = val; 490 491 err = device_property_read_u32(dev, "reg-io-width", &val); 492 if (!err && val == 4) { 493 p->iotype = UPIO_MEM32; 494 p->serial_in = dw8250_serial_in32; 495 p->serial_out = dw8250_serial_out32; 496 } 497 498 if (device_property_read_bool(dev, "dcd-override")) { 499 /* Always report DCD as active */ 500 data->msr_mask_on |= UART_MSR_DCD; 501 data->msr_mask_off |= UART_MSR_DDCD; 502 } 503 504 if (device_property_read_bool(dev, "dsr-override")) { 505 /* Always report DSR as active */ 506 data->msr_mask_on |= UART_MSR_DSR; 507 data->msr_mask_off |= UART_MSR_DDSR; 508 } 509 510 if (device_property_read_bool(dev, "cts-override")) { 511 /* Always report CTS as active */ 512 data->msr_mask_on |= UART_MSR_CTS; 513 data->msr_mask_off |= UART_MSR_DCTS; 514 } 515 516 if (device_property_read_bool(dev, "ri-override")) { 517 /* Always report Ring indicator as inactive */ 518 data->msr_mask_off |= UART_MSR_RI; 519 data->msr_mask_off |= UART_MSR_TERI; 520 } 521 522 /* Always ask for fixed clock rate from a property. */ 523 device_property_read_u32(dev, "clock-frequency", &p->uartclk); 524 525 /* If there is separate baudclk, get the rate from it. */ 526 data->clk = devm_clk_get_optional(dev, "baudclk"); 527 if (data->clk == NULL) 528 data->clk = devm_clk_get_optional(dev, NULL); 529 if (IS_ERR(data->clk)) 530 return PTR_ERR(data->clk); 531 532 INIT_WORK(&data->clk_work, dw8250_clk_work_cb); 533 data->clk_notifier.notifier_call = dw8250_clk_notifier_cb; 534 535 err = clk_prepare_enable(data->clk); 536 if (err) 537 dev_warn(dev, "could not enable optional baudclk: %d\n", err); 538 539 if (data->clk) 540 p->uartclk = clk_get_rate(data->clk); 541 542 /* If no clock rate is defined, fail. */ 543 if (!p->uartclk) { 544 dev_err(dev, "clock rate not defined\n"); 545 err = -EINVAL; 546 goto err_clk; 547 } 548 549 data->pclk = devm_clk_get_optional(dev, "apb_pclk"); 550 if (IS_ERR(data->pclk)) { 551 err = PTR_ERR(data->pclk); 552 goto err_clk; 553 } 554 555 err = clk_prepare_enable(data->pclk); 556 if (err) { 557 dev_err(dev, "could not enable apb_pclk\n"); 558 goto err_clk; 559 } 560 561 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); 562 if (IS_ERR(data->rst)) { 563 err = PTR_ERR(data->rst); 564 goto err_pclk; 565 } 566 reset_control_deassert(data->rst); 567 568 dw8250_quirks(p, data); 569 570 /* If the Busy Functionality is not implemented, don't handle it */ 571 if (data->uart_16550_compatible) 572 p->handle_irq = NULL; 573 574 if (!data->skip_autocfg) 575 dw8250_setup_port(p); 576 577 /* If we have a valid fifosize, try hooking up DMA */ 578 if (p->fifosize) { 579 data->data.dma.rxconf.src_maxburst = p->fifosize / 4; 580 data->data.dma.txconf.dst_maxburst = p->fifosize / 4; 581 up->dma = &data->data.dma; 582 } 583 584 data->data.line = serial8250_register_8250_port(up); 585 if (data->data.line < 0) { 586 err = data->data.line; 587 goto err_reset; 588 } 589 590 /* 591 * Some platforms may provide a reference clock shared between several 592 * devices. In this case any clock state change must be known to the 593 * UART port at least post factum. 594 */ 595 if (data->clk) { 596 err = clk_notifier_register(data->clk, &data->clk_notifier); 597 if (err) 598 dev_warn(p->dev, "Failed to set the clock notifier\n"); 599 else 600 queue_work(system_unbound_wq, &data->clk_work); 601 } 602 603 platform_set_drvdata(pdev, data); 604 605 pm_runtime_set_active(dev); 606 pm_runtime_enable(dev); 607 608 return 0; 609 610 err_reset: 611 reset_control_assert(data->rst); 612 613 err_pclk: 614 clk_disable_unprepare(data->pclk); 615 616 err_clk: 617 clk_disable_unprepare(data->clk); 618 619 return err; 620 } 621 622 static int dw8250_remove(struct platform_device *pdev) 623 { 624 struct dw8250_data *data = platform_get_drvdata(pdev); 625 struct device *dev = &pdev->dev; 626 627 pm_runtime_get_sync(dev); 628 629 if (data->clk) { 630 clk_notifier_unregister(data->clk, &data->clk_notifier); 631 632 flush_work(&data->clk_work); 633 } 634 635 serial8250_unregister_port(data->data.line); 636 637 reset_control_assert(data->rst); 638 639 clk_disable_unprepare(data->pclk); 640 641 clk_disable_unprepare(data->clk); 642 643 pm_runtime_disable(dev); 644 pm_runtime_put_noidle(dev); 645 646 return 0; 647 } 648 649 #ifdef CONFIG_PM_SLEEP 650 static int dw8250_suspend(struct device *dev) 651 { 652 struct dw8250_data *data = dev_get_drvdata(dev); 653 654 serial8250_suspend_port(data->data.line); 655 656 return 0; 657 } 658 659 static int dw8250_resume(struct device *dev) 660 { 661 struct dw8250_data *data = dev_get_drvdata(dev); 662 663 serial8250_resume_port(data->data.line); 664 665 return 0; 666 } 667 #endif /* CONFIG_PM_SLEEP */ 668 669 #ifdef CONFIG_PM 670 static int dw8250_runtime_suspend(struct device *dev) 671 { 672 struct dw8250_data *data = dev_get_drvdata(dev); 673 674 clk_disable_unprepare(data->clk); 675 676 clk_disable_unprepare(data->pclk); 677 678 return 0; 679 } 680 681 static int dw8250_runtime_resume(struct device *dev) 682 { 683 struct dw8250_data *data = dev_get_drvdata(dev); 684 685 clk_prepare_enable(data->pclk); 686 687 clk_prepare_enable(data->clk); 688 689 return 0; 690 } 691 #endif 692 693 static const struct dev_pm_ops dw8250_pm_ops = { 694 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 695 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 696 }; 697 698 static const struct of_device_id dw8250_of_match[] = { 699 { .compatible = "snps,dw-apb-uart" }, 700 { .compatible = "cavium,octeon-3860-uart" }, 701 { .compatible = "marvell,armada-38x-uart" }, 702 { .compatible = "renesas,rzn1-uart" }, 703 { /* Sentinel */ } 704 }; 705 MODULE_DEVICE_TABLE(of, dw8250_of_match); 706 707 static const struct acpi_device_id dw8250_acpi_match[] = { 708 { "INT33C4", 0 }, 709 { "INT33C5", 0 }, 710 { "INT3434", 0 }, 711 { "INT3435", 0 }, 712 { "80860F0A", 0 }, 713 { "8086228A", 0 }, 714 { "APMC0D08", 0}, 715 { "AMD0020", 0 }, 716 { "AMDI0020", 0 }, 717 { "AMDI0022", 0 }, 718 { "BRCM2032", 0 }, 719 { "HISI0031", 0 }, 720 { }, 721 }; 722 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 723 724 static struct platform_driver dw8250_platform_driver = { 725 .driver = { 726 .name = "dw-apb-uart", 727 .pm = &dw8250_pm_ops, 728 .of_match_table = dw8250_of_match, 729 .acpi_match_table = ACPI_PTR(dw8250_acpi_match), 730 }, 731 .probe = dw8250_probe, 732 .remove = dw8250_remove, 733 }; 734 735 module_platform_driver(dw8250_platform_driver); 736 737 MODULE_AUTHOR("Jamie Iles"); 738 MODULE_LICENSE("GPL"); 739 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 740 MODULE_ALIAS("platform:dw-apb-uart"); 741