1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Synopsys DesignWare 8250 driver. 4 * 5 * Copyright 2011 Picochip, Jamie Iles. 6 * Copyright 2013 Intel Corporation 7 * 8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 9 * LCR is written whilst busy. If it is, then a busy detect interrupt is 10 * raised, the LCR needs to be rewritten and the uart status register read. 11 */ 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 #include <linux/acpi.h> 24 #include <linux/clk.h> 25 #include <linux/reset.h> 26 #include <linux/pm_runtime.h> 27 28 #include <asm/byteorder.h> 29 30 #include "8250.h" 31 32 /* Offsets for the DesignWare specific registers */ 33 #define DW_UART_USR 0x1f /* UART Status Register */ 34 #define DW_UART_DLF 0xc0 /* Divisor Latch Fraction Register */ 35 #define DW_UART_CPR 0xf4 /* Component Parameter Register */ 36 #define DW_UART_UCV 0xf8 /* UART Component Version */ 37 38 /* Component Parameter Register bits */ 39 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) 40 #define DW_UART_CPR_AFCE_MODE (1 << 4) 41 #define DW_UART_CPR_THRE_MODE (1 << 5) 42 #define DW_UART_CPR_SIR_MODE (1 << 6) 43 #define DW_UART_CPR_SIR_LP_MODE (1 << 7) 44 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) 45 #define DW_UART_CPR_FIFO_ACCESS (1 << 9) 46 #define DW_UART_CPR_FIFO_STAT (1 << 10) 47 #define DW_UART_CPR_SHADOW (1 << 11) 48 #define DW_UART_CPR_ENCODED_PARMS (1 << 12) 49 #define DW_UART_CPR_DMA_EXTRA (1 << 13) 50 #define DW_UART_CPR_FIFO_MODE (0xff << 16) 51 /* Helper for fifo size calculation */ 52 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) 53 54 /* DesignWare specific register fields */ 55 #define DW_UART_MCR_SIRE BIT(6) 56 57 struct dw8250_data { 58 u8 usr_reg; 59 u8 dlf_size; 60 int line; 61 int msr_mask_on; 62 int msr_mask_off; 63 struct clk *clk; 64 struct clk *pclk; 65 struct reset_control *rst; 66 struct uart_8250_dma dma; 67 68 unsigned int skip_autocfg:1; 69 unsigned int uart_16550_compatible:1; 70 }; 71 72 static inline u32 dw8250_readl_ext(struct uart_port *p, int offset) 73 { 74 if (p->iotype == UPIO_MEM32BE) 75 return ioread32be(p->membase + offset); 76 return readl(p->membase + offset); 77 } 78 79 static inline void dw8250_writel_ext(struct uart_port *p, int offset, u32 reg) 80 { 81 if (p->iotype == UPIO_MEM32BE) 82 iowrite32be(reg, p->membase + offset); 83 else 84 writel(reg, p->membase + offset); 85 } 86 87 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 88 { 89 struct dw8250_data *d = p->private_data; 90 91 /* Override any modem control signals if needed */ 92 if (offset == UART_MSR) { 93 value |= d->msr_mask_on; 94 value &= ~d->msr_mask_off; 95 } 96 97 return value; 98 } 99 100 static void dw8250_force_idle(struct uart_port *p) 101 { 102 struct uart_8250_port *up = up_to_u8250p(p); 103 104 serial8250_clear_and_reinit_fifos(up); 105 (void)p->serial_in(p, UART_RX); 106 } 107 108 static void dw8250_check_lcr(struct uart_port *p, int value) 109 { 110 void __iomem *offset = p->membase + (UART_LCR << p->regshift); 111 int tries = 1000; 112 113 /* Make sure LCR write wasn't ignored */ 114 while (tries--) { 115 unsigned int lcr = p->serial_in(p, UART_LCR); 116 117 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 118 return; 119 120 dw8250_force_idle(p); 121 122 #ifdef CONFIG_64BIT 123 if (p->type == PORT_OCTEON) 124 __raw_writeq(value & 0xff, offset); 125 else 126 #endif 127 if (p->iotype == UPIO_MEM32) 128 writel(value, offset); 129 else if (p->iotype == UPIO_MEM32BE) 130 iowrite32be(value, offset); 131 else 132 writeb(value, offset); 133 } 134 /* 135 * FIXME: this deadlocks if port->lock is already held 136 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 137 */ 138 } 139 140 /* Returns once the transmitter is empty or we run out of retries */ 141 static void dw8250_tx_wait_empty(struct uart_port *p) 142 { 143 unsigned int tries = 20000; 144 unsigned int delay_threshold = tries - 1000; 145 unsigned int lsr; 146 147 while (tries--) { 148 lsr = readb (p->membase + (UART_LSR << p->regshift)); 149 if (lsr & UART_LSR_TEMT) 150 break; 151 152 /* The device is first given a chance to empty without delay, 153 * to avoid slowdowns at high bitrates. If after 1000 tries 154 * the buffer has still not emptied, allow more time for low- 155 * speed links. */ 156 if (tries < delay_threshold) 157 udelay (1); 158 } 159 } 160 161 static void dw8250_serial_out38x(struct uart_port *p, int offset, int value) 162 { 163 struct dw8250_data *d = p->private_data; 164 165 /* Allow the TX to drain before we reconfigure */ 166 if (offset == UART_LCR) 167 dw8250_tx_wait_empty(p); 168 169 writeb(value, p->membase + (offset << p->regshift)); 170 171 if (offset == UART_LCR && !d->uart_16550_compatible) 172 dw8250_check_lcr(p, value); 173 } 174 175 176 static void dw8250_serial_out(struct uart_port *p, int offset, int value) 177 { 178 struct dw8250_data *d = p->private_data; 179 180 writeb(value, p->membase + (offset << p->regshift)); 181 182 if (offset == UART_LCR && !d->uart_16550_compatible) 183 dw8250_check_lcr(p, value); 184 } 185 186 static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 187 { 188 unsigned int value = readb(p->membase + (offset << p->regshift)); 189 190 return dw8250_modify_msr(p, offset, value); 191 } 192 193 #ifdef CONFIG_64BIT 194 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) 195 { 196 unsigned int value; 197 198 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); 199 200 return dw8250_modify_msr(p, offset, value); 201 } 202 203 static void dw8250_serial_outq(struct uart_port *p, int offset, int value) 204 { 205 struct dw8250_data *d = p->private_data; 206 207 value &= 0xff; 208 __raw_writeq(value, p->membase + (offset << p->regshift)); 209 /* Read back to ensure register write ordering. */ 210 __raw_readq(p->membase + (UART_LCR << p->regshift)); 211 212 if (offset == UART_LCR && !d->uart_16550_compatible) 213 dw8250_check_lcr(p, value); 214 } 215 #endif /* CONFIG_64BIT */ 216 217 static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 218 { 219 struct dw8250_data *d = p->private_data; 220 221 writel(value, p->membase + (offset << p->regshift)); 222 223 if (offset == UART_LCR && !d->uart_16550_compatible) 224 dw8250_check_lcr(p, value); 225 } 226 227 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 228 { 229 unsigned int value = readl(p->membase + (offset << p->regshift)); 230 231 return dw8250_modify_msr(p, offset, value); 232 } 233 234 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value) 235 { 236 struct dw8250_data *d = p->private_data; 237 238 iowrite32be(value, p->membase + (offset << p->regshift)); 239 240 if (offset == UART_LCR && !d->uart_16550_compatible) 241 dw8250_check_lcr(p, value); 242 } 243 244 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) 245 { 246 unsigned int value = ioread32be(p->membase + (offset << p->regshift)); 247 248 return dw8250_modify_msr(p, offset, value); 249 } 250 251 252 static int dw8250_handle_irq(struct uart_port *p) 253 { 254 struct uart_8250_port *up = up_to_u8250p(p); 255 struct dw8250_data *d = p->private_data; 256 unsigned int iir = p->serial_in(p, UART_IIR); 257 unsigned int status; 258 unsigned long flags; 259 260 /* 261 * There are ways to get Designware-based UARTs into a state where 262 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual 263 * data available. If we see such a case then we'll do a bogus 264 * read. If we don't do this then the "RX TIMEOUT" interrupt will 265 * fire forever. 266 * 267 * This problem has only been observed so far when not in DMA mode 268 * so we limit the workaround only to non-DMA mode. 269 */ 270 if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) { 271 spin_lock_irqsave(&p->lock, flags); 272 status = p->serial_in(p, UART_LSR); 273 274 if (!(status & (UART_LSR_DR | UART_LSR_BI))) 275 (void) p->serial_in(p, UART_RX); 276 277 spin_unlock_irqrestore(&p->lock, flags); 278 } 279 280 if (serial8250_handle_irq(p, iir)) 281 return 1; 282 283 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 284 /* Clear the USR */ 285 (void)p->serial_in(p, d->usr_reg); 286 287 return 1; 288 } 289 290 return 0; 291 } 292 293 static void 294 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 295 { 296 if (!state) 297 pm_runtime_get_sync(port->dev); 298 299 serial8250_do_pm(port, state, old); 300 301 if (state) 302 pm_runtime_put_sync_suspend(port->dev); 303 } 304 305 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, 306 struct ktermios *old) 307 { 308 unsigned int baud = tty_termios_baud_rate(termios); 309 struct dw8250_data *d = p->private_data; 310 long rate; 311 int ret; 312 313 if (IS_ERR(d->clk)) 314 goto out; 315 316 clk_disable_unprepare(d->clk); 317 rate = clk_round_rate(d->clk, baud * 16); 318 if (rate < 0) 319 ret = rate; 320 else if (rate == 0) 321 ret = -ENOENT; 322 else 323 ret = clk_set_rate(d->clk, rate); 324 clk_prepare_enable(d->clk); 325 326 if (!ret) 327 p->uartclk = rate; 328 329 out: 330 p->status &= ~UPSTAT_AUTOCTS; 331 if (termios->c_cflag & CRTSCTS) 332 p->status |= UPSTAT_AUTOCTS; 333 334 serial8250_do_set_termios(p, termios, old); 335 } 336 337 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios) 338 { 339 struct uart_8250_port *up = up_to_u8250p(p); 340 unsigned int mcr = p->serial_in(p, UART_MCR); 341 342 if (up->capabilities & UART_CAP_IRDA) { 343 if (termios->c_line == N_IRDA) 344 mcr |= DW_UART_MCR_SIRE; 345 else 346 mcr &= ~DW_UART_MCR_SIRE; 347 348 p->serial_out(p, UART_MCR, mcr); 349 } 350 serial8250_do_set_ldisc(p, termios); 351 } 352 353 /* 354 * dw8250_fallback_dma_filter will prevent the UART from getting just any free 355 * channel on platforms that have DMA engines, but don't have any channels 356 * assigned to the UART. 357 * 358 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the 359 * core problem is fixed, this function is no longer needed. 360 */ 361 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param) 362 { 363 return false; 364 } 365 366 static bool dw8250_idma_filter(struct dma_chan *chan, void *param) 367 { 368 return param == chan->device->dev; 369 } 370 371 /* 372 * divisor = div(I) + div(F) 373 * "I" means integer, "F" means fractional 374 * quot = div(I) = clk / (16 * baud) 375 * frac = div(F) * 2^dlf_size 376 * 377 * let rem = clk % (16 * baud) 378 * we have: div(F) * (16 * baud) = rem 379 * so frac = 2^dlf_size * rem / (16 * baud) = (rem << dlf_size) / (16 * baud) 380 */ 381 static unsigned int dw8250_get_divisor(struct uart_port *p, 382 unsigned int baud, 383 unsigned int *frac) 384 { 385 unsigned int quot, rem, base_baud = baud * 16; 386 struct dw8250_data *d = p->private_data; 387 388 quot = p->uartclk / base_baud; 389 rem = p->uartclk % base_baud; 390 *frac = DIV_ROUND_CLOSEST(rem << d->dlf_size, base_baud); 391 392 return quot; 393 } 394 395 static void dw8250_set_divisor(struct uart_port *p, unsigned int baud, 396 unsigned int quot, unsigned int quot_frac) 397 { 398 dw8250_writel_ext(p, DW_UART_DLF, quot_frac); 399 serial8250_do_set_divisor(p, baud, quot, quot_frac); 400 } 401 402 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) 403 { 404 if (p->dev->of_node) { 405 struct device_node *np = p->dev->of_node; 406 int id; 407 408 /* get index of serial line, if found in DT aliases */ 409 id = of_alias_get_id(np, "serial"); 410 if (id >= 0) 411 p->line = id; 412 #ifdef CONFIG_64BIT 413 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 414 p->serial_in = dw8250_serial_inq; 415 p->serial_out = dw8250_serial_outq; 416 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 417 p->type = PORT_OCTEON; 418 data->usr_reg = 0x27; 419 data->skip_autocfg = true; 420 } 421 #endif 422 if (of_device_is_big_endian(p->dev->of_node)) { 423 p->iotype = UPIO_MEM32BE; 424 p->serial_in = dw8250_serial_in32be; 425 p->serial_out = dw8250_serial_out32be; 426 } 427 if (of_device_is_compatible(np, "marvell,armada-38x-uart")) 428 p->serial_out = dw8250_serial_out38x; 429 430 } else if (acpi_dev_present("APMC0D08", NULL, -1)) { 431 p->iotype = UPIO_MEM32; 432 p->regshift = 2; 433 p->serial_in = dw8250_serial_in32; 434 data->uart_16550_compatible = true; 435 } 436 437 /* Platforms with iDMA 64-bit */ 438 if (platform_get_resource_byname(to_platform_device(p->dev), 439 IORESOURCE_MEM, "lpss_priv")) { 440 data->dma.rx_param = p->dev->parent; 441 data->dma.tx_param = p->dev->parent; 442 data->dma.fn = dw8250_idma_filter; 443 } 444 } 445 446 static void dw8250_setup_port(struct uart_port *p) 447 { 448 struct uart_8250_port *up = up_to_u8250p(p); 449 u32 reg; 450 451 /* 452 * If the Component Version Register returns zero, we know that 453 * ADDITIONAL_FEATURES are not enabled. No need to go any further. 454 */ 455 reg = dw8250_readl_ext(p, DW_UART_UCV); 456 if (!reg) 457 return; 458 459 dev_dbg(p->dev, "Designware UART version %c.%c%c\n", 460 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); 461 462 dw8250_writel_ext(p, DW_UART_DLF, ~0U); 463 reg = dw8250_readl_ext(p, DW_UART_DLF); 464 dw8250_writel_ext(p, DW_UART_DLF, 0); 465 466 if (reg) { 467 struct dw8250_data *d = p->private_data; 468 469 d->dlf_size = fls(reg); 470 p->get_divisor = dw8250_get_divisor; 471 p->set_divisor = dw8250_set_divisor; 472 } 473 474 reg = dw8250_readl_ext(p, DW_UART_CPR); 475 if (!reg) 476 return; 477 478 /* Select the type based on fifo */ 479 if (reg & DW_UART_CPR_FIFO_MODE) { 480 p->type = PORT_16550A; 481 p->flags |= UPF_FIXED_TYPE; 482 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); 483 up->capabilities = UART_CAP_FIFO; 484 } 485 486 if (reg & DW_UART_CPR_AFCE_MODE) 487 up->capabilities |= UART_CAP_AFE; 488 489 if (reg & DW_UART_CPR_SIR_MODE) 490 up->capabilities |= UART_CAP_IRDA; 491 } 492 493 static int dw8250_probe(struct platform_device *pdev) 494 { 495 struct uart_8250_port uart = {}; 496 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 497 int irq = platform_get_irq(pdev, 0); 498 struct uart_port *p = &uart.port; 499 struct device *dev = &pdev->dev; 500 struct dw8250_data *data; 501 int err; 502 u32 val; 503 504 if (!regs) { 505 dev_err(dev, "no registers defined\n"); 506 return -EINVAL; 507 } 508 509 if (irq < 0) { 510 if (irq != -EPROBE_DEFER) 511 dev_err(dev, "cannot get irq\n"); 512 return irq; 513 } 514 515 spin_lock_init(&p->lock); 516 p->mapbase = regs->start; 517 p->irq = irq; 518 p->handle_irq = dw8250_handle_irq; 519 p->pm = dw8250_do_pm; 520 p->type = PORT_8250; 521 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; 522 p->dev = dev; 523 p->iotype = UPIO_MEM; 524 p->serial_in = dw8250_serial_in; 525 p->serial_out = dw8250_serial_out; 526 p->set_ldisc = dw8250_set_ldisc; 527 p->set_termios = dw8250_set_termios; 528 529 p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); 530 if (!p->membase) 531 return -ENOMEM; 532 533 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 534 if (!data) 535 return -ENOMEM; 536 537 data->dma.fn = dw8250_fallback_dma_filter; 538 data->usr_reg = DW_UART_USR; 539 p->private_data = data; 540 541 data->uart_16550_compatible = device_property_read_bool(dev, 542 "snps,uart-16550-compatible"); 543 544 err = device_property_read_u32(dev, "reg-shift", &val); 545 if (!err) 546 p->regshift = val; 547 548 err = device_property_read_u32(dev, "reg-io-width", &val); 549 if (!err && val == 4) { 550 p->iotype = UPIO_MEM32; 551 p->serial_in = dw8250_serial_in32; 552 p->serial_out = dw8250_serial_out32; 553 } 554 555 if (device_property_read_bool(dev, "dcd-override")) { 556 /* Always report DCD as active */ 557 data->msr_mask_on |= UART_MSR_DCD; 558 data->msr_mask_off |= UART_MSR_DDCD; 559 } 560 561 if (device_property_read_bool(dev, "dsr-override")) { 562 /* Always report DSR as active */ 563 data->msr_mask_on |= UART_MSR_DSR; 564 data->msr_mask_off |= UART_MSR_DDSR; 565 } 566 567 if (device_property_read_bool(dev, "cts-override")) { 568 /* Always report CTS as active */ 569 data->msr_mask_on |= UART_MSR_CTS; 570 data->msr_mask_off |= UART_MSR_DCTS; 571 } 572 573 if (device_property_read_bool(dev, "ri-override")) { 574 /* Always report Ring indicator as inactive */ 575 data->msr_mask_off |= UART_MSR_RI; 576 data->msr_mask_off |= UART_MSR_TERI; 577 } 578 579 /* Always ask for fixed clock rate from a property. */ 580 device_property_read_u32(dev, "clock-frequency", &p->uartclk); 581 582 /* If there is separate baudclk, get the rate from it. */ 583 data->clk = devm_clk_get(dev, "baudclk"); 584 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) 585 data->clk = devm_clk_get(dev, NULL); 586 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) 587 return -EPROBE_DEFER; 588 if (!IS_ERR_OR_NULL(data->clk)) { 589 err = clk_prepare_enable(data->clk); 590 if (err) 591 dev_warn(dev, "could not enable optional baudclk: %d\n", 592 err); 593 else 594 p->uartclk = clk_get_rate(data->clk); 595 } 596 597 /* If no clock rate is defined, fail. */ 598 if (!p->uartclk) { 599 dev_err(dev, "clock rate not defined\n"); 600 err = -EINVAL; 601 goto err_clk; 602 } 603 604 data->pclk = devm_clk_get(dev, "apb_pclk"); 605 if (IS_ERR(data->pclk) && PTR_ERR(data->pclk) == -EPROBE_DEFER) { 606 err = -EPROBE_DEFER; 607 goto err_clk; 608 } 609 if (!IS_ERR(data->pclk)) { 610 err = clk_prepare_enable(data->pclk); 611 if (err) { 612 dev_err(dev, "could not enable apb_pclk\n"); 613 goto err_clk; 614 } 615 } 616 617 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); 618 if (IS_ERR(data->rst)) { 619 err = PTR_ERR(data->rst); 620 goto err_pclk; 621 } 622 reset_control_deassert(data->rst); 623 624 dw8250_quirks(p, data); 625 626 /* If the Busy Functionality is not implemented, don't handle it */ 627 if (data->uart_16550_compatible) 628 p->handle_irq = NULL; 629 630 if (!data->skip_autocfg) 631 dw8250_setup_port(p); 632 633 /* If we have a valid fifosize, try hooking up DMA */ 634 if (p->fifosize) { 635 data->dma.rxconf.src_maxburst = p->fifosize / 4; 636 data->dma.txconf.dst_maxburst = p->fifosize / 4; 637 uart.dma = &data->dma; 638 } 639 640 data->line = serial8250_register_8250_port(&uart); 641 if (data->line < 0) { 642 err = data->line; 643 goto err_reset; 644 } 645 646 platform_set_drvdata(pdev, data); 647 648 pm_runtime_set_active(dev); 649 pm_runtime_enable(dev); 650 651 return 0; 652 653 err_reset: 654 reset_control_assert(data->rst); 655 656 err_pclk: 657 if (!IS_ERR(data->pclk)) 658 clk_disable_unprepare(data->pclk); 659 660 err_clk: 661 if (!IS_ERR(data->clk)) 662 clk_disable_unprepare(data->clk); 663 664 return err; 665 } 666 667 static int dw8250_remove(struct platform_device *pdev) 668 { 669 struct dw8250_data *data = platform_get_drvdata(pdev); 670 671 pm_runtime_get_sync(&pdev->dev); 672 673 serial8250_unregister_port(data->line); 674 675 reset_control_assert(data->rst); 676 677 if (!IS_ERR(data->pclk)) 678 clk_disable_unprepare(data->pclk); 679 680 if (!IS_ERR(data->clk)) 681 clk_disable_unprepare(data->clk); 682 683 pm_runtime_disable(&pdev->dev); 684 pm_runtime_put_noidle(&pdev->dev); 685 686 return 0; 687 } 688 689 #ifdef CONFIG_PM_SLEEP 690 static int dw8250_suspend(struct device *dev) 691 { 692 struct dw8250_data *data = dev_get_drvdata(dev); 693 694 serial8250_suspend_port(data->line); 695 696 return 0; 697 } 698 699 static int dw8250_resume(struct device *dev) 700 { 701 struct dw8250_data *data = dev_get_drvdata(dev); 702 703 serial8250_resume_port(data->line); 704 705 return 0; 706 } 707 #endif /* CONFIG_PM_SLEEP */ 708 709 #ifdef CONFIG_PM 710 static int dw8250_runtime_suspend(struct device *dev) 711 { 712 struct dw8250_data *data = dev_get_drvdata(dev); 713 714 if (!IS_ERR(data->clk)) 715 clk_disable_unprepare(data->clk); 716 717 if (!IS_ERR(data->pclk)) 718 clk_disable_unprepare(data->pclk); 719 720 return 0; 721 } 722 723 static int dw8250_runtime_resume(struct device *dev) 724 { 725 struct dw8250_data *data = dev_get_drvdata(dev); 726 727 if (!IS_ERR(data->pclk)) 728 clk_prepare_enable(data->pclk); 729 730 if (!IS_ERR(data->clk)) 731 clk_prepare_enable(data->clk); 732 733 return 0; 734 } 735 #endif 736 737 static const struct dev_pm_ops dw8250_pm_ops = { 738 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 739 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 740 }; 741 742 static const struct of_device_id dw8250_of_match[] = { 743 { .compatible = "snps,dw-apb-uart" }, 744 { .compatible = "cavium,octeon-3860-uart" }, 745 { .compatible = "marvell,armada-38x-uart" }, 746 { .compatible = "renesas,rzn1-uart" }, 747 { /* Sentinel */ } 748 }; 749 MODULE_DEVICE_TABLE(of, dw8250_of_match); 750 751 static const struct acpi_device_id dw8250_acpi_match[] = { 752 { "INT33C4", 0 }, 753 { "INT33C5", 0 }, 754 { "INT3434", 0 }, 755 { "INT3435", 0 }, 756 { "80860F0A", 0 }, 757 { "8086228A", 0 }, 758 { "APMC0D08", 0}, 759 { "AMD0020", 0 }, 760 { "AMDI0020", 0 }, 761 { "BRCM2032", 0 }, 762 { "HISI0031", 0 }, 763 { }, 764 }; 765 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 766 767 static struct platform_driver dw8250_platform_driver = { 768 .driver = { 769 .name = "dw-apb-uart", 770 .pm = &dw8250_pm_ops, 771 .of_match_table = dw8250_of_match, 772 .acpi_match_table = ACPI_PTR(dw8250_acpi_match), 773 }, 774 .probe = dw8250_probe, 775 .remove = dw8250_remove, 776 }; 777 778 module_platform_driver(dw8250_platform_driver); 779 780 MODULE_AUTHOR("Jamie Iles"); 781 MODULE_LICENSE("GPL"); 782 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 783 MODULE_ALIAS("platform:dw-apb-uart"); 784