1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Synopsys DesignWare 8250 driver. 4 * 5 * Copyright 2011 Picochip, Jamie Iles. 6 * Copyright 2013 Intel Corporation 7 * 8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 9 * LCR is written whilst busy. If it is, then a busy detect interrupt is 10 * raised, the LCR needs to be rewritten and the uart status register read. 11 */ 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 #include <linux/acpi.h> 24 #include <linux/clk.h> 25 #include <linux/reset.h> 26 #include <linux/pm_runtime.h> 27 28 #include <asm/byteorder.h> 29 30 #include "8250.h" 31 32 /* Offsets for the DesignWare specific registers */ 33 #define DW_UART_USR 0x1f /* UART Status Register */ 34 #define DW_UART_CPR 0xf4 /* Component Parameter Register */ 35 #define DW_UART_UCV 0xf8 /* UART Component Version */ 36 37 /* Component Parameter Register bits */ 38 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) 39 #define DW_UART_CPR_AFCE_MODE (1 << 4) 40 #define DW_UART_CPR_THRE_MODE (1 << 5) 41 #define DW_UART_CPR_SIR_MODE (1 << 6) 42 #define DW_UART_CPR_SIR_LP_MODE (1 << 7) 43 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) 44 #define DW_UART_CPR_FIFO_ACCESS (1 << 9) 45 #define DW_UART_CPR_FIFO_STAT (1 << 10) 46 #define DW_UART_CPR_SHADOW (1 << 11) 47 #define DW_UART_CPR_ENCODED_PARMS (1 << 12) 48 #define DW_UART_CPR_DMA_EXTRA (1 << 13) 49 #define DW_UART_CPR_FIFO_MODE (0xff << 16) 50 /* Helper for fifo size calculation */ 51 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) 52 53 /* DesignWare specific register fields */ 54 #define DW_UART_MCR_SIRE BIT(6) 55 56 struct dw8250_data { 57 u8 usr_reg; 58 int line; 59 int msr_mask_on; 60 int msr_mask_off; 61 struct clk *clk; 62 struct clk *pclk; 63 struct reset_control *rst; 64 struct uart_8250_dma dma; 65 66 unsigned int skip_autocfg:1; 67 unsigned int uart_16550_compatible:1; 68 }; 69 70 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 71 { 72 struct dw8250_data *d = p->private_data; 73 74 /* Override any modem control signals if needed */ 75 if (offset == UART_MSR) { 76 value |= d->msr_mask_on; 77 value &= ~d->msr_mask_off; 78 } 79 80 return value; 81 } 82 83 static void dw8250_force_idle(struct uart_port *p) 84 { 85 struct uart_8250_port *up = up_to_u8250p(p); 86 87 serial8250_clear_and_reinit_fifos(up); 88 (void)p->serial_in(p, UART_RX); 89 } 90 91 static void dw8250_check_lcr(struct uart_port *p, int value) 92 { 93 void __iomem *offset = p->membase + (UART_LCR << p->regshift); 94 int tries = 1000; 95 96 /* Make sure LCR write wasn't ignored */ 97 while (tries--) { 98 unsigned int lcr = p->serial_in(p, UART_LCR); 99 100 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 101 return; 102 103 dw8250_force_idle(p); 104 105 #ifdef CONFIG_64BIT 106 if (p->type == PORT_OCTEON) 107 __raw_writeq(value & 0xff, offset); 108 else 109 #endif 110 if (p->iotype == UPIO_MEM32) 111 writel(value, offset); 112 else if (p->iotype == UPIO_MEM32BE) 113 iowrite32be(value, offset); 114 else 115 writeb(value, offset); 116 } 117 /* 118 * FIXME: this deadlocks if port->lock is already held 119 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 120 */ 121 } 122 123 /* Returns once the transmitter is empty or we run out of retries */ 124 static void dw8250_tx_wait_empty(struct uart_port *p) 125 { 126 unsigned int tries = 20000; 127 unsigned int delay_threshold = tries - 1000; 128 unsigned int lsr; 129 130 while (tries--) { 131 lsr = readb (p->membase + (UART_LSR << p->regshift)); 132 if (lsr & UART_LSR_TEMT) 133 break; 134 135 /* The device is first given a chance to empty without delay, 136 * to avoid slowdowns at high bitrates. If after 1000 tries 137 * the buffer has still not emptied, allow more time for low- 138 * speed links. */ 139 if (tries < delay_threshold) 140 udelay (1); 141 } 142 } 143 144 static void dw8250_serial_out38x(struct uart_port *p, int offset, int value) 145 { 146 struct dw8250_data *d = p->private_data; 147 148 /* Allow the TX to drain before we reconfigure */ 149 if (offset == UART_LCR) 150 dw8250_tx_wait_empty(p); 151 152 writeb(value, p->membase + (offset << p->regshift)); 153 154 if (offset == UART_LCR && !d->uart_16550_compatible) 155 dw8250_check_lcr(p, value); 156 } 157 158 159 static void dw8250_serial_out(struct uart_port *p, int offset, int value) 160 { 161 struct dw8250_data *d = p->private_data; 162 163 writeb(value, p->membase + (offset << p->regshift)); 164 165 if (offset == UART_LCR && !d->uart_16550_compatible) 166 dw8250_check_lcr(p, value); 167 } 168 169 static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 170 { 171 unsigned int value = readb(p->membase + (offset << p->regshift)); 172 173 return dw8250_modify_msr(p, offset, value); 174 } 175 176 #ifdef CONFIG_64BIT 177 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) 178 { 179 unsigned int value; 180 181 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); 182 183 return dw8250_modify_msr(p, offset, value); 184 } 185 186 static void dw8250_serial_outq(struct uart_port *p, int offset, int value) 187 { 188 struct dw8250_data *d = p->private_data; 189 190 value &= 0xff; 191 __raw_writeq(value, p->membase + (offset << p->regshift)); 192 /* Read back to ensure register write ordering. */ 193 __raw_readq(p->membase + (UART_LCR << p->regshift)); 194 195 if (offset == UART_LCR && !d->uart_16550_compatible) 196 dw8250_check_lcr(p, value); 197 } 198 #endif /* CONFIG_64BIT */ 199 200 static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 201 { 202 struct dw8250_data *d = p->private_data; 203 204 writel(value, p->membase + (offset << p->regshift)); 205 206 if (offset == UART_LCR && !d->uart_16550_compatible) 207 dw8250_check_lcr(p, value); 208 } 209 210 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 211 { 212 unsigned int value = readl(p->membase + (offset << p->regshift)); 213 214 return dw8250_modify_msr(p, offset, value); 215 } 216 217 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value) 218 { 219 struct dw8250_data *d = p->private_data; 220 221 iowrite32be(value, p->membase + (offset << p->regshift)); 222 223 if (offset == UART_LCR && !d->uart_16550_compatible) 224 dw8250_check_lcr(p, value); 225 } 226 227 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) 228 { 229 unsigned int value = ioread32be(p->membase + (offset << p->regshift)); 230 231 return dw8250_modify_msr(p, offset, value); 232 } 233 234 235 static int dw8250_handle_irq(struct uart_port *p) 236 { 237 struct uart_8250_port *up = up_to_u8250p(p); 238 struct dw8250_data *d = p->private_data; 239 unsigned int iir = p->serial_in(p, UART_IIR); 240 unsigned int status; 241 unsigned long flags; 242 243 /* 244 * There are ways to get Designware-based UARTs into a state where 245 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual 246 * data available. If we see such a case then we'll do a bogus 247 * read. If we don't do this then the "RX TIMEOUT" interrupt will 248 * fire forever. 249 * 250 * This problem has only been observed so far when not in DMA mode 251 * so we limit the workaround only to non-DMA mode. 252 */ 253 if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) { 254 spin_lock_irqsave(&p->lock, flags); 255 status = p->serial_in(p, UART_LSR); 256 257 if (!(status & (UART_LSR_DR | UART_LSR_BI))) 258 (void) p->serial_in(p, UART_RX); 259 260 spin_unlock_irqrestore(&p->lock, flags); 261 } 262 263 if (serial8250_handle_irq(p, iir)) 264 return 1; 265 266 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 267 /* Clear the USR */ 268 (void)p->serial_in(p, d->usr_reg); 269 270 return 1; 271 } 272 273 return 0; 274 } 275 276 static void 277 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 278 { 279 if (!state) 280 pm_runtime_get_sync(port->dev); 281 282 serial8250_do_pm(port, state, old); 283 284 if (state) 285 pm_runtime_put_sync_suspend(port->dev); 286 } 287 288 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, 289 struct ktermios *old) 290 { 291 unsigned int baud = tty_termios_baud_rate(termios); 292 struct dw8250_data *d = p->private_data; 293 long rate; 294 int ret; 295 296 if (IS_ERR(d->clk) || !old) 297 goto out; 298 299 clk_disable_unprepare(d->clk); 300 rate = clk_round_rate(d->clk, baud * 16); 301 if (rate < 0) 302 ret = rate; 303 else if (rate == 0) 304 ret = -ENOENT; 305 else 306 ret = clk_set_rate(d->clk, rate); 307 clk_prepare_enable(d->clk); 308 309 if (!ret) 310 p->uartclk = rate; 311 312 out: 313 p->status &= ~UPSTAT_AUTOCTS; 314 if (termios->c_cflag & CRTSCTS) 315 p->status |= UPSTAT_AUTOCTS; 316 317 serial8250_do_set_termios(p, termios, old); 318 } 319 320 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios) 321 { 322 struct uart_8250_port *up = up_to_u8250p(p); 323 unsigned int mcr = p->serial_in(p, UART_MCR); 324 325 if (up->capabilities & UART_CAP_IRDA) { 326 if (termios->c_line == N_IRDA) 327 mcr |= DW_UART_MCR_SIRE; 328 else 329 mcr &= ~DW_UART_MCR_SIRE; 330 331 p->serial_out(p, UART_MCR, mcr); 332 } 333 serial8250_do_set_ldisc(p, termios); 334 } 335 336 /* 337 * dw8250_fallback_dma_filter will prevent the UART from getting just any free 338 * channel on platforms that have DMA engines, but don't have any channels 339 * assigned to the UART. 340 * 341 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the 342 * core problem is fixed, this function is no longer needed. 343 */ 344 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param) 345 { 346 return false; 347 } 348 349 static bool dw8250_idma_filter(struct dma_chan *chan, void *param) 350 { 351 return param == chan->device->dev->parent; 352 } 353 354 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) 355 { 356 if (p->dev->of_node) { 357 struct device_node *np = p->dev->of_node; 358 int id; 359 360 /* get index of serial line, if found in DT aliases */ 361 id = of_alias_get_id(np, "serial"); 362 if (id >= 0) 363 p->line = id; 364 #ifdef CONFIG_64BIT 365 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 366 p->serial_in = dw8250_serial_inq; 367 p->serial_out = dw8250_serial_outq; 368 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 369 p->type = PORT_OCTEON; 370 data->usr_reg = 0x27; 371 data->skip_autocfg = true; 372 } 373 #endif 374 if (of_device_is_big_endian(p->dev->of_node)) { 375 p->iotype = UPIO_MEM32BE; 376 p->serial_in = dw8250_serial_in32be; 377 p->serial_out = dw8250_serial_out32be; 378 } 379 if (of_device_is_compatible(np, "marvell,armada-38x-uart")) 380 p->serial_out = dw8250_serial_out38x; 381 382 } else if (acpi_dev_present("APMC0D08", NULL, -1)) { 383 p->iotype = UPIO_MEM32; 384 p->regshift = 2; 385 p->serial_in = dw8250_serial_in32; 386 data->uart_16550_compatible = true; 387 } 388 389 /* Platforms with iDMA */ 390 if (platform_get_resource_byname(to_platform_device(p->dev), 391 IORESOURCE_MEM, "lpss_priv")) { 392 data->dma.rx_param = p->dev->parent; 393 data->dma.tx_param = p->dev->parent; 394 data->dma.fn = dw8250_idma_filter; 395 } 396 } 397 398 static void dw8250_setup_port(struct uart_port *p) 399 { 400 struct uart_8250_port *up = up_to_u8250p(p); 401 u32 reg; 402 403 /* 404 * If the Component Version Register returns zero, we know that 405 * ADDITIONAL_FEATURES are not enabled. No need to go any further. 406 */ 407 if (p->iotype == UPIO_MEM32BE) 408 reg = ioread32be(p->membase + DW_UART_UCV); 409 else 410 reg = readl(p->membase + DW_UART_UCV); 411 if (!reg) 412 return; 413 414 dev_dbg(p->dev, "Designware UART version %c.%c%c\n", 415 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); 416 417 if (p->iotype == UPIO_MEM32BE) 418 reg = ioread32be(p->membase + DW_UART_CPR); 419 else 420 reg = readl(p->membase + DW_UART_CPR); 421 if (!reg) 422 return; 423 424 /* Select the type based on fifo */ 425 if (reg & DW_UART_CPR_FIFO_MODE) { 426 p->type = PORT_16550A; 427 p->flags |= UPF_FIXED_TYPE; 428 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); 429 up->capabilities = UART_CAP_FIFO; 430 } 431 432 if (reg & DW_UART_CPR_AFCE_MODE) 433 up->capabilities |= UART_CAP_AFE; 434 435 if (reg & DW_UART_CPR_SIR_MODE) 436 up->capabilities |= UART_CAP_IRDA; 437 } 438 439 static int dw8250_probe(struct platform_device *pdev) 440 { 441 struct uart_8250_port uart = {}; 442 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 443 int irq = platform_get_irq(pdev, 0); 444 struct uart_port *p = &uart.port; 445 struct device *dev = &pdev->dev; 446 struct dw8250_data *data; 447 int err; 448 u32 val; 449 450 if (!regs) { 451 dev_err(dev, "no registers defined\n"); 452 return -EINVAL; 453 } 454 455 if (irq < 0) { 456 if (irq != -EPROBE_DEFER) 457 dev_err(dev, "cannot get irq\n"); 458 return irq; 459 } 460 461 spin_lock_init(&p->lock); 462 p->mapbase = regs->start; 463 p->irq = irq; 464 p->handle_irq = dw8250_handle_irq; 465 p->pm = dw8250_do_pm; 466 p->type = PORT_8250; 467 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; 468 p->dev = dev; 469 p->iotype = UPIO_MEM; 470 p->serial_in = dw8250_serial_in; 471 p->serial_out = dw8250_serial_out; 472 p->set_ldisc = dw8250_set_ldisc; 473 p->set_termios = dw8250_set_termios; 474 475 p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); 476 if (!p->membase) 477 return -ENOMEM; 478 479 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 480 if (!data) 481 return -ENOMEM; 482 483 data->dma.fn = dw8250_fallback_dma_filter; 484 data->usr_reg = DW_UART_USR; 485 p->private_data = data; 486 487 data->uart_16550_compatible = device_property_read_bool(dev, 488 "snps,uart-16550-compatible"); 489 490 err = device_property_read_u32(dev, "reg-shift", &val); 491 if (!err) 492 p->regshift = val; 493 494 err = device_property_read_u32(dev, "reg-io-width", &val); 495 if (!err && val == 4) { 496 p->iotype = UPIO_MEM32; 497 p->serial_in = dw8250_serial_in32; 498 p->serial_out = dw8250_serial_out32; 499 } 500 501 if (device_property_read_bool(dev, "dcd-override")) { 502 /* Always report DCD as active */ 503 data->msr_mask_on |= UART_MSR_DCD; 504 data->msr_mask_off |= UART_MSR_DDCD; 505 } 506 507 if (device_property_read_bool(dev, "dsr-override")) { 508 /* Always report DSR as active */ 509 data->msr_mask_on |= UART_MSR_DSR; 510 data->msr_mask_off |= UART_MSR_DDSR; 511 } 512 513 if (device_property_read_bool(dev, "cts-override")) { 514 /* Always report CTS as active */ 515 data->msr_mask_on |= UART_MSR_CTS; 516 data->msr_mask_off |= UART_MSR_DCTS; 517 } 518 519 if (device_property_read_bool(dev, "ri-override")) { 520 /* Always report Ring indicator as inactive */ 521 data->msr_mask_off |= UART_MSR_RI; 522 data->msr_mask_off |= UART_MSR_TERI; 523 } 524 525 /* Always ask for fixed clock rate from a property. */ 526 device_property_read_u32(dev, "clock-frequency", &p->uartclk); 527 528 /* If there is separate baudclk, get the rate from it. */ 529 data->clk = devm_clk_get(dev, "baudclk"); 530 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) 531 data->clk = devm_clk_get(dev, NULL); 532 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) 533 return -EPROBE_DEFER; 534 if (!IS_ERR_OR_NULL(data->clk)) { 535 err = clk_prepare_enable(data->clk); 536 if (err) 537 dev_warn(dev, "could not enable optional baudclk: %d\n", 538 err); 539 else 540 p->uartclk = clk_get_rate(data->clk); 541 } 542 543 /* If no clock rate is defined, fail. */ 544 if (!p->uartclk) { 545 dev_err(dev, "clock rate not defined\n"); 546 err = -EINVAL; 547 goto err_clk; 548 } 549 550 data->pclk = devm_clk_get(dev, "apb_pclk"); 551 if (IS_ERR(data->pclk) && PTR_ERR(data->pclk) == -EPROBE_DEFER) { 552 err = -EPROBE_DEFER; 553 goto err_clk; 554 } 555 if (!IS_ERR(data->pclk)) { 556 err = clk_prepare_enable(data->pclk); 557 if (err) { 558 dev_err(dev, "could not enable apb_pclk\n"); 559 goto err_clk; 560 } 561 } 562 563 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); 564 if (IS_ERR(data->rst)) { 565 err = PTR_ERR(data->rst); 566 goto err_pclk; 567 } 568 reset_control_deassert(data->rst); 569 570 dw8250_quirks(p, data); 571 572 /* If the Busy Functionality is not implemented, don't handle it */ 573 if (data->uart_16550_compatible) 574 p->handle_irq = NULL; 575 576 if (!data->skip_autocfg) 577 dw8250_setup_port(p); 578 579 #ifdef CONFIG_PM 580 uart.capabilities |= UART_CAP_RPM; 581 #endif 582 583 /* If we have a valid fifosize, try hooking up DMA */ 584 if (p->fifosize) { 585 data->dma.rxconf.src_maxburst = p->fifosize / 4; 586 data->dma.txconf.dst_maxburst = p->fifosize / 4; 587 uart.dma = &data->dma; 588 } 589 590 data->line = serial8250_register_8250_port(&uart); 591 if (data->line < 0) { 592 err = data->line; 593 goto err_reset; 594 } 595 596 platform_set_drvdata(pdev, data); 597 598 pm_runtime_set_active(dev); 599 pm_runtime_enable(dev); 600 601 return 0; 602 603 err_reset: 604 reset_control_assert(data->rst); 605 606 err_pclk: 607 if (!IS_ERR(data->pclk)) 608 clk_disable_unprepare(data->pclk); 609 610 err_clk: 611 if (!IS_ERR(data->clk)) 612 clk_disable_unprepare(data->clk); 613 614 return err; 615 } 616 617 static int dw8250_remove(struct platform_device *pdev) 618 { 619 struct dw8250_data *data = platform_get_drvdata(pdev); 620 621 pm_runtime_get_sync(&pdev->dev); 622 623 serial8250_unregister_port(data->line); 624 625 reset_control_assert(data->rst); 626 627 if (!IS_ERR(data->pclk)) 628 clk_disable_unprepare(data->pclk); 629 630 if (!IS_ERR(data->clk)) 631 clk_disable_unprepare(data->clk); 632 633 pm_runtime_disable(&pdev->dev); 634 pm_runtime_put_noidle(&pdev->dev); 635 636 return 0; 637 } 638 639 #ifdef CONFIG_PM_SLEEP 640 static int dw8250_suspend(struct device *dev) 641 { 642 struct dw8250_data *data = dev_get_drvdata(dev); 643 644 serial8250_suspend_port(data->line); 645 646 return 0; 647 } 648 649 static int dw8250_resume(struct device *dev) 650 { 651 struct dw8250_data *data = dev_get_drvdata(dev); 652 653 serial8250_resume_port(data->line); 654 655 return 0; 656 } 657 #endif /* CONFIG_PM_SLEEP */ 658 659 #ifdef CONFIG_PM 660 static int dw8250_runtime_suspend(struct device *dev) 661 { 662 struct dw8250_data *data = dev_get_drvdata(dev); 663 664 if (!IS_ERR(data->clk)) 665 clk_disable_unprepare(data->clk); 666 667 if (!IS_ERR(data->pclk)) 668 clk_disable_unprepare(data->pclk); 669 670 return 0; 671 } 672 673 static int dw8250_runtime_resume(struct device *dev) 674 { 675 struct dw8250_data *data = dev_get_drvdata(dev); 676 677 if (!IS_ERR(data->pclk)) 678 clk_prepare_enable(data->pclk); 679 680 if (!IS_ERR(data->clk)) 681 clk_prepare_enable(data->clk); 682 683 return 0; 684 } 685 #endif 686 687 static const struct dev_pm_ops dw8250_pm_ops = { 688 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 689 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 690 }; 691 692 static const struct of_device_id dw8250_of_match[] = { 693 { .compatible = "snps,dw-apb-uart" }, 694 { .compatible = "cavium,octeon-3860-uart" }, 695 { .compatible = "marvell,armada-38x-uart" }, 696 { /* Sentinel */ } 697 }; 698 MODULE_DEVICE_TABLE(of, dw8250_of_match); 699 700 static const struct acpi_device_id dw8250_acpi_match[] = { 701 { "INT33C4", 0 }, 702 { "INT33C5", 0 }, 703 { "INT3434", 0 }, 704 { "INT3435", 0 }, 705 { "80860F0A", 0 }, 706 { "8086228A", 0 }, 707 { "APMC0D08", 0}, 708 { "AMD0020", 0 }, 709 { "AMDI0020", 0 }, 710 { "HISI0031", 0 }, 711 { }, 712 }; 713 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 714 715 static struct platform_driver dw8250_platform_driver = { 716 .driver = { 717 .name = "dw-apb-uart", 718 .pm = &dw8250_pm_ops, 719 .of_match_table = dw8250_of_match, 720 .acpi_match_table = ACPI_PTR(dw8250_acpi_match), 721 }, 722 .probe = dw8250_probe, 723 .remove = dw8250_remove, 724 }; 725 726 module_platform_driver(dw8250_platform_driver); 727 728 MODULE_AUTHOR("Jamie Iles"); 729 MODULE_LICENSE("GPL"); 730 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 731 MODULE_ALIAS("platform:dw-apb-uart"); 732