1 /* 2 * Synopsys DesignWare 8250 driver. 3 * 4 * Copyright 2011 Picochip, Jamie Iles. 5 * Copyright 2013 Intel Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 13 * LCR is written whilst busy. If it is, then a busy detect interrupt is 14 * raised, the LCR needs to be rewritten and the uart status register read. 15 */ 16 #include <linux/device.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/serial_8250.h> 20 #include <linux/serial_reg.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/slab.h> 26 #include <linux/acpi.h> 27 #include <linux/clk.h> 28 #include <linux/reset.h> 29 #include <linux/pm_runtime.h> 30 31 #include <asm/byteorder.h> 32 33 #include "8250.h" 34 35 /* Offsets for the DesignWare specific registers */ 36 #define DW_UART_USR 0x1f /* UART Status Register */ 37 #define DW_UART_CPR 0xf4 /* Component Parameter Register */ 38 #define DW_UART_UCV 0xf8 /* UART Component Version */ 39 40 /* Component Parameter Register bits */ 41 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) 42 #define DW_UART_CPR_AFCE_MODE (1 << 4) 43 #define DW_UART_CPR_THRE_MODE (1 << 5) 44 #define DW_UART_CPR_SIR_MODE (1 << 6) 45 #define DW_UART_CPR_SIR_LP_MODE (1 << 7) 46 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) 47 #define DW_UART_CPR_FIFO_ACCESS (1 << 9) 48 #define DW_UART_CPR_FIFO_STAT (1 << 10) 49 #define DW_UART_CPR_SHADOW (1 << 11) 50 #define DW_UART_CPR_ENCODED_PARMS (1 << 12) 51 #define DW_UART_CPR_DMA_EXTRA (1 << 13) 52 #define DW_UART_CPR_FIFO_MODE (0xff << 16) 53 /* Helper for fifo size calculation */ 54 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) 55 56 /* DesignWare specific register fields */ 57 #define DW_UART_MCR_SIRE BIT(6) 58 59 struct dw8250_data { 60 u8 usr_reg; 61 int line; 62 int msr_mask_on; 63 int msr_mask_off; 64 struct clk *clk; 65 struct clk *pclk; 66 struct reset_control *rst; 67 struct uart_8250_dma dma; 68 69 unsigned int skip_autocfg:1; 70 unsigned int uart_16550_compatible:1; 71 }; 72 73 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 74 { 75 struct dw8250_data *d = p->private_data; 76 77 /* Override any modem control signals if needed */ 78 if (offset == UART_MSR) { 79 value |= d->msr_mask_on; 80 value &= ~d->msr_mask_off; 81 } 82 83 return value; 84 } 85 86 static void dw8250_force_idle(struct uart_port *p) 87 { 88 struct uart_8250_port *up = up_to_u8250p(p); 89 90 serial8250_clear_and_reinit_fifos(up); 91 (void)p->serial_in(p, UART_RX); 92 } 93 94 static void dw8250_check_lcr(struct uart_port *p, int value) 95 { 96 void __iomem *offset = p->membase + (UART_LCR << p->regshift); 97 int tries = 1000; 98 99 /* Make sure LCR write wasn't ignored */ 100 while (tries--) { 101 unsigned int lcr = p->serial_in(p, UART_LCR); 102 103 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 104 return; 105 106 dw8250_force_idle(p); 107 108 #ifdef CONFIG_64BIT 109 if (p->type == PORT_OCTEON) 110 __raw_writeq(value & 0xff, offset); 111 else 112 #endif 113 if (p->iotype == UPIO_MEM32) 114 writel(value, offset); 115 else if (p->iotype == UPIO_MEM32BE) 116 iowrite32be(value, offset); 117 else 118 writeb(value, offset); 119 } 120 /* 121 * FIXME: this deadlocks if port->lock is already held 122 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 123 */ 124 } 125 126 static void dw8250_serial_out(struct uart_port *p, int offset, int value) 127 { 128 struct dw8250_data *d = p->private_data; 129 130 writeb(value, p->membase + (offset << p->regshift)); 131 132 if (offset == UART_LCR && !d->uart_16550_compatible) 133 dw8250_check_lcr(p, value); 134 } 135 136 static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 137 { 138 unsigned int value = readb(p->membase + (offset << p->regshift)); 139 140 return dw8250_modify_msr(p, offset, value); 141 } 142 143 #ifdef CONFIG_64BIT 144 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) 145 { 146 unsigned int value; 147 148 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); 149 150 return dw8250_modify_msr(p, offset, value); 151 } 152 153 static void dw8250_serial_outq(struct uart_port *p, int offset, int value) 154 { 155 struct dw8250_data *d = p->private_data; 156 157 value &= 0xff; 158 __raw_writeq(value, p->membase + (offset << p->regshift)); 159 /* Read back to ensure register write ordering. */ 160 __raw_readq(p->membase + (UART_LCR << p->regshift)); 161 162 if (offset == UART_LCR && !d->uart_16550_compatible) 163 dw8250_check_lcr(p, value); 164 } 165 #endif /* CONFIG_64BIT */ 166 167 static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 168 { 169 struct dw8250_data *d = p->private_data; 170 171 writel(value, p->membase + (offset << p->regshift)); 172 173 if (offset == UART_LCR && !d->uart_16550_compatible) 174 dw8250_check_lcr(p, value); 175 } 176 177 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 178 { 179 unsigned int value = readl(p->membase + (offset << p->regshift)); 180 181 return dw8250_modify_msr(p, offset, value); 182 } 183 184 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value) 185 { 186 struct dw8250_data *d = p->private_data; 187 188 iowrite32be(value, p->membase + (offset << p->regshift)); 189 190 if (offset == UART_LCR && !d->uart_16550_compatible) 191 dw8250_check_lcr(p, value); 192 } 193 194 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) 195 { 196 unsigned int value = ioread32be(p->membase + (offset << p->regshift)); 197 198 return dw8250_modify_msr(p, offset, value); 199 } 200 201 202 static int dw8250_handle_irq(struct uart_port *p) 203 { 204 struct dw8250_data *d = p->private_data; 205 unsigned int iir = p->serial_in(p, UART_IIR); 206 207 if (serial8250_handle_irq(p, iir)) 208 return 1; 209 210 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 211 /* Clear the USR */ 212 (void)p->serial_in(p, d->usr_reg); 213 214 return 1; 215 } 216 217 return 0; 218 } 219 220 static void 221 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 222 { 223 if (!state) 224 pm_runtime_get_sync(port->dev); 225 226 serial8250_do_pm(port, state, old); 227 228 if (state) 229 pm_runtime_put_sync_suspend(port->dev); 230 } 231 232 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, 233 struct ktermios *old) 234 { 235 unsigned int baud = tty_termios_baud_rate(termios); 236 struct dw8250_data *d = p->private_data; 237 unsigned int rate; 238 int ret; 239 240 if (IS_ERR(d->clk) || !old) 241 goto out; 242 243 clk_disable_unprepare(d->clk); 244 rate = clk_round_rate(d->clk, baud * 16); 245 ret = clk_set_rate(d->clk, rate); 246 clk_prepare_enable(d->clk); 247 248 if (!ret) 249 p->uartclk = rate; 250 251 p->status &= ~UPSTAT_AUTOCTS; 252 if (termios->c_cflag & CRTSCTS) 253 p->status |= UPSTAT_AUTOCTS; 254 255 out: 256 serial8250_do_set_termios(p, termios, old); 257 } 258 259 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios) 260 { 261 struct uart_8250_port *up = up_to_u8250p(p); 262 unsigned int mcr = p->serial_in(p, UART_MCR); 263 264 if (up->capabilities & UART_CAP_IRDA) { 265 if (termios->c_line == N_IRDA) 266 mcr |= DW_UART_MCR_SIRE; 267 else 268 mcr &= ~DW_UART_MCR_SIRE; 269 270 p->serial_out(p, UART_MCR, mcr); 271 } 272 serial8250_do_set_ldisc(p, termios); 273 } 274 275 /* 276 * dw8250_fallback_dma_filter will prevent the UART from getting just any free 277 * channel on platforms that have DMA engines, but don't have any channels 278 * assigned to the UART. 279 * 280 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the 281 * core problem is fixed, this function is no longer needed. 282 */ 283 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param) 284 { 285 return false; 286 } 287 288 static bool dw8250_idma_filter(struct dma_chan *chan, void *param) 289 { 290 return param == chan->device->dev->parent; 291 } 292 293 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) 294 { 295 if (p->dev->of_node) { 296 struct device_node *np = p->dev->of_node; 297 int id; 298 299 /* get index of serial line, if found in DT aliases */ 300 id = of_alias_get_id(np, "serial"); 301 if (id >= 0) 302 p->line = id; 303 #ifdef CONFIG_64BIT 304 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 305 p->serial_in = dw8250_serial_inq; 306 p->serial_out = dw8250_serial_outq; 307 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 308 p->type = PORT_OCTEON; 309 data->usr_reg = 0x27; 310 data->skip_autocfg = true; 311 } 312 #endif 313 if (of_device_is_big_endian(p->dev->of_node)) { 314 p->iotype = UPIO_MEM32BE; 315 p->serial_in = dw8250_serial_in32be; 316 p->serial_out = dw8250_serial_out32be; 317 } 318 } else if (has_acpi_companion(p->dev)) { 319 const struct acpi_device_id *id; 320 321 id = acpi_match_device(p->dev->driver->acpi_match_table, 322 p->dev); 323 if (id && !strcmp(id->id, "APMC0D08")) { 324 p->iotype = UPIO_MEM32; 325 p->regshift = 2; 326 p->serial_in = dw8250_serial_in32; 327 data->uart_16550_compatible = true; 328 } 329 p->set_termios = dw8250_set_termios; 330 } 331 332 /* Platforms with iDMA */ 333 if (platform_get_resource_byname(to_platform_device(p->dev), 334 IORESOURCE_MEM, "lpss_priv")) { 335 p->set_termios = dw8250_set_termios; 336 data->dma.rx_param = p->dev->parent; 337 data->dma.tx_param = p->dev->parent; 338 data->dma.fn = dw8250_idma_filter; 339 } 340 } 341 342 static void dw8250_setup_port(struct uart_port *p) 343 { 344 struct uart_8250_port *up = up_to_u8250p(p); 345 u32 reg; 346 347 /* 348 * If the Component Version Register returns zero, we know that 349 * ADDITIONAL_FEATURES are not enabled. No need to go any further. 350 */ 351 if (p->iotype == UPIO_MEM32BE) 352 reg = ioread32be(p->membase + DW_UART_UCV); 353 else 354 reg = readl(p->membase + DW_UART_UCV); 355 if (!reg) 356 return; 357 358 dev_dbg(p->dev, "Designware UART version %c.%c%c\n", 359 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); 360 361 if (p->iotype == UPIO_MEM32BE) 362 reg = ioread32be(p->membase + DW_UART_CPR); 363 else 364 reg = readl(p->membase + DW_UART_CPR); 365 if (!reg) 366 return; 367 368 /* Select the type based on fifo */ 369 if (reg & DW_UART_CPR_FIFO_MODE) { 370 p->type = PORT_16550A; 371 p->flags |= UPF_FIXED_TYPE; 372 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); 373 up->capabilities = UART_CAP_FIFO; 374 } 375 376 if (reg & DW_UART_CPR_AFCE_MODE) 377 up->capabilities |= UART_CAP_AFE; 378 379 if (reg & DW_UART_CPR_SIR_MODE) 380 up->capabilities |= UART_CAP_IRDA; 381 } 382 383 static int dw8250_probe(struct platform_device *pdev) 384 { 385 struct uart_8250_port uart = {}; 386 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 387 int irq = platform_get_irq(pdev, 0); 388 struct uart_port *p = &uart.port; 389 struct device *dev = &pdev->dev; 390 struct dw8250_data *data; 391 int err; 392 u32 val; 393 394 if (!regs) { 395 dev_err(dev, "no registers defined\n"); 396 return -EINVAL; 397 } 398 399 if (irq < 0) { 400 if (irq != -EPROBE_DEFER) 401 dev_err(dev, "cannot get irq\n"); 402 return irq; 403 } 404 405 spin_lock_init(&p->lock); 406 p->mapbase = regs->start; 407 p->irq = irq; 408 p->handle_irq = dw8250_handle_irq; 409 p->pm = dw8250_do_pm; 410 p->type = PORT_8250; 411 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; 412 p->dev = dev; 413 p->iotype = UPIO_MEM; 414 p->serial_in = dw8250_serial_in; 415 p->serial_out = dw8250_serial_out; 416 p->set_ldisc = dw8250_set_ldisc; 417 418 p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); 419 if (!p->membase) 420 return -ENOMEM; 421 422 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 423 if (!data) 424 return -ENOMEM; 425 426 data->dma.fn = dw8250_fallback_dma_filter; 427 data->usr_reg = DW_UART_USR; 428 p->private_data = data; 429 430 data->uart_16550_compatible = device_property_read_bool(dev, 431 "snps,uart-16550-compatible"); 432 433 err = device_property_read_u32(dev, "reg-shift", &val); 434 if (!err) 435 p->regshift = val; 436 437 err = device_property_read_u32(dev, "reg-io-width", &val); 438 if (!err && val == 4) { 439 p->iotype = UPIO_MEM32; 440 p->serial_in = dw8250_serial_in32; 441 p->serial_out = dw8250_serial_out32; 442 } 443 444 if (device_property_read_bool(dev, "dcd-override")) { 445 /* Always report DCD as active */ 446 data->msr_mask_on |= UART_MSR_DCD; 447 data->msr_mask_off |= UART_MSR_DDCD; 448 } 449 450 if (device_property_read_bool(dev, "dsr-override")) { 451 /* Always report DSR as active */ 452 data->msr_mask_on |= UART_MSR_DSR; 453 data->msr_mask_off |= UART_MSR_DDSR; 454 } 455 456 if (device_property_read_bool(dev, "cts-override")) { 457 /* Always report CTS as active */ 458 data->msr_mask_on |= UART_MSR_CTS; 459 data->msr_mask_off |= UART_MSR_DCTS; 460 } 461 462 if (device_property_read_bool(dev, "ri-override")) { 463 /* Always report Ring indicator as inactive */ 464 data->msr_mask_off |= UART_MSR_RI; 465 data->msr_mask_off |= UART_MSR_TERI; 466 } 467 468 /* Always ask for fixed clock rate from a property. */ 469 device_property_read_u32(dev, "clock-frequency", &p->uartclk); 470 471 /* If there is separate baudclk, get the rate from it. */ 472 data->clk = devm_clk_get(dev, "baudclk"); 473 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) 474 data->clk = devm_clk_get(dev, NULL); 475 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) 476 return -EPROBE_DEFER; 477 if (!IS_ERR_OR_NULL(data->clk)) { 478 err = clk_prepare_enable(data->clk); 479 if (err) 480 dev_warn(dev, "could not enable optional baudclk: %d\n", 481 err); 482 else 483 p->uartclk = clk_get_rate(data->clk); 484 } 485 486 /* If no clock rate is defined, fail. */ 487 if (!p->uartclk) { 488 dev_err(dev, "clock rate not defined\n"); 489 return -EINVAL; 490 } 491 492 data->pclk = devm_clk_get(dev, "apb_pclk"); 493 if (IS_ERR(data->pclk) && PTR_ERR(data->pclk) == -EPROBE_DEFER) { 494 err = -EPROBE_DEFER; 495 goto err_clk; 496 } 497 if (!IS_ERR(data->pclk)) { 498 err = clk_prepare_enable(data->pclk); 499 if (err) { 500 dev_err(dev, "could not enable apb_pclk\n"); 501 goto err_clk; 502 } 503 } 504 505 data->rst = devm_reset_control_get_optional(dev, NULL); 506 if (IS_ERR(data->rst) && PTR_ERR(data->rst) == -EPROBE_DEFER) { 507 err = -EPROBE_DEFER; 508 goto err_pclk; 509 } 510 if (!IS_ERR(data->rst)) 511 reset_control_deassert(data->rst); 512 513 dw8250_quirks(p, data); 514 515 /* If the Busy Functionality is not implemented, don't handle it */ 516 if (data->uart_16550_compatible) 517 p->handle_irq = NULL; 518 519 if (!data->skip_autocfg) 520 dw8250_setup_port(p); 521 522 /* If we have a valid fifosize, try hooking up DMA */ 523 if (p->fifosize) { 524 data->dma.rxconf.src_maxburst = p->fifosize / 4; 525 data->dma.txconf.dst_maxburst = p->fifosize / 4; 526 uart.dma = &data->dma; 527 } 528 529 data->line = serial8250_register_8250_port(&uart); 530 if (data->line < 0) { 531 err = data->line; 532 goto err_reset; 533 } 534 535 platform_set_drvdata(pdev, data); 536 537 pm_runtime_set_active(dev); 538 pm_runtime_enable(dev); 539 540 return 0; 541 542 err_reset: 543 if (!IS_ERR(data->rst)) 544 reset_control_assert(data->rst); 545 546 err_pclk: 547 if (!IS_ERR(data->pclk)) 548 clk_disable_unprepare(data->pclk); 549 550 err_clk: 551 if (!IS_ERR(data->clk)) 552 clk_disable_unprepare(data->clk); 553 554 return err; 555 } 556 557 static int dw8250_remove(struct platform_device *pdev) 558 { 559 struct dw8250_data *data = platform_get_drvdata(pdev); 560 561 pm_runtime_get_sync(&pdev->dev); 562 563 serial8250_unregister_port(data->line); 564 565 if (!IS_ERR(data->rst)) 566 reset_control_assert(data->rst); 567 568 if (!IS_ERR(data->pclk)) 569 clk_disable_unprepare(data->pclk); 570 571 if (!IS_ERR(data->clk)) 572 clk_disable_unprepare(data->clk); 573 574 pm_runtime_disable(&pdev->dev); 575 pm_runtime_put_noidle(&pdev->dev); 576 577 return 0; 578 } 579 580 #ifdef CONFIG_PM_SLEEP 581 static int dw8250_suspend(struct device *dev) 582 { 583 struct dw8250_data *data = dev_get_drvdata(dev); 584 585 serial8250_suspend_port(data->line); 586 587 return 0; 588 } 589 590 static int dw8250_resume(struct device *dev) 591 { 592 struct dw8250_data *data = dev_get_drvdata(dev); 593 594 serial8250_resume_port(data->line); 595 596 return 0; 597 } 598 #endif /* CONFIG_PM_SLEEP */ 599 600 #ifdef CONFIG_PM 601 static int dw8250_runtime_suspend(struct device *dev) 602 { 603 struct dw8250_data *data = dev_get_drvdata(dev); 604 605 if (!IS_ERR(data->clk)) 606 clk_disable_unprepare(data->clk); 607 608 if (!IS_ERR(data->pclk)) 609 clk_disable_unprepare(data->pclk); 610 611 return 0; 612 } 613 614 static int dw8250_runtime_resume(struct device *dev) 615 { 616 struct dw8250_data *data = dev_get_drvdata(dev); 617 618 if (!IS_ERR(data->pclk)) 619 clk_prepare_enable(data->pclk); 620 621 if (!IS_ERR(data->clk)) 622 clk_prepare_enable(data->clk); 623 624 return 0; 625 } 626 #endif 627 628 static const struct dev_pm_ops dw8250_pm_ops = { 629 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 630 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 631 }; 632 633 static const struct of_device_id dw8250_of_match[] = { 634 { .compatible = "snps,dw-apb-uart" }, 635 { .compatible = "cavium,octeon-3860-uart" }, 636 { /* Sentinel */ } 637 }; 638 MODULE_DEVICE_TABLE(of, dw8250_of_match); 639 640 static const struct acpi_device_id dw8250_acpi_match[] = { 641 { "INT33C4", 0 }, 642 { "INT33C5", 0 }, 643 { "INT3434", 0 }, 644 { "INT3435", 0 }, 645 { "80860F0A", 0 }, 646 { "8086228A", 0 }, 647 { "APMC0D08", 0}, 648 { "AMD0020", 0 }, 649 { "AMDI0020", 0 }, 650 { "HISI0031", 0 }, 651 { }, 652 }; 653 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 654 655 static struct platform_driver dw8250_platform_driver = { 656 .driver = { 657 .name = "dw-apb-uart", 658 .pm = &dw8250_pm_ops, 659 .of_match_table = dw8250_of_match, 660 .acpi_match_table = ACPI_PTR(dw8250_acpi_match), 661 }, 662 .probe = dw8250_probe, 663 .remove = dw8250_remove, 664 }; 665 666 module_platform_driver(dw8250_platform_driver); 667 668 MODULE_AUTHOR("Jamie Iles"); 669 MODULE_LICENSE("GPL"); 670 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 671 MODULE_ALIAS("platform:dw-apb-uart"); 672