1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Synopsys DesignWare 8250 driver. 4 * 5 * Copyright 2011 Picochip, Jamie Iles. 6 * Copyright 2013 Intel Corporation 7 * 8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 9 * LCR is written whilst busy. If it is, then a busy detect interrupt is 10 * raised, the LCR needs to be rewritten and the uart status register read. 11 */ 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 #include <linux/acpi.h> 24 #include <linux/clk.h> 25 #include <linux/reset.h> 26 #include <linux/pm_runtime.h> 27 28 #include <asm/byteorder.h> 29 30 #include "8250.h" 31 32 /* Offsets for the DesignWare specific registers */ 33 #define DW_UART_USR 0x1f /* UART Status Register */ 34 #define DW_UART_CPR 0xf4 /* Component Parameter Register */ 35 #define DW_UART_UCV 0xf8 /* UART Component Version */ 36 37 /* Component Parameter Register bits */ 38 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) 39 #define DW_UART_CPR_AFCE_MODE (1 << 4) 40 #define DW_UART_CPR_THRE_MODE (1 << 5) 41 #define DW_UART_CPR_SIR_MODE (1 << 6) 42 #define DW_UART_CPR_SIR_LP_MODE (1 << 7) 43 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) 44 #define DW_UART_CPR_FIFO_ACCESS (1 << 9) 45 #define DW_UART_CPR_FIFO_STAT (1 << 10) 46 #define DW_UART_CPR_SHADOW (1 << 11) 47 #define DW_UART_CPR_ENCODED_PARMS (1 << 12) 48 #define DW_UART_CPR_DMA_EXTRA (1 << 13) 49 #define DW_UART_CPR_FIFO_MODE (0xff << 16) 50 /* Helper for fifo size calculation */ 51 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) 52 53 /* DesignWare specific register fields */ 54 #define DW_UART_MCR_SIRE BIT(6) 55 56 struct dw8250_data { 57 u8 usr_reg; 58 int line; 59 int msr_mask_on; 60 int msr_mask_off; 61 struct clk *clk; 62 struct clk *pclk; 63 struct reset_control *rst; 64 struct uart_8250_dma dma; 65 66 unsigned int skip_autocfg:1; 67 unsigned int uart_16550_compatible:1; 68 }; 69 70 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 71 { 72 struct dw8250_data *d = p->private_data; 73 74 /* Override any modem control signals if needed */ 75 if (offset == UART_MSR) { 76 value |= d->msr_mask_on; 77 value &= ~d->msr_mask_off; 78 } 79 80 return value; 81 } 82 83 static void dw8250_force_idle(struct uart_port *p) 84 { 85 struct uart_8250_port *up = up_to_u8250p(p); 86 87 serial8250_clear_and_reinit_fifos(up); 88 (void)p->serial_in(p, UART_RX); 89 } 90 91 static void dw8250_check_lcr(struct uart_port *p, int value) 92 { 93 void __iomem *offset = p->membase + (UART_LCR << p->regshift); 94 int tries = 1000; 95 96 /* Make sure LCR write wasn't ignored */ 97 while (tries--) { 98 unsigned int lcr = p->serial_in(p, UART_LCR); 99 100 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 101 return; 102 103 dw8250_force_idle(p); 104 105 #ifdef CONFIG_64BIT 106 if (p->type == PORT_OCTEON) 107 __raw_writeq(value & 0xff, offset); 108 else 109 #endif 110 if (p->iotype == UPIO_MEM32) 111 writel(value, offset); 112 else if (p->iotype == UPIO_MEM32BE) 113 iowrite32be(value, offset); 114 else 115 writeb(value, offset); 116 } 117 /* 118 * FIXME: this deadlocks if port->lock is already held 119 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 120 */ 121 } 122 123 /* Returns once the transmitter is empty or we run out of retries */ 124 static void dw8250_tx_wait_empty(struct uart_port *p, int tries) 125 { 126 unsigned int lsr; 127 128 while (tries--) { 129 lsr = readb (p->membase + (UART_LSR << p->regshift)); 130 if (lsr & UART_LSR_TEMT) 131 break; 132 udelay (10); 133 } 134 } 135 136 static void dw8250_serial_out(struct uart_port *p, int offset, int value) 137 { 138 struct dw8250_data *d = p->private_data; 139 140 /* Allow the TX to drain before we reconfigure */ 141 if (offset == UART_LCR) 142 dw8250_tx_wait_empty(p, 1000); 143 144 writeb(value, p->membase + (offset << p->regshift)); 145 146 if (offset == UART_LCR && !d->uart_16550_compatible) 147 dw8250_check_lcr(p, value); 148 } 149 150 static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 151 { 152 unsigned int value = readb(p->membase + (offset << p->regshift)); 153 154 return dw8250_modify_msr(p, offset, value); 155 } 156 157 #ifdef CONFIG_64BIT 158 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) 159 { 160 unsigned int value; 161 162 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); 163 164 return dw8250_modify_msr(p, offset, value); 165 } 166 167 static void dw8250_serial_outq(struct uart_port *p, int offset, int value) 168 { 169 struct dw8250_data *d = p->private_data; 170 171 value &= 0xff; 172 __raw_writeq(value, p->membase + (offset << p->regshift)); 173 /* Read back to ensure register write ordering. */ 174 __raw_readq(p->membase + (UART_LCR << p->regshift)); 175 176 if (offset == UART_LCR && !d->uart_16550_compatible) 177 dw8250_check_lcr(p, value); 178 } 179 #endif /* CONFIG_64BIT */ 180 181 static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 182 { 183 struct dw8250_data *d = p->private_data; 184 185 writel(value, p->membase + (offset << p->regshift)); 186 187 if (offset == UART_LCR && !d->uart_16550_compatible) 188 dw8250_check_lcr(p, value); 189 } 190 191 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 192 { 193 unsigned int value = readl(p->membase + (offset << p->regshift)); 194 195 return dw8250_modify_msr(p, offset, value); 196 } 197 198 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value) 199 { 200 struct dw8250_data *d = p->private_data; 201 202 iowrite32be(value, p->membase + (offset << p->regshift)); 203 204 if (offset == UART_LCR && !d->uart_16550_compatible) 205 dw8250_check_lcr(p, value); 206 } 207 208 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) 209 { 210 unsigned int value = ioread32be(p->membase + (offset << p->regshift)); 211 212 return dw8250_modify_msr(p, offset, value); 213 } 214 215 216 static int dw8250_handle_irq(struct uart_port *p) 217 { 218 struct uart_8250_port *up = up_to_u8250p(p); 219 struct dw8250_data *d = p->private_data; 220 unsigned int iir = p->serial_in(p, UART_IIR); 221 unsigned int status; 222 unsigned long flags; 223 224 /* 225 * There are ways to get Designware-based UARTs into a state where 226 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual 227 * data available. If we see such a case then we'll do a bogus 228 * read. If we don't do this then the "RX TIMEOUT" interrupt will 229 * fire forever. 230 * 231 * This problem has only been observed so far when not in DMA mode 232 * so we limit the workaround only to non-DMA mode. 233 */ 234 if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) { 235 spin_lock_irqsave(&p->lock, flags); 236 status = p->serial_in(p, UART_LSR); 237 238 if (!(status & (UART_LSR_DR | UART_LSR_BI))) 239 (void) p->serial_in(p, UART_RX); 240 241 spin_unlock_irqrestore(&p->lock, flags); 242 } 243 244 if (serial8250_handle_irq(p, iir)) 245 return 1; 246 247 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 248 /* Clear the USR */ 249 (void)p->serial_in(p, d->usr_reg); 250 251 return 1; 252 } 253 254 return 0; 255 } 256 257 static void 258 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 259 { 260 if (!state) 261 pm_runtime_get_sync(port->dev); 262 263 serial8250_do_pm(port, state, old); 264 265 if (state) 266 pm_runtime_put_sync_suspend(port->dev); 267 } 268 269 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, 270 struct ktermios *old) 271 { 272 unsigned int baud = tty_termios_baud_rate(termios); 273 struct dw8250_data *d = p->private_data; 274 long rate; 275 int ret; 276 277 if (IS_ERR(d->clk) || !old) 278 goto out; 279 280 clk_disable_unprepare(d->clk); 281 rate = clk_round_rate(d->clk, baud * 16); 282 if (rate < 0) 283 ret = rate; 284 else if (rate == 0) 285 ret = -ENOENT; 286 else 287 ret = clk_set_rate(d->clk, rate); 288 clk_prepare_enable(d->clk); 289 290 if (!ret) 291 p->uartclk = rate; 292 293 out: 294 p->status &= ~UPSTAT_AUTOCTS; 295 if (termios->c_cflag & CRTSCTS) 296 p->status |= UPSTAT_AUTOCTS; 297 298 serial8250_do_set_termios(p, termios, old); 299 } 300 301 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios) 302 { 303 struct uart_8250_port *up = up_to_u8250p(p); 304 unsigned int mcr = p->serial_in(p, UART_MCR); 305 306 if (up->capabilities & UART_CAP_IRDA) { 307 if (termios->c_line == N_IRDA) 308 mcr |= DW_UART_MCR_SIRE; 309 else 310 mcr &= ~DW_UART_MCR_SIRE; 311 312 p->serial_out(p, UART_MCR, mcr); 313 } 314 serial8250_do_set_ldisc(p, termios); 315 } 316 317 /* 318 * dw8250_fallback_dma_filter will prevent the UART from getting just any free 319 * channel on platforms that have DMA engines, but don't have any channels 320 * assigned to the UART. 321 * 322 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the 323 * core problem is fixed, this function is no longer needed. 324 */ 325 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param) 326 { 327 return false; 328 } 329 330 static bool dw8250_idma_filter(struct dma_chan *chan, void *param) 331 { 332 return param == chan->device->dev->parent; 333 } 334 335 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) 336 { 337 if (p->dev->of_node) { 338 struct device_node *np = p->dev->of_node; 339 int id; 340 341 /* get index of serial line, if found in DT aliases */ 342 id = of_alias_get_id(np, "serial"); 343 if (id >= 0) 344 p->line = id; 345 #ifdef CONFIG_64BIT 346 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 347 p->serial_in = dw8250_serial_inq; 348 p->serial_out = dw8250_serial_outq; 349 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 350 p->type = PORT_OCTEON; 351 data->usr_reg = 0x27; 352 data->skip_autocfg = true; 353 } 354 #endif 355 if (of_device_is_big_endian(p->dev->of_node)) { 356 p->iotype = UPIO_MEM32BE; 357 p->serial_in = dw8250_serial_in32be; 358 p->serial_out = dw8250_serial_out32be; 359 } 360 } else if (acpi_dev_present("APMC0D08", NULL, -1)) { 361 p->iotype = UPIO_MEM32; 362 p->regshift = 2; 363 p->serial_in = dw8250_serial_in32; 364 data->uart_16550_compatible = true; 365 } 366 367 /* Platforms with iDMA */ 368 if (platform_get_resource_byname(to_platform_device(p->dev), 369 IORESOURCE_MEM, "lpss_priv")) { 370 data->dma.rx_param = p->dev->parent; 371 data->dma.tx_param = p->dev->parent; 372 data->dma.fn = dw8250_idma_filter; 373 } 374 } 375 376 static void dw8250_setup_port(struct uart_port *p) 377 { 378 struct uart_8250_port *up = up_to_u8250p(p); 379 u32 reg; 380 381 /* 382 * If the Component Version Register returns zero, we know that 383 * ADDITIONAL_FEATURES are not enabled. No need to go any further. 384 */ 385 if (p->iotype == UPIO_MEM32BE) 386 reg = ioread32be(p->membase + DW_UART_UCV); 387 else 388 reg = readl(p->membase + DW_UART_UCV); 389 if (!reg) 390 return; 391 392 dev_dbg(p->dev, "Designware UART version %c.%c%c\n", 393 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); 394 395 if (p->iotype == UPIO_MEM32BE) 396 reg = ioread32be(p->membase + DW_UART_CPR); 397 else 398 reg = readl(p->membase + DW_UART_CPR); 399 if (!reg) 400 return; 401 402 /* Select the type based on fifo */ 403 if (reg & DW_UART_CPR_FIFO_MODE) { 404 p->type = PORT_16550A; 405 p->flags |= UPF_FIXED_TYPE; 406 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); 407 up->capabilities = UART_CAP_FIFO; 408 } 409 410 if (reg & DW_UART_CPR_AFCE_MODE) 411 up->capabilities |= UART_CAP_AFE; 412 413 if (reg & DW_UART_CPR_SIR_MODE) 414 up->capabilities |= UART_CAP_IRDA; 415 } 416 417 static int dw8250_probe(struct platform_device *pdev) 418 { 419 struct uart_8250_port uart = {}; 420 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 421 int irq = platform_get_irq(pdev, 0); 422 struct uart_port *p = &uart.port; 423 struct device *dev = &pdev->dev; 424 struct dw8250_data *data; 425 int err; 426 u32 val; 427 428 if (!regs) { 429 dev_err(dev, "no registers defined\n"); 430 return -EINVAL; 431 } 432 433 if (irq < 0) { 434 if (irq != -EPROBE_DEFER) 435 dev_err(dev, "cannot get irq\n"); 436 return irq; 437 } 438 439 spin_lock_init(&p->lock); 440 p->mapbase = regs->start; 441 p->irq = irq; 442 p->handle_irq = dw8250_handle_irq; 443 p->pm = dw8250_do_pm; 444 p->type = PORT_8250; 445 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; 446 p->dev = dev; 447 p->iotype = UPIO_MEM; 448 p->serial_in = dw8250_serial_in; 449 p->serial_out = dw8250_serial_out; 450 p->set_ldisc = dw8250_set_ldisc; 451 p->set_termios = dw8250_set_termios; 452 453 p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); 454 if (!p->membase) 455 return -ENOMEM; 456 457 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 458 if (!data) 459 return -ENOMEM; 460 461 data->dma.fn = dw8250_fallback_dma_filter; 462 data->usr_reg = DW_UART_USR; 463 p->private_data = data; 464 465 data->uart_16550_compatible = device_property_read_bool(dev, 466 "snps,uart-16550-compatible"); 467 468 err = device_property_read_u32(dev, "reg-shift", &val); 469 if (!err) 470 p->regshift = val; 471 472 err = device_property_read_u32(dev, "reg-io-width", &val); 473 if (!err && val == 4) { 474 p->iotype = UPIO_MEM32; 475 p->serial_in = dw8250_serial_in32; 476 p->serial_out = dw8250_serial_out32; 477 } 478 479 if (device_property_read_bool(dev, "dcd-override")) { 480 /* Always report DCD as active */ 481 data->msr_mask_on |= UART_MSR_DCD; 482 data->msr_mask_off |= UART_MSR_DDCD; 483 } 484 485 if (device_property_read_bool(dev, "dsr-override")) { 486 /* Always report DSR as active */ 487 data->msr_mask_on |= UART_MSR_DSR; 488 data->msr_mask_off |= UART_MSR_DDSR; 489 } 490 491 if (device_property_read_bool(dev, "cts-override")) { 492 /* Always report CTS as active */ 493 data->msr_mask_on |= UART_MSR_CTS; 494 data->msr_mask_off |= UART_MSR_DCTS; 495 } 496 497 if (device_property_read_bool(dev, "ri-override")) { 498 /* Always report Ring indicator as inactive */ 499 data->msr_mask_off |= UART_MSR_RI; 500 data->msr_mask_off |= UART_MSR_TERI; 501 } 502 503 /* Always ask for fixed clock rate from a property. */ 504 device_property_read_u32(dev, "clock-frequency", &p->uartclk); 505 506 /* If there is separate baudclk, get the rate from it. */ 507 data->clk = devm_clk_get(dev, "baudclk"); 508 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) 509 data->clk = devm_clk_get(dev, NULL); 510 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) 511 return -EPROBE_DEFER; 512 if (!IS_ERR_OR_NULL(data->clk)) { 513 err = clk_prepare_enable(data->clk); 514 if (err) 515 dev_warn(dev, "could not enable optional baudclk: %d\n", 516 err); 517 else 518 p->uartclk = clk_get_rate(data->clk); 519 } 520 521 /* If no clock rate is defined, fail. */ 522 if (!p->uartclk) { 523 dev_err(dev, "clock rate not defined\n"); 524 err = -EINVAL; 525 goto err_clk; 526 } 527 528 data->pclk = devm_clk_get(dev, "apb_pclk"); 529 if (IS_ERR(data->pclk) && PTR_ERR(data->pclk) == -EPROBE_DEFER) { 530 err = -EPROBE_DEFER; 531 goto err_clk; 532 } 533 if (!IS_ERR(data->pclk)) { 534 err = clk_prepare_enable(data->pclk); 535 if (err) { 536 dev_err(dev, "could not enable apb_pclk\n"); 537 goto err_clk; 538 } 539 } 540 541 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); 542 if (IS_ERR(data->rst)) { 543 err = PTR_ERR(data->rst); 544 goto err_pclk; 545 } 546 reset_control_deassert(data->rst); 547 548 dw8250_quirks(p, data); 549 550 /* If the Busy Functionality is not implemented, don't handle it */ 551 if (data->uart_16550_compatible) 552 p->handle_irq = NULL; 553 554 if (!data->skip_autocfg) 555 dw8250_setup_port(p); 556 557 /* If we have a valid fifosize, try hooking up DMA */ 558 if (p->fifosize) { 559 data->dma.rxconf.src_maxburst = p->fifosize / 4; 560 data->dma.txconf.dst_maxburst = p->fifosize / 4; 561 uart.dma = &data->dma; 562 } 563 564 data->line = serial8250_register_8250_port(&uart); 565 if (data->line < 0) { 566 err = data->line; 567 goto err_reset; 568 } 569 570 platform_set_drvdata(pdev, data); 571 572 pm_runtime_set_active(dev); 573 pm_runtime_enable(dev); 574 575 return 0; 576 577 err_reset: 578 reset_control_assert(data->rst); 579 580 err_pclk: 581 if (!IS_ERR(data->pclk)) 582 clk_disable_unprepare(data->pclk); 583 584 err_clk: 585 if (!IS_ERR(data->clk)) 586 clk_disable_unprepare(data->clk); 587 588 return err; 589 } 590 591 static int dw8250_remove(struct platform_device *pdev) 592 { 593 struct dw8250_data *data = platform_get_drvdata(pdev); 594 595 pm_runtime_get_sync(&pdev->dev); 596 597 serial8250_unregister_port(data->line); 598 599 reset_control_assert(data->rst); 600 601 if (!IS_ERR(data->pclk)) 602 clk_disable_unprepare(data->pclk); 603 604 if (!IS_ERR(data->clk)) 605 clk_disable_unprepare(data->clk); 606 607 pm_runtime_disable(&pdev->dev); 608 pm_runtime_put_noidle(&pdev->dev); 609 610 return 0; 611 } 612 613 #ifdef CONFIG_PM_SLEEP 614 static int dw8250_suspend(struct device *dev) 615 { 616 struct dw8250_data *data = dev_get_drvdata(dev); 617 618 serial8250_suspend_port(data->line); 619 620 return 0; 621 } 622 623 static int dw8250_resume(struct device *dev) 624 { 625 struct dw8250_data *data = dev_get_drvdata(dev); 626 627 serial8250_resume_port(data->line); 628 629 return 0; 630 } 631 #endif /* CONFIG_PM_SLEEP */ 632 633 #ifdef CONFIG_PM 634 static int dw8250_runtime_suspend(struct device *dev) 635 { 636 struct dw8250_data *data = dev_get_drvdata(dev); 637 638 if (!IS_ERR(data->clk)) 639 clk_disable_unprepare(data->clk); 640 641 if (!IS_ERR(data->pclk)) 642 clk_disable_unprepare(data->pclk); 643 644 return 0; 645 } 646 647 static int dw8250_runtime_resume(struct device *dev) 648 { 649 struct dw8250_data *data = dev_get_drvdata(dev); 650 651 if (!IS_ERR(data->pclk)) 652 clk_prepare_enable(data->pclk); 653 654 if (!IS_ERR(data->clk)) 655 clk_prepare_enable(data->clk); 656 657 return 0; 658 } 659 #endif 660 661 static const struct dev_pm_ops dw8250_pm_ops = { 662 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 663 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 664 }; 665 666 static const struct of_device_id dw8250_of_match[] = { 667 { .compatible = "snps,dw-apb-uart" }, 668 { .compatible = "cavium,octeon-3860-uart" }, 669 { /* Sentinel */ } 670 }; 671 MODULE_DEVICE_TABLE(of, dw8250_of_match); 672 673 static const struct acpi_device_id dw8250_acpi_match[] = { 674 { "INT33C4", 0 }, 675 { "INT33C5", 0 }, 676 { "INT3434", 0 }, 677 { "INT3435", 0 }, 678 { "80860F0A", 0 }, 679 { "8086228A", 0 }, 680 { "APMC0D08", 0}, 681 { "AMD0020", 0 }, 682 { "AMDI0020", 0 }, 683 { "HISI0031", 0 }, 684 { }, 685 }; 686 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 687 688 static struct platform_driver dw8250_platform_driver = { 689 .driver = { 690 .name = "dw-apb-uart", 691 .pm = &dw8250_pm_ops, 692 .of_match_table = dw8250_of_match, 693 .acpi_match_table = ACPI_PTR(dw8250_acpi_match), 694 }, 695 .probe = dw8250_probe, 696 .remove = dw8250_remove, 697 }; 698 699 module_platform_driver(dw8250_platform_driver); 700 701 MODULE_AUTHOR("Jamie Iles"); 702 MODULE_LICENSE("GPL"); 703 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 704 MODULE_ALIAS("platform:dw-apb-uart"); 705