1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Synopsys DesignWare 8250 driver. 4 * 5 * Copyright 2011 Picochip, Jamie Iles. 6 * Copyright 2013 Intel Corporation 7 * 8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 9 * LCR is written whilst busy. If it is, then a busy detect interrupt is 10 * raised, the LCR needs to be rewritten and the uart status register read. 11 */ 12 #include <linux/delay.h> 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/serial_8250.h> 17 #include <linux/serial_reg.h> 18 #include <linux/of.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/platform_device.h> 22 #include <linux/slab.h> 23 #include <linux/acpi.h> 24 #include <linux/clk.h> 25 #include <linux/reset.h> 26 #include <linux/pm_runtime.h> 27 28 #include <asm/byteorder.h> 29 30 #include "8250_dwlib.h" 31 32 /* Offsets for the DesignWare specific registers */ 33 #define DW_UART_USR 0x1f /* UART Status Register */ 34 35 /* DesignWare specific register fields */ 36 #define DW_UART_MCR_SIRE BIT(6) 37 38 struct dw8250_data { 39 struct dw8250_port_data data; 40 41 u8 usr_reg; 42 int msr_mask_on; 43 int msr_mask_off; 44 struct clk *clk; 45 struct clk *pclk; 46 struct reset_control *rst; 47 48 unsigned int skip_autocfg:1; 49 unsigned int uart_16550_compatible:1; 50 }; 51 52 static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data) 53 { 54 return container_of(data, struct dw8250_data, data); 55 } 56 57 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 58 { 59 struct dw8250_data *d = to_dw8250_data(p->private_data); 60 61 /* Override any modem control signals if needed */ 62 if (offset == UART_MSR) { 63 value |= d->msr_mask_on; 64 value &= ~d->msr_mask_off; 65 } 66 67 return value; 68 } 69 70 static void dw8250_force_idle(struct uart_port *p) 71 { 72 struct uart_8250_port *up = up_to_u8250p(p); 73 74 serial8250_clear_and_reinit_fifos(up); 75 (void)p->serial_in(p, UART_RX); 76 } 77 78 static void dw8250_check_lcr(struct uart_port *p, int value) 79 { 80 void __iomem *offset = p->membase + (UART_LCR << p->regshift); 81 int tries = 1000; 82 83 /* Make sure LCR write wasn't ignored */ 84 while (tries--) { 85 unsigned int lcr = p->serial_in(p, UART_LCR); 86 87 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 88 return; 89 90 dw8250_force_idle(p); 91 92 #ifdef CONFIG_64BIT 93 if (p->type == PORT_OCTEON) 94 __raw_writeq(value & 0xff, offset); 95 else 96 #endif 97 if (p->iotype == UPIO_MEM32) 98 writel(value, offset); 99 else if (p->iotype == UPIO_MEM32BE) 100 iowrite32be(value, offset); 101 else 102 writeb(value, offset); 103 } 104 /* 105 * FIXME: this deadlocks if port->lock is already held 106 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 107 */ 108 } 109 110 /* Returns once the transmitter is empty or we run out of retries */ 111 static void dw8250_tx_wait_empty(struct uart_port *p) 112 { 113 unsigned int tries = 20000; 114 unsigned int delay_threshold = tries - 1000; 115 unsigned int lsr; 116 117 while (tries--) { 118 lsr = readb (p->membase + (UART_LSR << p->regshift)); 119 if (lsr & UART_LSR_TEMT) 120 break; 121 122 /* The device is first given a chance to empty without delay, 123 * to avoid slowdowns at high bitrates. If after 1000 tries 124 * the buffer has still not emptied, allow more time for low- 125 * speed links. */ 126 if (tries < delay_threshold) 127 udelay (1); 128 } 129 } 130 131 static void dw8250_serial_out38x(struct uart_port *p, int offset, int value) 132 { 133 struct dw8250_data *d = to_dw8250_data(p->private_data); 134 135 /* Allow the TX to drain before we reconfigure */ 136 if (offset == UART_LCR) 137 dw8250_tx_wait_empty(p); 138 139 writeb(value, p->membase + (offset << p->regshift)); 140 141 if (offset == UART_LCR && !d->uart_16550_compatible) 142 dw8250_check_lcr(p, value); 143 } 144 145 146 static void dw8250_serial_out(struct uart_port *p, int offset, int value) 147 { 148 struct dw8250_data *d = to_dw8250_data(p->private_data); 149 150 writeb(value, p->membase + (offset << p->regshift)); 151 152 if (offset == UART_LCR && !d->uart_16550_compatible) 153 dw8250_check_lcr(p, value); 154 } 155 156 static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 157 { 158 unsigned int value = readb(p->membase + (offset << p->regshift)); 159 160 return dw8250_modify_msr(p, offset, value); 161 } 162 163 #ifdef CONFIG_64BIT 164 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) 165 { 166 unsigned int value; 167 168 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); 169 170 return dw8250_modify_msr(p, offset, value); 171 } 172 173 static void dw8250_serial_outq(struct uart_port *p, int offset, int value) 174 { 175 struct dw8250_data *d = to_dw8250_data(p->private_data); 176 177 value &= 0xff; 178 __raw_writeq(value, p->membase + (offset << p->regshift)); 179 /* Read back to ensure register write ordering. */ 180 __raw_readq(p->membase + (UART_LCR << p->regshift)); 181 182 if (offset == UART_LCR && !d->uart_16550_compatible) 183 dw8250_check_lcr(p, value); 184 } 185 #endif /* CONFIG_64BIT */ 186 187 static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 188 { 189 struct dw8250_data *d = to_dw8250_data(p->private_data); 190 191 writel(value, p->membase + (offset << p->regshift)); 192 193 if (offset == UART_LCR && !d->uart_16550_compatible) 194 dw8250_check_lcr(p, value); 195 } 196 197 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 198 { 199 unsigned int value = readl(p->membase + (offset << p->regshift)); 200 201 return dw8250_modify_msr(p, offset, value); 202 } 203 204 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value) 205 { 206 struct dw8250_data *d = to_dw8250_data(p->private_data); 207 208 iowrite32be(value, p->membase + (offset << p->regshift)); 209 210 if (offset == UART_LCR && !d->uart_16550_compatible) 211 dw8250_check_lcr(p, value); 212 } 213 214 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) 215 { 216 unsigned int value = ioread32be(p->membase + (offset << p->regshift)); 217 218 return dw8250_modify_msr(p, offset, value); 219 } 220 221 222 static int dw8250_handle_irq(struct uart_port *p) 223 { 224 struct uart_8250_port *up = up_to_u8250p(p); 225 struct dw8250_data *d = to_dw8250_data(p->private_data); 226 unsigned int iir = p->serial_in(p, UART_IIR); 227 unsigned int status; 228 unsigned long flags; 229 230 /* 231 * There are ways to get Designware-based UARTs into a state where 232 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual 233 * data available. If we see such a case then we'll do a bogus 234 * read. If we don't do this then the "RX TIMEOUT" interrupt will 235 * fire forever. 236 * 237 * This problem has only been observed so far when not in DMA mode 238 * so we limit the workaround only to non-DMA mode. 239 */ 240 if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) { 241 spin_lock_irqsave(&p->lock, flags); 242 status = p->serial_in(p, UART_LSR); 243 244 if (!(status & (UART_LSR_DR | UART_LSR_BI))) 245 (void) p->serial_in(p, UART_RX); 246 247 spin_unlock_irqrestore(&p->lock, flags); 248 } 249 250 if (serial8250_handle_irq(p, iir)) 251 return 1; 252 253 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 254 /* Clear the USR */ 255 (void)p->serial_in(p, d->usr_reg); 256 257 return 1; 258 } 259 260 return 0; 261 } 262 263 static void 264 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 265 { 266 if (!state) 267 pm_runtime_get_sync(port->dev); 268 269 serial8250_do_pm(port, state, old); 270 271 if (state) 272 pm_runtime_put_sync_suspend(port->dev); 273 } 274 275 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, 276 struct ktermios *old) 277 { 278 unsigned int baud = tty_termios_baud_rate(termios); 279 struct dw8250_data *d = to_dw8250_data(p->private_data); 280 long rate; 281 int ret; 282 283 if (IS_ERR(d->clk)) 284 goto out; 285 286 clk_disable_unprepare(d->clk); 287 rate = clk_round_rate(d->clk, baud * 16); 288 if (rate < 0) 289 ret = rate; 290 else if (rate == 0) 291 ret = -ENOENT; 292 else 293 ret = clk_set_rate(d->clk, rate); 294 clk_prepare_enable(d->clk); 295 296 if (!ret) 297 p->uartclk = rate; 298 299 out: 300 p->status &= ~UPSTAT_AUTOCTS; 301 if (termios->c_cflag & CRTSCTS) 302 p->status |= UPSTAT_AUTOCTS; 303 304 serial8250_do_set_termios(p, termios, old); 305 } 306 307 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios) 308 { 309 struct uart_8250_port *up = up_to_u8250p(p); 310 unsigned int mcr = p->serial_in(p, UART_MCR); 311 312 if (up->capabilities & UART_CAP_IRDA) { 313 if (termios->c_line == N_IRDA) 314 mcr |= DW_UART_MCR_SIRE; 315 else 316 mcr &= ~DW_UART_MCR_SIRE; 317 318 p->serial_out(p, UART_MCR, mcr); 319 } 320 serial8250_do_set_ldisc(p, termios); 321 } 322 323 /* 324 * dw8250_fallback_dma_filter will prevent the UART from getting just any free 325 * channel on platforms that have DMA engines, but don't have any channels 326 * assigned to the UART. 327 * 328 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the 329 * core problem is fixed, this function is no longer needed. 330 */ 331 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param) 332 { 333 return false; 334 } 335 336 static bool dw8250_idma_filter(struct dma_chan *chan, void *param) 337 { 338 return param == chan->device->dev; 339 } 340 341 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) 342 { 343 if (p->dev->of_node) { 344 struct device_node *np = p->dev->of_node; 345 int id; 346 347 /* get index of serial line, if found in DT aliases */ 348 id = of_alias_get_id(np, "serial"); 349 if (id >= 0) 350 p->line = id; 351 #ifdef CONFIG_64BIT 352 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 353 p->serial_in = dw8250_serial_inq; 354 p->serial_out = dw8250_serial_outq; 355 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 356 p->type = PORT_OCTEON; 357 data->usr_reg = 0x27; 358 data->skip_autocfg = true; 359 } 360 #endif 361 if (of_device_is_big_endian(p->dev->of_node)) { 362 p->iotype = UPIO_MEM32BE; 363 p->serial_in = dw8250_serial_in32be; 364 p->serial_out = dw8250_serial_out32be; 365 } 366 if (of_device_is_compatible(np, "marvell,armada-38x-uart")) 367 p->serial_out = dw8250_serial_out38x; 368 369 } else if (acpi_dev_present("APMC0D08", NULL, -1)) { 370 p->iotype = UPIO_MEM32; 371 p->regshift = 2; 372 p->serial_in = dw8250_serial_in32; 373 data->uart_16550_compatible = true; 374 } 375 376 /* Platforms with iDMA 64-bit */ 377 if (platform_get_resource_byname(to_platform_device(p->dev), 378 IORESOURCE_MEM, "lpss_priv")) { 379 data->data.dma.rx_param = p->dev->parent; 380 data->data.dma.tx_param = p->dev->parent; 381 data->data.dma.fn = dw8250_idma_filter; 382 } 383 } 384 385 static int dw8250_probe(struct platform_device *pdev) 386 { 387 struct uart_8250_port uart = {}, *up = &uart; 388 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 389 int irq = platform_get_irq(pdev, 0); 390 struct uart_port *p = &up->port; 391 struct device *dev = &pdev->dev; 392 struct dw8250_data *data; 393 int err; 394 u32 val; 395 396 if (!regs) { 397 dev_err(dev, "no registers defined\n"); 398 return -EINVAL; 399 } 400 401 if (irq < 0) { 402 if (irq != -EPROBE_DEFER) 403 dev_err(dev, "cannot get irq\n"); 404 return irq; 405 } 406 407 spin_lock_init(&p->lock); 408 p->mapbase = regs->start; 409 p->irq = irq; 410 p->handle_irq = dw8250_handle_irq; 411 p->pm = dw8250_do_pm; 412 p->type = PORT_8250; 413 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; 414 p->dev = dev; 415 p->iotype = UPIO_MEM; 416 p->serial_in = dw8250_serial_in; 417 p->serial_out = dw8250_serial_out; 418 p->set_ldisc = dw8250_set_ldisc; 419 p->set_termios = dw8250_set_termios; 420 421 p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); 422 if (!p->membase) 423 return -ENOMEM; 424 425 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 426 if (!data) 427 return -ENOMEM; 428 429 data->data.dma.fn = dw8250_fallback_dma_filter; 430 data->usr_reg = DW_UART_USR; 431 p->private_data = &data->data; 432 433 data->uart_16550_compatible = device_property_read_bool(dev, 434 "snps,uart-16550-compatible"); 435 436 err = device_property_read_u32(dev, "reg-shift", &val); 437 if (!err) 438 p->regshift = val; 439 440 err = device_property_read_u32(dev, "reg-io-width", &val); 441 if (!err && val == 4) { 442 p->iotype = UPIO_MEM32; 443 p->serial_in = dw8250_serial_in32; 444 p->serial_out = dw8250_serial_out32; 445 } 446 447 if (device_property_read_bool(dev, "dcd-override")) { 448 /* Always report DCD as active */ 449 data->msr_mask_on |= UART_MSR_DCD; 450 data->msr_mask_off |= UART_MSR_DDCD; 451 } 452 453 if (device_property_read_bool(dev, "dsr-override")) { 454 /* Always report DSR as active */ 455 data->msr_mask_on |= UART_MSR_DSR; 456 data->msr_mask_off |= UART_MSR_DDSR; 457 } 458 459 if (device_property_read_bool(dev, "cts-override")) { 460 /* Always report CTS as active */ 461 data->msr_mask_on |= UART_MSR_CTS; 462 data->msr_mask_off |= UART_MSR_DCTS; 463 } 464 465 if (device_property_read_bool(dev, "ri-override")) { 466 /* Always report Ring indicator as inactive */ 467 data->msr_mask_off |= UART_MSR_RI; 468 data->msr_mask_off |= UART_MSR_TERI; 469 } 470 471 /* Always ask for fixed clock rate from a property. */ 472 device_property_read_u32(dev, "clock-frequency", &p->uartclk); 473 474 /* If there is separate baudclk, get the rate from it. */ 475 data->clk = devm_clk_get(dev, "baudclk"); 476 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) 477 data->clk = devm_clk_get(dev, NULL); 478 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) 479 return -EPROBE_DEFER; 480 if (!IS_ERR_OR_NULL(data->clk)) { 481 err = clk_prepare_enable(data->clk); 482 if (err) 483 dev_warn(dev, "could not enable optional baudclk: %d\n", 484 err); 485 else 486 p->uartclk = clk_get_rate(data->clk); 487 } 488 489 /* If no clock rate is defined, fail. */ 490 if (!p->uartclk) { 491 dev_err(dev, "clock rate not defined\n"); 492 err = -EINVAL; 493 goto err_clk; 494 } 495 496 data->pclk = devm_clk_get(dev, "apb_pclk"); 497 if (IS_ERR(data->pclk) && PTR_ERR(data->pclk) == -EPROBE_DEFER) { 498 err = -EPROBE_DEFER; 499 goto err_clk; 500 } 501 if (!IS_ERR(data->pclk)) { 502 err = clk_prepare_enable(data->pclk); 503 if (err) { 504 dev_err(dev, "could not enable apb_pclk\n"); 505 goto err_clk; 506 } 507 } 508 509 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); 510 if (IS_ERR(data->rst)) { 511 err = PTR_ERR(data->rst); 512 goto err_pclk; 513 } 514 reset_control_deassert(data->rst); 515 516 dw8250_quirks(p, data); 517 518 /* If the Busy Functionality is not implemented, don't handle it */ 519 if (data->uart_16550_compatible) 520 p->handle_irq = NULL; 521 522 if (!data->skip_autocfg) 523 dw8250_setup_port(p); 524 525 /* If we have a valid fifosize, try hooking up DMA */ 526 if (p->fifosize) { 527 data->data.dma.rxconf.src_maxburst = p->fifosize / 4; 528 data->data.dma.txconf.dst_maxburst = p->fifosize / 4; 529 up->dma = &data->data.dma; 530 } 531 532 data->data.line = serial8250_register_8250_port(up); 533 if (data->data.line < 0) { 534 err = data->data.line; 535 goto err_reset; 536 } 537 538 platform_set_drvdata(pdev, data); 539 540 pm_runtime_set_active(dev); 541 pm_runtime_enable(dev); 542 543 return 0; 544 545 err_reset: 546 reset_control_assert(data->rst); 547 548 err_pclk: 549 if (!IS_ERR(data->pclk)) 550 clk_disable_unprepare(data->pclk); 551 552 err_clk: 553 if (!IS_ERR(data->clk)) 554 clk_disable_unprepare(data->clk); 555 556 return err; 557 } 558 559 static int dw8250_remove(struct platform_device *pdev) 560 { 561 struct dw8250_data *data = platform_get_drvdata(pdev); 562 struct device *dev = &pdev->dev; 563 564 pm_runtime_get_sync(dev); 565 566 serial8250_unregister_port(data->data.line); 567 568 reset_control_assert(data->rst); 569 570 if (!IS_ERR(data->pclk)) 571 clk_disable_unprepare(data->pclk); 572 573 if (!IS_ERR(data->clk)) 574 clk_disable_unprepare(data->clk); 575 576 pm_runtime_disable(dev); 577 pm_runtime_put_noidle(dev); 578 579 return 0; 580 } 581 582 #ifdef CONFIG_PM_SLEEP 583 static int dw8250_suspend(struct device *dev) 584 { 585 struct dw8250_data *data = dev_get_drvdata(dev); 586 587 serial8250_suspend_port(data->data.line); 588 589 return 0; 590 } 591 592 static int dw8250_resume(struct device *dev) 593 { 594 struct dw8250_data *data = dev_get_drvdata(dev); 595 596 serial8250_resume_port(data->data.line); 597 598 return 0; 599 } 600 #endif /* CONFIG_PM_SLEEP */ 601 602 #ifdef CONFIG_PM 603 static int dw8250_runtime_suspend(struct device *dev) 604 { 605 struct dw8250_data *data = dev_get_drvdata(dev); 606 607 if (!IS_ERR(data->clk)) 608 clk_disable_unprepare(data->clk); 609 610 if (!IS_ERR(data->pclk)) 611 clk_disable_unprepare(data->pclk); 612 613 return 0; 614 } 615 616 static int dw8250_runtime_resume(struct device *dev) 617 { 618 struct dw8250_data *data = dev_get_drvdata(dev); 619 620 if (!IS_ERR(data->pclk)) 621 clk_prepare_enable(data->pclk); 622 623 if (!IS_ERR(data->clk)) 624 clk_prepare_enable(data->clk); 625 626 return 0; 627 } 628 #endif 629 630 static const struct dev_pm_ops dw8250_pm_ops = { 631 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 632 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 633 }; 634 635 static const struct of_device_id dw8250_of_match[] = { 636 { .compatible = "snps,dw-apb-uart" }, 637 { .compatible = "cavium,octeon-3860-uart" }, 638 { .compatible = "marvell,armada-38x-uart" }, 639 { .compatible = "renesas,rzn1-uart" }, 640 { /* Sentinel */ } 641 }; 642 MODULE_DEVICE_TABLE(of, dw8250_of_match); 643 644 static const struct acpi_device_id dw8250_acpi_match[] = { 645 { "INT33C4", 0 }, 646 { "INT33C5", 0 }, 647 { "INT3434", 0 }, 648 { "INT3435", 0 }, 649 { "80860F0A", 0 }, 650 { "8086228A", 0 }, 651 { "APMC0D08", 0}, 652 { "AMD0020", 0 }, 653 { "AMDI0020", 0 }, 654 { "BRCM2032", 0 }, 655 { "HISI0031", 0 }, 656 { }, 657 }; 658 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 659 660 static struct platform_driver dw8250_platform_driver = { 661 .driver = { 662 .name = "dw-apb-uart", 663 .pm = &dw8250_pm_ops, 664 .of_match_table = dw8250_of_match, 665 .acpi_match_table = ACPI_PTR(dw8250_acpi_match), 666 }, 667 .probe = dw8250_probe, 668 .remove = dw8250_remove, 669 }; 670 671 module_platform_driver(dw8250_platform_driver); 672 673 MODULE_AUTHOR("Jamie Iles"); 674 MODULE_LICENSE("GPL"); 675 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 676 MODULE_ALIAS("platform:dw-apb-uart"); 677