1 /* 2 * Synopsys DesignWare 8250 driver. 3 * 4 * Copyright 2011 Picochip, Jamie Iles. 5 * Copyright 2013 Intel Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 13 * LCR is written whilst busy. If it is, then a busy detect interrupt is 14 * raised, the LCR needs to be rewritten and the uart status register read. 15 */ 16 #include <linux/device.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/serial_8250.h> 20 #include <linux/serial_reg.h> 21 #include <linux/of.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_platform.h> 24 #include <linux/platform_device.h> 25 #include <linux/slab.h> 26 #include <linux/acpi.h> 27 #include <linux/clk.h> 28 #include <linux/reset.h> 29 #include <linux/pm_runtime.h> 30 31 #include <asm/byteorder.h> 32 33 #include "8250.h" 34 35 /* Offsets for the DesignWare specific registers */ 36 #define DW_UART_USR 0x1f /* UART Status Register */ 37 #define DW_UART_CPR 0xf4 /* Component Parameter Register */ 38 #define DW_UART_UCV 0xf8 /* UART Component Version */ 39 40 /* Component Parameter Register bits */ 41 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) 42 #define DW_UART_CPR_AFCE_MODE (1 << 4) 43 #define DW_UART_CPR_THRE_MODE (1 << 5) 44 #define DW_UART_CPR_SIR_MODE (1 << 6) 45 #define DW_UART_CPR_SIR_LP_MODE (1 << 7) 46 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) 47 #define DW_UART_CPR_FIFO_ACCESS (1 << 9) 48 #define DW_UART_CPR_FIFO_STAT (1 << 10) 49 #define DW_UART_CPR_SHADOW (1 << 11) 50 #define DW_UART_CPR_ENCODED_PARMS (1 << 12) 51 #define DW_UART_CPR_DMA_EXTRA (1 << 13) 52 #define DW_UART_CPR_FIFO_MODE (0xff << 16) 53 /* Helper for fifo size calculation */ 54 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) 55 56 /* DesignWare specific register fields */ 57 #define DW_UART_MCR_SIRE BIT(6) 58 59 struct dw8250_data { 60 u8 usr_reg; 61 int line; 62 int msr_mask_on; 63 int msr_mask_off; 64 struct clk *clk; 65 struct clk *pclk; 66 struct reset_control *rst; 67 struct uart_8250_dma dma; 68 69 unsigned int skip_autocfg:1; 70 unsigned int uart_16550_compatible:1; 71 }; 72 73 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 74 { 75 struct dw8250_data *d = p->private_data; 76 77 /* Override any modem control signals if needed */ 78 if (offset == UART_MSR) { 79 value |= d->msr_mask_on; 80 value &= ~d->msr_mask_off; 81 } 82 83 return value; 84 } 85 86 static void dw8250_force_idle(struct uart_port *p) 87 { 88 struct uart_8250_port *up = up_to_u8250p(p); 89 90 serial8250_clear_and_reinit_fifos(up); 91 (void)p->serial_in(p, UART_RX); 92 } 93 94 static void dw8250_check_lcr(struct uart_port *p, int value) 95 { 96 void __iomem *offset = p->membase + (UART_LCR << p->regshift); 97 int tries = 1000; 98 99 /* Make sure LCR write wasn't ignored */ 100 while (tries--) { 101 unsigned int lcr = p->serial_in(p, UART_LCR); 102 103 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 104 return; 105 106 dw8250_force_idle(p); 107 108 #ifdef CONFIG_64BIT 109 if (p->type == PORT_OCTEON) 110 __raw_writeq(value & 0xff, offset); 111 else 112 #endif 113 if (p->iotype == UPIO_MEM32) 114 writel(value, offset); 115 else if (p->iotype == UPIO_MEM32BE) 116 iowrite32be(value, offset); 117 else 118 writeb(value, offset); 119 } 120 /* 121 * FIXME: this deadlocks if port->lock is already held 122 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 123 */ 124 } 125 126 static void dw8250_serial_out(struct uart_port *p, int offset, int value) 127 { 128 struct dw8250_data *d = p->private_data; 129 130 writeb(value, p->membase + (offset << p->regshift)); 131 132 if (offset == UART_LCR && !d->uart_16550_compatible) 133 dw8250_check_lcr(p, value); 134 } 135 136 static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 137 { 138 unsigned int value = readb(p->membase + (offset << p->regshift)); 139 140 return dw8250_modify_msr(p, offset, value); 141 } 142 143 #ifdef CONFIG_64BIT 144 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) 145 { 146 unsigned int value; 147 148 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); 149 150 return dw8250_modify_msr(p, offset, value); 151 } 152 153 static void dw8250_serial_outq(struct uart_port *p, int offset, int value) 154 { 155 struct dw8250_data *d = p->private_data; 156 157 value &= 0xff; 158 __raw_writeq(value, p->membase + (offset << p->regshift)); 159 /* Read back to ensure register write ordering. */ 160 __raw_readq(p->membase + (UART_LCR << p->regshift)); 161 162 if (offset == UART_LCR && !d->uart_16550_compatible) 163 dw8250_check_lcr(p, value); 164 } 165 #endif /* CONFIG_64BIT */ 166 167 static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 168 { 169 struct dw8250_data *d = p->private_data; 170 171 writel(value, p->membase + (offset << p->regshift)); 172 173 if (offset == UART_LCR && !d->uart_16550_compatible) 174 dw8250_check_lcr(p, value); 175 } 176 177 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 178 { 179 unsigned int value = readl(p->membase + (offset << p->regshift)); 180 181 return dw8250_modify_msr(p, offset, value); 182 } 183 184 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value) 185 { 186 struct dw8250_data *d = p->private_data; 187 188 iowrite32be(value, p->membase + (offset << p->regshift)); 189 190 if (offset == UART_LCR && !d->uart_16550_compatible) 191 dw8250_check_lcr(p, value); 192 } 193 194 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) 195 { 196 unsigned int value = ioread32be(p->membase + (offset << p->regshift)); 197 198 return dw8250_modify_msr(p, offset, value); 199 } 200 201 202 static int dw8250_handle_irq(struct uart_port *p) 203 { 204 struct uart_8250_port *up = up_to_u8250p(p); 205 struct dw8250_data *d = p->private_data; 206 unsigned int iir = p->serial_in(p, UART_IIR); 207 unsigned int status; 208 unsigned long flags; 209 210 /* 211 * There are ways to get Designware-based UARTs into a state where 212 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual 213 * data available. If we see such a case then we'll do a bogus 214 * read. If we don't do this then the "RX TIMEOUT" interrupt will 215 * fire forever. 216 * 217 * This problem has only been observed so far when not in DMA mode 218 * so we limit the workaround only to non-DMA mode. 219 */ 220 if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) { 221 spin_lock_irqsave(&p->lock, flags); 222 status = p->serial_in(p, UART_LSR); 223 224 if (!(status & (UART_LSR_DR | UART_LSR_BI))) 225 (void) p->serial_in(p, UART_RX); 226 227 spin_unlock_irqrestore(&p->lock, flags); 228 } 229 230 if (serial8250_handle_irq(p, iir)) 231 return 1; 232 233 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 234 /* Clear the USR */ 235 (void)p->serial_in(p, d->usr_reg); 236 237 return 1; 238 } 239 240 return 0; 241 } 242 243 static void 244 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 245 { 246 if (!state) 247 pm_runtime_get_sync(port->dev); 248 249 serial8250_do_pm(port, state, old); 250 251 if (state) 252 pm_runtime_put_sync_suspend(port->dev); 253 } 254 255 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, 256 struct ktermios *old) 257 { 258 unsigned int baud = tty_termios_baud_rate(termios); 259 struct dw8250_data *d = p->private_data; 260 long rate; 261 int ret; 262 263 if (IS_ERR(d->clk) || !old) 264 goto out; 265 266 clk_disable_unprepare(d->clk); 267 rate = clk_round_rate(d->clk, baud * 16); 268 if (rate < 0) 269 ret = rate; 270 else if (rate == 0) 271 ret = -ENOENT; 272 else 273 ret = clk_set_rate(d->clk, rate); 274 clk_prepare_enable(d->clk); 275 276 if (!ret) 277 p->uartclk = rate; 278 279 out: 280 p->status &= ~UPSTAT_AUTOCTS; 281 if (termios->c_cflag & CRTSCTS) 282 p->status |= UPSTAT_AUTOCTS; 283 284 serial8250_do_set_termios(p, termios, old); 285 } 286 287 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios) 288 { 289 struct uart_8250_port *up = up_to_u8250p(p); 290 unsigned int mcr = p->serial_in(p, UART_MCR); 291 292 if (up->capabilities & UART_CAP_IRDA) { 293 if (termios->c_line == N_IRDA) 294 mcr |= DW_UART_MCR_SIRE; 295 else 296 mcr &= ~DW_UART_MCR_SIRE; 297 298 p->serial_out(p, UART_MCR, mcr); 299 } 300 serial8250_do_set_ldisc(p, termios); 301 } 302 303 /* 304 * dw8250_fallback_dma_filter will prevent the UART from getting just any free 305 * channel on platforms that have DMA engines, but don't have any channels 306 * assigned to the UART. 307 * 308 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the 309 * core problem is fixed, this function is no longer needed. 310 */ 311 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param) 312 { 313 return false; 314 } 315 316 static bool dw8250_idma_filter(struct dma_chan *chan, void *param) 317 { 318 return param == chan->device->dev->parent; 319 } 320 321 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) 322 { 323 if (p->dev->of_node) { 324 struct device_node *np = p->dev->of_node; 325 int id; 326 327 /* get index of serial line, if found in DT aliases */ 328 id = of_alias_get_id(np, "serial"); 329 if (id >= 0) 330 p->line = id; 331 #ifdef CONFIG_64BIT 332 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 333 p->serial_in = dw8250_serial_inq; 334 p->serial_out = dw8250_serial_outq; 335 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 336 p->type = PORT_OCTEON; 337 data->usr_reg = 0x27; 338 data->skip_autocfg = true; 339 } 340 #endif 341 if (of_device_is_big_endian(p->dev->of_node)) { 342 p->iotype = UPIO_MEM32BE; 343 p->serial_in = dw8250_serial_in32be; 344 p->serial_out = dw8250_serial_out32be; 345 } 346 } else if (has_acpi_companion(p->dev)) { 347 const struct acpi_device_id *id; 348 349 id = acpi_match_device(p->dev->driver->acpi_match_table, 350 p->dev); 351 if (id && !strcmp(id->id, "APMC0D08")) { 352 p->iotype = UPIO_MEM32; 353 p->regshift = 2; 354 p->serial_in = dw8250_serial_in32; 355 data->uart_16550_compatible = true; 356 } 357 } 358 359 /* Platforms with iDMA */ 360 if (platform_get_resource_byname(to_platform_device(p->dev), 361 IORESOURCE_MEM, "lpss_priv")) { 362 data->dma.rx_param = p->dev->parent; 363 data->dma.tx_param = p->dev->parent; 364 data->dma.fn = dw8250_idma_filter; 365 } 366 } 367 368 static void dw8250_setup_port(struct uart_port *p) 369 { 370 struct uart_8250_port *up = up_to_u8250p(p); 371 u32 reg; 372 373 /* 374 * If the Component Version Register returns zero, we know that 375 * ADDITIONAL_FEATURES are not enabled. No need to go any further. 376 */ 377 if (p->iotype == UPIO_MEM32BE) 378 reg = ioread32be(p->membase + DW_UART_UCV); 379 else 380 reg = readl(p->membase + DW_UART_UCV); 381 if (!reg) 382 return; 383 384 dev_dbg(p->dev, "Designware UART version %c.%c%c\n", 385 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); 386 387 if (p->iotype == UPIO_MEM32BE) 388 reg = ioread32be(p->membase + DW_UART_CPR); 389 else 390 reg = readl(p->membase + DW_UART_CPR); 391 if (!reg) 392 return; 393 394 /* Select the type based on fifo */ 395 if (reg & DW_UART_CPR_FIFO_MODE) { 396 p->type = PORT_16550A; 397 p->flags |= UPF_FIXED_TYPE; 398 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); 399 up->capabilities = UART_CAP_FIFO; 400 } 401 402 if (reg & DW_UART_CPR_AFCE_MODE) 403 up->capabilities |= UART_CAP_AFE; 404 405 if (reg & DW_UART_CPR_SIR_MODE) 406 up->capabilities |= UART_CAP_IRDA; 407 } 408 409 static int dw8250_probe(struct platform_device *pdev) 410 { 411 struct uart_8250_port uart = {}; 412 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 413 int irq = platform_get_irq(pdev, 0); 414 struct uart_port *p = &uart.port; 415 struct device *dev = &pdev->dev; 416 struct dw8250_data *data; 417 int err; 418 u32 val; 419 420 if (!regs) { 421 dev_err(dev, "no registers defined\n"); 422 return -EINVAL; 423 } 424 425 if (irq < 0) { 426 if (irq != -EPROBE_DEFER) 427 dev_err(dev, "cannot get irq\n"); 428 return irq; 429 } 430 431 spin_lock_init(&p->lock); 432 p->mapbase = regs->start; 433 p->irq = irq; 434 p->handle_irq = dw8250_handle_irq; 435 p->pm = dw8250_do_pm; 436 p->type = PORT_8250; 437 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; 438 p->dev = dev; 439 p->iotype = UPIO_MEM; 440 p->serial_in = dw8250_serial_in; 441 p->serial_out = dw8250_serial_out; 442 p->set_ldisc = dw8250_set_ldisc; 443 p->set_termios = dw8250_set_termios; 444 445 p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); 446 if (!p->membase) 447 return -ENOMEM; 448 449 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 450 if (!data) 451 return -ENOMEM; 452 453 data->dma.fn = dw8250_fallback_dma_filter; 454 data->usr_reg = DW_UART_USR; 455 p->private_data = data; 456 457 data->uart_16550_compatible = device_property_read_bool(dev, 458 "snps,uart-16550-compatible"); 459 460 err = device_property_read_u32(dev, "reg-shift", &val); 461 if (!err) 462 p->regshift = val; 463 464 err = device_property_read_u32(dev, "reg-io-width", &val); 465 if (!err && val == 4) { 466 p->iotype = UPIO_MEM32; 467 p->serial_in = dw8250_serial_in32; 468 p->serial_out = dw8250_serial_out32; 469 } 470 471 if (device_property_read_bool(dev, "dcd-override")) { 472 /* Always report DCD as active */ 473 data->msr_mask_on |= UART_MSR_DCD; 474 data->msr_mask_off |= UART_MSR_DDCD; 475 } 476 477 if (device_property_read_bool(dev, "dsr-override")) { 478 /* Always report DSR as active */ 479 data->msr_mask_on |= UART_MSR_DSR; 480 data->msr_mask_off |= UART_MSR_DDSR; 481 } 482 483 if (device_property_read_bool(dev, "cts-override")) { 484 /* Always report CTS as active */ 485 data->msr_mask_on |= UART_MSR_CTS; 486 data->msr_mask_off |= UART_MSR_DCTS; 487 } 488 489 if (device_property_read_bool(dev, "ri-override")) { 490 /* Always report Ring indicator as inactive */ 491 data->msr_mask_off |= UART_MSR_RI; 492 data->msr_mask_off |= UART_MSR_TERI; 493 } 494 495 /* Always ask for fixed clock rate from a property. */ 496 device_property_read_u32(dev, "clock-frequency", &p->uartclk); 497 498 /* If there is separate baudclk, get the rate from it. */ 499 data->clk = devm_clk_get(dev, "baudclk"); 500 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) 501 data->clk = devm_clk_get(dev, NULL); 502 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) 503 return -EPROBE_DEFER; 504 if (!IS_ERR_OR_NULL(data->clk)) { 505 err = clk_prepare_enable(data->clk); 506 if (err) 507 dev_warn(dev, "could not enable optional baudclk: %d\n", 508 err); 509 else 510 p->uartclk = clk_get_rate(data->clk); 511 } 512 513 /* If no clock rate is defined, fail. */ 514 if (!p->uartclk) { 515 dev_err(dev, "clock rate not defined\n"); 516 return -EINVAL; 517 } 518 519 data->pclk = devm_clk_get(dev, "apb_pclk"); 520 if (IS_ERR(data->pclk) && PTR_ERR(data->pclk) == -EPROBE_DEFER) { 521 err = -EPROBE_DEFER; 522 goto err_clk; 523 } 524 if (!IS_ERR(data->pclk)) { 525 err = clk_prepare_enable(data->pclk); 526 if (err) { 527 dev_err(dev, "could not enable apb_pclk\n"); 528 goto err_clk; 529 } 530 } 531 532 data->rst = devm_reset_control_get_optional(dev, NULL); 533 if (IS_ERR(data->rst)) { 534 err = PTR_ERR(data->rst); 535 goto err_pclk; 536 } 537 reset_control_deassert(data->rst); 538 539 dw8250_quirks(p, data); 540 541 /* If the Busy Functionality is not implemented, don't handle it */ 542 if (data->uart_16550_compatible) 543 p->handle_irq = NULL; 544 545 if (!data->skip_autocfg) 546 dw8250_setup_port(p); 547 548 /* If we have a valid fifosize, try hooking up DMA */ 549 if (p->fifosize) { 550 data->dma.rxconf.src_maxburst = p->fifosize / 4; 551 data->dma.txconf.dst_maxburst = p->fifosize / 4; 552 uart.dma = &data->dma; 553 } 554 555 data->line = serial8250_register_8250_port(&uart); 556 if (data->line < 0) { 557 err = data->line; 558 goto err_reset; 559 } 560 561 platform_set_drvdata(pdev, data); 562 563 pm_runtime_set_active(dev); 564 pm_runtime_enable(dev); 565 566 return 0; 567 568 err_reset: 569 reset_control_assert(data->rst); 570 571 err_pclk: 572 if (!IS_ERR(data->pclk)) 573 clk_disable_unprepare(data->pclk); 574 575 err_clk: 576 if (!IS_ERR(data->clk)) 577 clk_disable_unprepare(data->clk); 578 579 return err; 580 } 581 582 static int dw8250_remove(struct platform_device *pdev) 583 { 584 struct dw8250_data *data = platform_get_drvdata(pdev); 585 586 pm_runtime_get_sync(&pdev->dev); 587 588 serial8250_unregister_port(data->line); 589 590 reset_control_assert(data->rst); 591 592 if (!IS_ERR(data->pclk)) 593 clk_disable_unprepare(data->pclk); 594 595 if (!IS_ERR(data->clk)) 596 clk_disable_unprepare(data->clk); 597 598 pm_runtime_disable(&pdev->dev); 599 pm_runtime_put_noidle(&pdev->dev); 600 601 return 0; 602 } 603 604 #ifdef CONFIG_PM_SLEEP 605 static int dw8250_suspend(struct device *dev) 606 { 607 struct dw8250_data *data = dev_get_drvdata(dev); 608 609 serial8250_suspend_port(data->line); 610 611 return 0; 612 } 613 614 static int dw8250_resume(struct device *dev) 615 { 616 struct dw8250_data *data = dev_get_drvdata(dev); 617 618 serial8250_resume_port(data->line); 619 620 return 0; 621 } 622 #endif /* CONFIG_PM_SLEEP */ 623 624 #ifdef CONFIG_PM 625 static int dw8250_runtime_suspend(struct device *dev) 626 { 627 struct dw8250_data *data = dev_get_drvdata(dev); 628 629 if (!IS_ERR(data->clk)) 630 clk_disable_unprepare(data->clk); 631 632 if (!IS_ERR(data->pclk)) 633 clk_disable_unprepare(data->pclk); 634 635 return 0; 636 } 637 638 static int dw8250_runtime_resume(struct device *dev) 639 { 640 struct dw8250_data *data = dev_get_drvdata(dev); 641 642 if (!IS_ERR(data->pclk)) 643 clk_prepare_enable(data->pclk); 644 645 if (!IS_ERR(data->clk)) 646 clk_prepare_enable(data->clk); 647 648 return 0; 649 } 650 #endif 651 652 static const struct dev_pm_ops dw8250_pm_ops = { 653 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 654 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 655 }; 656 657 static const struct of_device_id dw8250_of_match[] = { 658 { .compatible = "snps,dw-apb-uart" }, 659 { .compatible = "cavium,octeon-3860-uart" }, 660 { /* Sentinel */ } 661 }; 662 MODULE_DEVICE_TABLE(of, dw8250_of_match); 663 664 static const struct acpi_device_id dw8250_acpi_match[] = { 665 { "INT33C4", 0 }, 666 { "INT33C5", 0 }, 667 { "INT3434", 0 }, 668 { "INT3435", 0 }, 669 { "80860F0A", 0 }, 670 { "8086228A", 0 }, 671 { "APMC0D08", 0}, 672 { "AMD0020", 0 }, 673 { "AMDI0020", 0 }, 674 { "HISI0031", 0 }, 675 { }, 676 }; 677 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 678 679 static struct platform_driver dw8250_platform_driver = { 680 .driver = { 681 .name = "dw-apb-uart", 682 .pm = &dw8250_pm_ops, 683 .of_match_table = dw8250_of_match, 684 .acpi_match_table = ACPI_PTR(dw8250_acpi_match), 685 }, 686 .probe = dw8250_probe, 687 .remove = dw8250_remove, 688 }; 689 690 module_platform_driver(dw8250_platform_driver); 691 692 MODULE_AUTHOR("Jamie Iles"); 693 MODULE_LICENSE("GPL"); 694 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 695 MODULE_ALIAS("platform:dw-apb-uart"); 696