1 /* 2 * Synopsys DesignWare 8250 driver. 3 * 4 * Copyright 2011 Picochip, Jamie Iles. 5 * Copyright 2013 Intel Corporation 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 13 * LCR is written whilst busy. If it is, then a busy detect interrupt is 14 * raised, the LCR needs to be rewritten and the uart status register read. 15 */ 16 #include <linux/device.h> 17 #include <linux/io.h> 18 #include <linux/module.h> 19 #include <linux/serial_8250.h> 20 #include <linux/serial_core.h> 21 #include <linux/serial_reg.h> 22 #include <linux/of.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_platform.h> 25 #include <linux/platform_device.h> 26 #include <linux/slab.h> 27 #include <linux/acpi.h> 28 #include <linux/clk.h> 29 #include <linux/pm_runtime.h> 30 31 #include <asm/byteorder.h> 32 33 #include "8250.h" 34 35 /* Offsets for the DesignWare specific registers */ 36 #define DW_UART_USR 0x1f /* UART Status Register */ 37 #define DW_UART_CPR 0xf4 /* Component Parameter Register */ 38 #define DW_UART_UCV 0xf8 /* UART Component Version */ 39 40 /* Component Parameter Register bits */ 41 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) 42 #define DW_UART_CPR_AFCE_MODE (1 << 4) 43 #define DW_UART_CPR_THRE_MODE (1 << 5) 44 #define DW_UART_CPR_SIR_MODE (1 << 6) 45 #define DW_UART_CPR_SIR_LP_MODE (1 << 7) 46 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) 47 #define DW_UART_CPR_FIFO_ACCESS (1 << 9) 48 #define DW_UART_CPR_FIFO_STAT (1 << 10) 49 #define DW_UART_CPR_SHADOW (1 << 11) 50 #define DW_UART_CPR_ENCODED_PARMS (1 << 12) 51 #define DW_UART_CPR_DMA_EXTRA (1 << 13) 52 #define DW_UART_CPR_FIFO_MODE (0xff << 16) 53 /* Helper for fifo size calculation */ 54 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) 55 56 57 struct dw8250_data { 58 u8 usr_reg; 59 int last_mcr; 60 int line; 61 struct clk *clk; 62 struct uart_8250_dma dma; 63 }; 64 65 struct dw8250_acpi_desc { 66 void (*set_termios)(struct uart_port *p, struct ktermios *termios, 67 struct ktermios *old); 68 }; 69 70 #define BYT_PRV_CLK 0x800 71 #define BYT_PRV_CLK_EN (1 << 0) 72 #define BYT_PRV_CLK_M_VAL_SHIFT 1 73 #define BYT_PRV_CLK_N_VAL_SHIFT 16 74 #define BYT_PRV_CLK_UPDATE (1 << 31) 75 76 static void byt_set_termios(struct uart_port *p, struct ktermios *termios, 77 struct ktermios *old) 78 { 79 unsigned int baud = tty_termios_baud_rate(termios); 80 unsigned int m, n; 81 u32 reg; 82 83 /* 84 * For baud rates 0.5M, 1M, 1.5M, 2M, 2.5M, 3M, 3.5M and 4M the 85 * dividers must be adjusted. 86 * 87 * uartclk = (m / n) * 100 MHz, where m <= n 88 */ 89 switch (baud) { 90 case 500000: 91 case 1000000: 92 case 2000000: 93 case 4000000: 94 m = 64; 95 n = 100; 96 p->uartclk = 64000000; 97 break; 98 case 3500000: 99 m = 56; 100 n = 100; 101 p->uartclk = 56000000; 102 break; 103 case 1500000: 104 case 3000000: 105 m = 48; 106 n = 100; 107 p->uartclk = 48000000; 108 break; 109 case 2500000: 110 m = 40; 111 n = 100; 112 p->uartclk = 40000000; 113 break; 114 default: 115 m = 2304; 116 n = 3125; 117 p->uartclk = 73728000; 118 } 119 120 /* Reset the clock */ 121 reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); 122 writel(reg, p->membase + BYT_PRV_CLK); 123 reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE; 124 writel(reg, p->membase + BYT_PRV_CLK); 125 126 serial8250_do_set_termios(p, termios, old); 127 } 128 129 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 130 { 131 struct dw8250_data *d = p->private_data; 132 133 /* If reading MSR, report CTS asserted when auto-CTS/RTS enabled */ 134 if (offset == UART_MSR && d->last_mcr & UART_MCR_AFE) { 135 value |= UART_MSR_CTS; 136 value &= ~UART_MSR_DCTS; 137 } 138 139 return value; 140 } 141 142 static void dw8250_force_idle(struct uart_port *p) 143 { 144 serial8250_clear_and_reinit_fifos(container_of 145 (p, struct uart_8250_port, port)); 146 (void)p->serial_in(p, UART_RX); 147 } 148 149 static void dw8250_serial_out(struct uart_port *p, int offset, int value) 150 { 151 struct dw8250_data *d = p->private_data; 152 153 if (offset == UART_MCR) 154 d->last_mcr = value; 155 156 writeb(value, p->membase + (offset << p->regshift)); 157 158 /* Make sure LCR write wasn't ignored */ 159 if (offset == UART_LCR) { 160 int tries = 1000; 161 while (tries--) { 162 unsigned int lcr = p->serial_in(p, UART_LCR); 163 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 164 return; 165 dw8250_force_idle(p); 166 writeb(value, p->membase + (UART_LCR << p->regshift)); 167 } 168 dev_err(p->dev, "Couldn't set LCR to %d\n", value); 169 } 170 } 171 172 static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 173 { 174 unsigned int value = readb(p->membase + (offset << p->regshift)); 175 176 return dw8250_modify_msr(p, offset, value); 177 } 178 179 /* Read Back (rb) version to ensure register access ording. */ 180 static void dw8250_serial_out_rb(struct uart_port *p, int offset, int value) 181 { 182 dw8250_serial_out(p, offset, value); 183 dw8250_serial_in(p, UART_LCR); 184 } 185 186 static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 187 { 188 struct dw8250_data *d = p->private_data; 189 190 if (offset == UART_MCR) 191 d->last_mcr = value; 192 193 writel(value, p->membase + (offset << p->regshift)); 194 195 /* Make sure LCR write wasn't ignored */ 196 if (offset == UART_LCR) { 197 int tries = 1000; 198 while (tries--) { 199 unsigned int lcr = p->serial_in(p, UART_LCR); 200 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 201 return; 202 dw8250_force_idle(p); 203 writel(value, p->membase + (UART_LCR << p->regshift)); 204 } 205 dev_err(p->dev, "Couldn't set LCR to %d\n", value); 206 } 207 } 208 209 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 210 { 211 unsigned int value = readl(p->membase + (offset << p->regshift)); 212 213 return dw8250_modify_msr(p, offset, value); 214 } 215 216 static int dw8250_handle_irq(struct uart_port *p) 217 { 218 struct dw8250_data *d = p->private_data; 219 unsigned int iir = p->serial_in(p, UART_IIR); 220 221 if (serial8250_handle_irq(p, iir)) { 222 return 1; 223 } else if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 224 /* Clear the USR */ 225 (void)p->serial_in(p, d->usr_reg); 226 227 return 1; 228 } 229 230 return 0; 231 } 232 233 static void 234 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 235 { 236 if (!state) 237 pm_runtime_get_sync(port->dev); 238 239 serial8250_do_pm(port, state, old); 240 241 if (state) 242 pm_runtime_put_sync_suspend(port->dev); 243 } 244 245 static bool dw8250_dma_filter(struct dma_chan *chan, void *param) 246 { 247 struct dw8250_data *data = param; 248 249 return chan->chan_id == data->dma.tx_chan_id || 250 chan->chan_id == data->dma.rx_chan_id; 251 } 252 253 static void dw8250_setup_port(struct uart_8250_port *up) 254 { 255 struct uart_port *p = &up->port; 256 u32 reg = readl(p->membase + DW_UART_UCV); 257 258 /* 259 * If the Component Version Register returns zero, we know that 260 * ADDITIONAL_FEATURES are not enabled. No need to go any further. 261 */ 262 if (!reg) 263 return; 264 265 dev_dbg_ratelimited(p->dev, "Designware UART version %c.%c%c\n", 266 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); 267 268 reg = readl(p->membase + DW_UART_CPR); 269 if (!reg) 270 return; 271 272 /* Select the type based on fifo */ 273 if (reg & DW_UART_CPR_FIFO_MODE) { 274 p->type = PORT_16550A; 275 p->flags |= UPF_FIXED_TYPE; 276 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); 277 up->tx_loadsz = p->fifosize; 278 up->capabilities = UART_CAP_FIFO; 279 } 280 281 if (reg & DW_UART_CPR_AFCE_MODE) 282 up->capabilities |= UART_CAP_AFE; 283 } 284 285 static int dw8250_probe_of(struct uart_port *p, 286 struct dw8250_data *data) 287 { 288 struct device_node *np = p->dev->of_node; 289 u32 val; 290 bool has_ucv = true; 291 292 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 293 #ifdef __BIG_ENDIAN 294 /* 295 * Low order bits of these 64-bit registers, when 296 * accessed as a byte, are 7 bytes further down in the 297 * address space in big endian mode. 298 */ 299 p->membase += 7; 300 #endif 301 p->serial_out = dw8250_serial_out_rb; 302 p->flags = ASYNC_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 303 p->type = PORT_OCTEON; 304 data->usr_reg = 0x27; 305 has_ucv = false; 306 } else if (!of_property_read_u32(np, "reg-io-width", &val)) { 307 switch (val) { 308 case 1: 309 break; 310 case 4: 311 p->iotype = UPIO_MEM32; 312 p->serial_in = dw8250_serial_in32; 313 p->serial_out = dw8250_serial_out32; 314 break; 315 default: 316 dev_err(p->dev, "unsupported reg-io-width (%u)\n", val); 317 return -EINVAL; 318 } 319 } 320 if (has_ucv) 321 dw8250_setup_port(container_of(p, struct uart_8250_port, port)); 322 323 if (!of_property_read_u32(np, "reg-shift", &val)) 324 p->regshift = val; 325 326 /* clock got configured through clk api, all done */ 327 if (p->uartclk) 328 return 0; 329 330 /* try to find out clock frequency from DT as fallback */ 331 if (of_property_read_u32(np, "clock-frequency", &val)) { 332 dev_err(p->dev, "clk or clock-frequency not defined\n"); 333 return -EINVAL; 334 } 335 p->uartclk = val; 336 337 return 0; 338 } 339 340 static int dw8250_probe_acpi(struct uart_8250_port *up, 341 struct dw8250_data *data) 342 { 343 const struct acpi_device_id *id; 344 struct uart_port *p = &up->port; 345 struct dw8250_acpi_desc *acpi_desc; 346 347 dw8250_setup_port(up); 348 349 id = acpi_match_device(p->dev->driver->acpi_match_table, p->dev); 350 if (!id) 351 return -ENODEV; 352 353 p->iotype = UPIO_MEM32; 354 p->serial_in = dw8250_serial_in32; 355 p->serial_out = dw8250_serial_out32; 356 p->regshift = 2; 357 358 up->dma = &data->dma; 359 360 up->dma->rxconf.src_maxburst = p->fifosize / 4; 361 up->dma->txconf.dst_maxburst = p->fifosize / 4; 362 363 acpi_desc = (struct dw8250_acpi_desc *)id->driver_data; 364 if (!acpi_desc) 365 return 0; 366 367 if (acpi_desc->set_termios) 368 p->set_termios = acpi_desc->set_termios; 369 370 return 0; 371 } 372 373 static int dw8250_probe(struct platform_device *pdev) 374 { 375 struct uart_8250_port uart = {}; 376 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 377 struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 378 struct dw8250_data *data; 379 int err; 380 381 if (!regs || !irq) { 382 dev_err(&pdev->dev, "no registers/irq defined\n"); 383 return -EINVAL; 384 } 385 386 spin_lock_init(&uart.port.lock); 387 uart.port.mapbase = regs->start; 388 uart.port.irq = irq->start; 389 uart.port.handle_irq = dw8250_handle_irq; 390 uart.port.pm = dw8250_do_pm; 391 uart.port.type = PORT_8250; 392 uart.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_FIXED_PORT; 393 uart.port.dev = &pdev->dev; 394 395 uart.port.membase = devm_ioremap(&pdev->dev, regs->start, 396 resource_size(regs)); 397 if (!uart.port.membase) 398 return -ENOMEM; 399 400 data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); 401 if (!data) 402 return -ENOMEM; 403 404 data->usr_reg = DW_UART_USR; 405 data->clk = devm_clk_get(&pdev->dev, NULL); 406 if (!IS_ERR(data->clk)) { 407 clk_prepare_enable(data->clk); 408 uart.port.uartclk = clk_get_rate(data->clk); 409 } 410 411 data->dma.rx_chan_id = -1; 412 data->dma.tx_chan_id = -1; 413 data->dma.rx_param = data; 414 data->dma.tx_param = data; 415 data->dma.fn = dw8250_dma_filter; 416 417 uart.port.iotype = UPIO_MEM; 418 uart.port.serial_in = dw8250_serial_in; 419 uart.port.serial_out = dw8250_serial_out; 420 uart.port.private_data = data; 421 422 if (pdev->dev.of_node) { 423 err = dw8250_probe_of(&uart.port, data); 424 if (err) 425 return err; 426 } else if (ACPI_HANDLE(&pdev->dev)) { 427 err = dw8250_probe_acpi(&uart, data); 428 if (err) 429 return err; 430 } else { 431 return -ENODEV; 432 } 433 434 data->line = serial8250_register_8250_port(&uart); 435 if (data->line < 0) 436 return data->line; 437 438 platform_set_drvdata(pdev, data); 439 440 pm_runtime_set_active(&pdev->dev); 441 pm_runtime_enable(&pdev->dev); 442 443 return 0; 444 } 445 446 static int dw8250_remove(struct platform_device *pdev) 447 { 448 struct dw8250_data *data = platform_get_drvdata(pdev); 449 450 pm_runtime_get_sync(&pdev->dev); 451 452 serial8250_unregister_port(data->line); 453 454 if (!IS_ERR(data->clk)) 455 clk_disable_unprepare(data->clk); 456 457 pm_runtime_disable(&pdev->dev); 458 pm_runtime_put_noidle(&pdev->dev); 459 460 return 0; 461 } 462 463 #ifdef CONFIG_PM_SLEEP 464 static int dw8250_suspend(struct device *dev) 465 { 466 struct dw8250_data *data = dev_get_drvdata(dev); 467 468 serial8250_suspend_port(data->line); 469 470 return 0; 471 } 472 473 static int dw8250_resume(struct device *dev) 474 { 475 struct dw8250_data *data = dev_get_drvdata(dev); 476 477 serial8250_resume_port(data->line); 478 479 return 0; 480 } 481 #endif /* CONFIG_PM_SLEEP */ 482 483 #ifdef CONFIG_PM_RUNTIME 484 static int dw8250_runtime_suspend(struct device *dev) 485 { 486 struct dw8250_data *data = dev_get_drvdata(dev); 487 488 if (!IS_ERR(data->clk)) 489 clk_disable_unprepare(data->clk); 490 491 return 0; 492 } 493 494 static int dw8250_runtime_resume(struct device *dev) 495 { 496 struct dw8250_data *data = dev_get_drvdata(dev); 497 498 if (!IS_ERR(data->clk)) 499 clk_prepare_enable(data->clk); 500 501 return 0; 502 } 503 #endif 504 505 static const struct dev_pm_ops dw8250_pm_ops = { 506 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 507 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 508 }; 509 510 static const struct of_device_id dw8250_of_match[] = { 511 { .compatible = "snps,dw-apb-uart" }, 512 { .compatible = "cavium,octeon-3860-uart" }, 513 { /* Sentinel */ } 514 }; 515 MODULE_DEVICE_TABLE(of, dw8250_of_match); 516 517 static struct dw8250_acpi_desc byt_8250_desc = { 518 .set_termios = byt_set_termios, 519 }; 520 521 static const struct acpi_device_id dw8250_acpi_match[] = { 522 { "INT33C4", 0 }, 523 { "INT33C5", 0 }, 524 { "INT3434", 0 }, 525 { "INT3435", 0 }, 526 { "80860F0A", (kernel_ulong_t)&byt_8250_desc}, 527 { }, 528 }; 529 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 530 531 static struct platform_driver dw8250_platform_driver = { 532 .driver = { 533 .name = "dw-apb-uart", 534 .owner = THIS_MODULE, 535 .pm = &dw8250_pm_ops, 536 .of_match_table = dw8250_of_match, 537 .acpi_match_table = ACPI_PTR(dw8250_acpi_match), 538 }, 539 .probe = dw8250_probe, 540 .remove = dw8250_remove, 541 }; 542 543 module_platform_driver(dw8250_platform_driver); 544 545 MODULE_AUTHOR("Jamie Iles"); 546 MODULE_LICENSE("GPL"); 547 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 548