1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Synopsys DesignWare 8250 driver. 4 * 5 * Copyright 2011 Picochip, Jamie Iles. 6 * Copyright 2013 Intel Corporation 7 * 8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the 9 * LCR is written whilst busy. If it is, then a busy detect interrupt is 10 * raised, the LCR needs to be rewritten and the uart status register read. 11 */ 12 #include <linux/device.h> 13 #include <linux/io.h> 14 #include <linux/module.h> 15 #include <linux/serial_8250.h> 16 #include <linux/serial_reg.h> 17 #include <linux/of.h> 18 #include <linux/of_irq.h> 19 #include <linux/of_platform.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 #include <linux/acpi.h> 23 #include <linux/clk.h> 24 #include <linux/reset.h> 25 #include <linux/pm_runtime.h> 26 27 #include <asm/byteorder.h> 28 29 #include "8250.h" 30 31 /* Offsets for the DesignWare specific registers */ 32 #define DW_UART_USR 0x1f /* UART Status Register */ 33 #define DW_UART_CPR 0xf4 /* Component Parameter Register */ 34 #define DW_UART_UCV 0xf8 /* UART Component Version */ 35 36 /* Component Parameter Register bits */ 37 #define DW_UART_CPR_ABP_DATA_WIDTH (3 << 0) 38 #define DW_UART_CPR_AFCE_MODE (1 << 4) 39 #define DW_UART_CPR_THRE_MODE (1 << 5) 40 #define DW_UART_CPR_SIR_MODE (1 << 6) 41 #define DW_UART_CPR_SIR_LP_MODE (1 << 7) 42 #define DW_UART_CPR_ADDITIONAL_FEATURES (1 << 8) 43 #define DW_UART_CPR_FIFO_ACCESS (1 << 9) 44 #define DW_UART_CPR_FIFO_STAT (1 << 10) 45 #define DW_UART_CPR_SHADOW (1 << 11) 46 #define DW_UART_CPR_ENCODED_PARMS (1 << 12) 47 #define DW_UART_CPR_DMA_EXTRA (1 << 13) 48 #define DW_UART_CPR_FIFO_MODE (0xff << 16) 49 /* Helper for fifo size calculation */ 50 #define DW_UART_CPR_FIFO_SIZE(a) (((a >> 16) & 0xff) * 16) 51 52 /* DesignWare specific register fields */ 53 #define DW_UART_MCR_SIRE BIT(6) 54 55 struct dw8250_data { 56 u8 usr_reg; 57 int line; 58 int msr_mask_on; 59 int msr_mask_off; 60 struct clk *clk; 61 struct clk *pclk; 62 struct reset_control *rst; 63 struct uart_8250_dma dma; 64 65 unsigned int skip_autocfg:1; 66 unsigned int uart_16550_compatible:1; 67 }; 68 69 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value) 70 { 71 struct dw8250_data *d = p->private_data; 72 73 /* Override any modem control signals if needed */ 74 if (offset == UART_MSR) { 75 value |= d->msr_mask_on; 76 value &= ~d->msr_mask_off; 77 } 78 79 return value; 80 } 81 82 static void dw8250_force_idle(struct uart_port *p) 83 { 84 struct uart_8250_port *up = up_to_u8250p(p); 85 86 serial8250_clear_and_reinit_fifos(up); 87 (void)p->serial_in(p, UART_RX); 88 } 89 90 static void dw8250_check_lcr(struct uart_port *p, int value) 91 { 92 void __iomem *offset = p->membase + (UART_LCR << p->regshift); 93 int tries = 1000; 94 95 /* Make sure LCR write wasn't ignored */ 96 while (tries--) { 97 unsigned int lcr = p->serial_in(p, UART_LCR); 98 99 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR)) 100 return; 101 102 dw8250_force_idle(p); 103 104 #ifdef CONFIG_64BIT 105 if (p->type == PORT_OCTEON) 106 __raw_writeq(value & 0xff, offset); 107 else 108 #endif 109 if (p->iotype == UPIO_MEM32) 110 writel(value, offset); 111 else if (p->iotype == UPIO_MEM32BE) 112 iowrite32be(value, offset); 113 else 114 writeb(value, offset); 115 } 116 /* 117 * FIXME: this deadlocks if port->lock is already held 118 * dev_err(p->dev, "Couldn't set LCR to %d\n", value); 119 */ 120 } 121 122 static void dw8250_serial_out(struct uart_port *p, int offset, int value) 123 { 124 struct dw8250_data *d = p->private_data; 125 126 writeb(value, p->membase + (offset << p->regshift)); 127 128 if (offset == UART_LCR && !d->uart_16550_compatible) 129 dw8250_check_lcr(p, value); 130 } 131 132 static unsigned int dw8250_serial_in(struct uart_port *p, int offset) 133 { 134 unsigned int value = readb(p->membase + (offset << p->regshift)); 135 136 return dw8250_modify_msr(p, offset, value); 137 } 138 139 #ifdef CONFIG_64BIT 140 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset) 141 { 142 unsigned int value; 143 144 value = (u8)__raw_readq(p->membase + (offset << p->regshift)); 145 146 return dw8250_modify_msr(p, offset, value); 147 } 148 149 static void dw8250_serial_outq(struct uart_port *p, int offset, int value) 150 { 151 struct dw8250_data *d = p->private_data; 152 153 value &= 0xff; 154 __raw_writeq(value, p->membase + (offset << p->regshift)); 155 /* Read back to ensure register write ordering. */ 156 __raw_readq(p->membase + (UART_LCR << p->regshift)); 157 158 if (offset == UART_LCR && !d->uart_16550_compatible) 159 dw8250_check_lcr(p, value); 160 } 161 #endif /* CONFIG_64BIT */ 162 163 static void dw8250_serial_out32(struct uart_port *p, int offset, int value) 164 { 165 struct dw8250_data *d = p->private_data; 166 167 writel(value, p->membase + (offset << p->regshift)); 168 169 if (offset == UART_LCR && !d->uart_16550_compatible) 170 dw8250_check_lcr(p, value); 171 } 172 173 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset) 174 { 175 unsigned int value = readl(p->membase + (offset << p->regshift)); 176 177 return dw8250_modify_msr(p, offset, value); 178 } 179 180 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value) 181 { 182 struct dw8250_data *d = p->private_data; 183 184 iowrite32be(value, p->membase + (offset << p->regshift)); 185 186 if (offset == UART_LCR && !d->uart_16550_compatible) 187 dw8250_check_lcr(p, value); 188 } 189 190 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset) 191 { 192 unsigned int value = ioread32be(p->membase + (offset << p->regshift)); 193 194 return dw8250_modify_msr(p, offset, value); 195 } 196 197 198 static int dw8250_handle_irq(struct uart_port *p) 199 { 200 struct uart_8250_port *up = up_to_u8250p(p); 201 struct dw8250_data *d = p->private_data; 202 unsigned int iir = p->serial_in(p, UART_IIR); 203 unsigned int status; 204 unsigned long flags; 205 206 /* 207 * There are ways to get Designware-based UARTs into a state where 208 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual 209 * data available. If we see such a case then we'll do a bogus 210 * read. If we don't do this then the "RX TIMEOUT" interrupt will 211 * fire forever. 212 * 213 * This problem has only been observed so far when not in DMA mode 214 * so we limit the workaround only to non-DMA mode. 215 */ 216 if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) { 217 spin_lock_irqsave(&p->lock, flags); 218 status = p->serial_in(p, UART_LSR); 219 220 if (!(status & (UART_LSR_DR | UART_LSR_BI))) 221 (void) p->serial_in(p, UART_RX); 222 223 spin_unlock_irqrestore(&p->lock, flags); 224 } 225 226 if (serial8250_handle_irq(p, iir)) 227 return 1; 228 229 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) { 230 /* Clear the USR */ 231 (void)p->serial_in(p, d->usr_reg); 232 233 return 1; 234 } 235 236 return 0; 237 } 238 239 static void 240 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old) 241 { 242 if (!state) 243 pm_runtime_get_sync(port->dev); 244 245 serial8250_do_pm(port, state, old); 246 247 if (state) 248 pm_runtime_put_sync_suspend(port->dev); 249 } 250 251 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios, 252 struct ktermios *old) 253 { 254 unsigned int baud = tty_termios_baud_rate(termios); 255 unsigned int target_rate, min_rate, max_rate; 256 struct dw8250_data *d = p->private_data; 257 long rate; 258 int i, ret; 259 260 if (IS_ERR(d->clk) || !old) 261 goto out; 262 263 /* Find a clk rate within +/-1.6% of an integer multiple of baudx16 */ 264 target_rate = baud * 16; 265 min_rate = target_rate - (target_rate >> 6); 266 max_rate = target_rate + (target_rate >> 6); 267 268 for (i = 1; i <= UART_DIV_MAX; i++) { 269 rate = clk_round_rate(d->clk, i * target_rate); 270 if (rate >= i * min_rate && rate <= i * max_rate) 271 break; 272 } 273 if (i <= UART_DIV_MAX) { 274 clk_disable_unprepare(d->clk); 275 ret = clk_set_rate(d->clk, rate); 276 clk_prepare_enable(d->clk); 277 if (!ret) 278 p->uartclk = rate; 279 } 280 281 out: 282 p->status &= ~UPSTAT_AUTOCTS; 283 if (termios->c_cflag & CRTSCTS) 284 p->status |= UPSTAT_AUTOCTS; 285 286 serial8250_do_set_termios(p, termios, old); 287 } 288 289 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios) 290 { 291 struct uart_8250_port *up = up_to_u8250p(p); 292 unsigned int mcr = p->serial_in(p, UART_MCR); 293 294 if (up->capabilities & UART_CAP_IRDA) { 295 if (termios->c_line == N_IRDA) 296 mcr |= DW_UART_MCR_SIRE; 297 else 298 mcr &= ~DW_UART_MCR_SIRE; 299 300 p->serial_out(p, UART_MCR, mcr); 301 } 302 serial8250_do_set_ldisc(p, termios); 303 } 304 305 /* 306 * dw8250_fallback_dma_filter will prevent the UART from getting just any free 307 * channel on platforms that have DMA engines, but don't have any channels 308 * assigned to the UART. 309 * 310 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the 311 * core problem is fixed, this function is no longer needed. 312 */ 313 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param) 314 { 315 return false; 316 } 317 318 static bool dw8250_idma_filter(struct dma_chan *chan, void *param) 319 { 320 return param == chan->device->dev->parent; 321 } 322 323 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data) 324 { 325 if (p->dev->of_node) { 326 struct device_node *np = p->dev->of_node; 327 int id; 328 329 /* get index of serial line, if found in DT aliases */ 330 id = of_alias_get_id(np, "serial"); 331 if (id >= 0) 332 p->line = id; 333 #ifdef CONFIG_64BIT 334 if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) { 335 p->serial_in = dw8250_serial_inq; 336 p->serial_out = dw8250_serial_outq; 337 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE; 338 p->type = PORT_OCTEON; 339 data->usr_reg = 0x27; 340 data->skip_autocfg = true; 341 } 342 #endif 343 if (of_device_is_big_endian(p->dev->of_node)) { 344 p->iotype = UPIO_MEM32BE; 345 p->serial_in = dw8250_serial_in32be; 346 p->serial_out = dw8250_serial_out32be; 347 } 348 } else if (has_acpi_companion(p->dev)) { 349 const struct acpi_device_id *id; 350 351 id = acpi_match_device(p->dev->driver->acpi_match_table, 352 p->dev); 353 if (id && !strcmp(id->id, "APMC0D08")) { 354 p->iotype = UPIO_MEM32; 355 p->regshift = 2; 356 p->serial_in = dw8250_serial_in32; 357 data->uart_16550_compatible = true; 358 } 359 } 360 361 /* Platforms with iDMA */ 362 if (platform_get_resource_byname(to_platform_device(p->dev), 363 IORESOURCE_MEM, "lpss_priv")) { 364 data->dma.rx_param = p->dev->parent; 365 data->dma.tx_param = p->dev->parent; 366 data->dma.fn = dw8250_idma_filter; 367 } 368 } 369 370 static void dw8250_setup_port(struct uart_port *p) 371 { 372 struct uart_8250_port *up = up_to_u8250p(p); 373 u32 reg; 374 375 /* 376 * If the Component Version Register returns zero, we know that 377 * ADDITIONAL_FEATURES are not enabled. No need to go any further. 378 */ 379 if (p->iotype == UPIO_MEM32BE) 380 reg = ioread32be(p->membase + DW_UART_UCV); 381 else 382 reg = readl(p->membase + DW_UART_UCV); 383 if (!reg) 384 return; 385 386 dev_dbg(p->dev, "Designware UART version %c.%c%c\n", 387 (reg >> 24) & 0xff, (reg >> 16) & 0xff, (reg >> 8) & 0xff); 388 389 if (p->iotype == UPIO_MEM32BE) 390 reg = ioread32be(p->membase + DW_UART_CPR); 391 else 392 reg = readl(p->membase + DW_UART_CPR); 393 if (!reg) 394 return; 395 396 /* Select the type based on fifo */ 397 if (reg & DW_UART_CPR_FIFO_MODE) { 398 p->type = PORT_16550A; 399 p->flags |= UPF_FIXED_TYPE; 400 p->fifosize = DW_UART_CPR_FIFO_SIZE(reg); 401 up->capabilities = UART_CAP_FIFO; 402 } 403 404 if (reg & DW_UART_CPR_AFCE_MODE) 405 up->capabilities |= UART_CAP_AFE; 406 407 if (reg & DW_UART_CPR_SIR_MODE) 408 up->capabilities |= UART_CAP_IRDA; 409 } 410 411 static int dw8250_probe(struct platform_device *pdev) 412 { 413 struct uart_8250_port uart = {}; 414 struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 415 int irq = platform_get_irq(pdev, 0); 416 struct uart_port *p = &uart.port; 417 struct device *dev = &pdev->dev; 418 struct dw8250_data *data; 419 int err; 420 u32 val; 421 422 if (!regs) { 423 dev_err(dev, "no registers defined\n"); 424 return -EINVAL; 425 } 426 427 if (irq < 0) { 428 if (irq != -EPROBE_DEFER) 429 dev_err(dev, "cannot get irq\n"); 430 return irq; 431 } 432 433 spin_lock_init(&p->lock); 434 p->mapbase = regs->start; 435 p->irq = irq; 436 p->handle_irq = dw8250_handle_irq; 437 p->pm = dw8250_do_pm; 438 p->type = PORT_8250; 439 p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT; 440 p->dev = dev; 441 p->iotype = UPIO_MEM; 442 p->serial_in = dw8250_serial_in; 443 p->serial_out = dw8250_serial_out; 444 p->set_ldisc = dw8250_set_ldisc; 445 p->set_termios = dw8250_set_termios; 446 447 p->membase = devm_ioremap(dev, regs->start, resource_size(regs)); 448 if (!p->membase) 449 return -ENOMEM; 450 451 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 452 if (!data) 453 return -ENOMEM; 454 455 data->dma.fn = dw8250_fallback_dma_filter; 456 data->usr_reg = DW_UART_USR; 457 p->private_data = data; 458 459 data->uart_16550_compatible = device_property_read_bool(dev, 460 "snps,uart-16550-compatible"); 461 462 err = device_property_read_u32(dev, "reg-shift", &val); 463 if (!err) 464 p->regshift = val; 465 466 err = device_property_read_u32(dev, "reg-io-width", &val); 467 if (!err && val == 4) { 468 p->iotype = UPIO_MEM32; 469 p->serial_in = dw8250_serial_in32; 470 p->serial_out = dw8250_serial_out32; 471 } 472 473 if (device_property_read_bool(dev, "dcd-override")) { 474 /* Always report DCD as active */ 475 data->msr_mask_on |= UART_MSR_DCD; 476 data->msr_mask_off |= UART_MSR_DDCD; 477 } 478 479 if (device_property_read_bool(dev, "dsr-override")) { 480 /* Always report DSR as active */ 481 data->msr_mask_on |= UART_MSR_DSR; 482 data->msr_mask_off |= UART_MSR_DDSR; 483 } 484 485 if (device_property_read_bool(dev, "cts-override")) { 486 /* Always report CTS as active */ 487 data->msr_mask_on |= UART_MSR_CTS; 488 data->msr_mask_off |= UART_MSR_DCTS; 489 } 490 491 if (device_property_read_bool(dev, "ri-override")) { 492 /* Always report Ring indicator as inactive */ 493 data->msr_mask_off |= UART_MSR_RI; 494 data->msr_mask_off |= UART_MSR_TERI; 495 } 496 497 /* Always ask for fixed clock rate from a property. */ 498 device_property_read_u32(dev, "clock-frequency", &p->uartclk); 499 500 /* If there is separate baudclk, get the rate from it. */ 501 data->clk = devm_clk_get(dev, "baudclk"); 502 if (IS_ERR(data->clk) && PTR_ERR(data->clk) != -EPROBE_DEFER) 503 data->clk = devm_clk_get(dev, NULL); 504 if (IS_ERR(data->clk) && PTR_ERR(data->clk) == -EPROBE_DEFER) 505 return -EPROBE_DEFER; 506 if (!IS_ERR_OR_NULL(data->clk)) { 507 err = clk_prepare_enable(data->clk); 508 if (err) 509 dev_warn(dev, "could not enable optional baudclk: %d\n", 510 err); 511 else 512 p->uartclk = clk_get_rate(data->clk); 513 } 514 515 /* If no clock rate is defined, fail. */ 516 if (!p->uartclk) { 517 dev_err(dev, "clock rate not defined\n"); 518 return -EINVAL; 519 } 520 521 data->pclk = devm_clk_get(dev, "apb_pclk"); 522 if (IS_ERR(data->pclk) && PTR_ERR(data->pclk) == -EPROBE_DEFER) { 523 err = -EPROBE_DEFER; 524 goto err_clk; 525 } 526 if (!IS_ERR(data->pclk)) { 527 err = clk_prepare_enable(data->pclk); 528 if (err) { 529 dev_err(dev, "could not enable apb_pclk\n"); 530 goto err_clk; 531 } 532 } 533 534 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL); 535 if (IS_ERR(data->rst)) { 536 err = PTR_ERR(data->rst); 537 goto err_pclk; 538 } 539 reset_control_deassert(data->rst); 540 541 dw8250_quirks(p, data); 542 543 /* If the Busy Functionality is not implemented, don't handle it */ 544 if (data->uart_16550_compatible) 545 p->handle_irq = NULL; 546 547 if (!data->skip_autocfg) 548 dw8250_setup_port(p); 549 550 /* If we have a valid fifosize, try hooking up DMA */ 551 if (p->fifosize) { 552 data->dma.rxconf.src_maxburst = p->fifosize / 4; 553 data->dma.txconf.dst_maxburst = p->fifosize / 4; 554 uart.dma = &data->dma; 555 } 556 557 data->line = serial8250_register_8250_port(&uart); 558 if (data->line < 0) { 559 err = data->line; 560 goto err_reset; 561 } 562 563 platform_set_drvdata(pdev, data); 564 565 pm_runtime_set_active(dev); 566 pm_runtime_enable(dev); 567 568 return 0; 569 570 err_reset: 571 reset_control_assert(data->rst); 572 573 err_pclk: 574 if (!IS_ERR(data->pclk)) 575 clk_disable_unprepare(data->pclk); 576 577 err_clk: 578 if (!IS_ERR(data->clk)) 579 clk_disable_unprepare(data->clk); 580 581 return err; 582 } 583 584 static int dw8250_remove(struct platform_device *pdev) 585 { 586 struct dw8250_data *data = platform_get_drvdata(pdev); 587 588 pm_runtime_get_sync(&pdev->dev); 589 590 serial8250_unregister_port(data->line); 591 592 reset_control_assert(data->rst); 593 594 if (!IS_ERR(data->pclk)) 595 clk_disable_unprepare(data->pclk); 596 597 if (!IS_ERR(data->clk)) 598 clk_disable_unprepare(data->clk); 599 600 pm_runtime_disable(&pdev->dev); 601 pm_runtime_put_noidle(&pdev->dev); 602 603 return 0; 604 } 605 606 #ifdef CONFIG_PM_SLEEP 607 static int dw8250_suspend(struct device *dev) 608 { 609 struct dw8250_data *data = dev_get_drvdata(dev); 610 611 serial8250_suspend_port(data->line); 612 613 return 0; 614 } 615 616 static int dw8250_resume(struct device *dev) 617 { 618 struct dw8250_data *data = dev_get_drvdata(dev); 619 620 serial8250_resume_port(data->line); 621 622 return 0; 623 } 624 #endif /* CONFIG_PM_SLEEP */ 625 626 #ifdef CONFIG_PM 627 static int dw8250_runtime_suspend(struct device *dev) 628 { 629 struct dw8250_data *data = dev_get_drvdata(dev); 630 631 if (!IS_ERR(data->clk)) 632 clk_disable_unprepare(data->clk); 633 634 if (!IS_ERR(data->pclk)) 635 clk_disable_unprepare(data->pclk); 636 637 return 0; 638 } 639 640 static int dw8250_runtime_resume(struct device *dev) 641 { 642 struct dw8250_data *data = dev_get_drvdata(dev); 643 644 if (!IS_ERR(data->pclk)) 645 clk_prepare_enable(data->pclk); 646 647 if (!IS_ERR(data->clk)) 648 clk_prepare_enable(data->clk); 649 650 return 0; 651 } 652 #endif 653 654 static const struct dev_pm_ops dw8250_pm_ops = { 655 SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume) 656 SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL) 657 }; 658 659 static const struct of_device_id dw8250_of_match[] = { 660 { .compatible = "snps,dw-apb-uart" }, 661 { .compatible = "cavium,octeon-3860-uart" }, 662 { /* Sentinel */ } 663 }; 664 MODULE_DEVICE_TABLE(of, dw8250_of_match); 665 666 static const struct acpi_device_id dw8250_acpi_match[] = { 667 { "INT33C4", 0 }, 668 { "INT33C5", 0 }, 669 { "INT3434", 0 }, 670 { "INT3435", 0 }, 671 { "80860F0A", 0 }, 672 { "8086228A", 0 }, 673 { "APMC0D08", 0}, 674 { "AMD0020", 0 }, 675 { "AMDI0020", 0 }, 676 { "HISI0031", 0 }, 677 { }, 678 }; 679 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match); 680 681 static struct platform_driver dw8250_platform_driver = { 682 .driver = { 683 .name = "dw-apb-uart", 684 .pm = &dw8250_pm_ops, 685 .of_match_table = dw8250_of_match, 686 .acpi_match_table = ACPI_PTR(dw8250_acpi_match), 687 }, 688 .probe = dw8250_probe, 689 .remove = dw8250_remove, 690 }; 691 692 module_platform_driver(dw8250_platform_driver); 693 694 MODULE_AUTHOR("Jamie Iles"); 695 MODULE_LICENSE("GPL"); 696 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver"); 697 MODULE_ALIAS("platform:dw-apb-uart"); 698