1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Synopsys DesignWare 8250 driver.
4 *
5 * Copyright 2011 Picochip, Jamie Iles.
6 * Copyright 2013 Intel Corporation
7 *
8 * The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
9 * LCR is written whilst busy. If it is, then a busy detect interrupt is
10 * raised, the LCR needs to be rewritten and the uart status register read.
11 */
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/io.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/notifier.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/property.h>
22 #include <linux/reset.h>
23 #include <linux/slab.h>
24 #include <linux/workqueue.h>
25
26 #include <asm/byteorder.h>
27
28 #include <linux/serial_8250.h>
29 #include <linux/serial_reg.h>
30
31 #include "8250_dwlib.h"
32
33 /* Offsets for the DesignWare specific registers */
34 #define DW_UART_USR 0x1f /* UART Status Register */
35 #define DW_UART_DMASA 0xa8 /* DMA Software Ack */
36
37 #define OCTEON_UART_USR 0x27 /* UART Status Register */
38
39 #define RZN1_UART_TDMACR 0x10c /* DMA Control Register Transmit Mode */
40 #define RZN1_UART_RDMACR 0x110 /* DMA Control Register Receive Mode */
41
42 /* DesignWare specific register fields */
43 #define DW_UART_MCR_SIRE BIT(6)
44
45 /* Renesas specific register fields */
46 #define RZN1_UART_xDMACR_DMA_EN BIT(0)
47 #define RZN1_UART_xDMACR_1_WORD_BURST (0 << 1)
48 #define RZN1_UART_xDMACR_4_WORD_BURST (1 << 1)
49 #define RZN1_UART_xDMACR_8_WORD_BURST (2 << 1)
50 #define RZN1_UART_xDMACR_BLK_SZ(x) ((x) << 3)
51
52 /* Quirks */
53 #define DW_UART_QUIRK_OCTEON BIT(0)
54 #define DW_UART_QUIRK_ARMADA_38X BIT(1)
55 #define DW_UART_QUIRK_SKIP_SET_RATE BIT(2)
56 #define DW_UART_QUIRK_IS_DMA_FC BIT(3)
57 #define DW_UART_QUIRK_APMC0D08 BIT(4)
58 #define DW_UART_QUIRK_CPR_VALUE BIT(5)
59
60 struct dw8250_platform_data {
61 u8 usr_reg;
62 u32 cpr_value;
63 unsigned int quirks;
64 };
65
66 struct dw8250_data {
67 struct dw8250_port_data data;
68 const struct dw8250_platform_data *pdata;
69
70 int msr_mask_on;
71 int msr_mask_off;
72 struct clk *clk;
73 struct clk *pclk;
74 struct notifier_block clk_notifier;
75 struct work_struct clk_work;
76 struct reset_control *rst;
77
78 unsigned int skip_autocfg:1;
79 unsigned int uart_16550_compatible:1;
80 };
81
to_dw8250_data(struct dw8250_port_data * data)82 static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
83 {
84 return container_of(data, struct dw8250_data, data);
85 }
86
clk_to_dw8250_data(struct notifier_block * nb)87 static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
88 {
89 return container_of(nb, struct dw8250_data, clk_notifier);
90 }
91
work_to_dw8250_data(struct work_struct * work)92 static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work)
93 {
94 return container_of(work, struct dw8250_data, clk_work);
95 }
96
dw8250_modify_msr(struct uart_port * p,int offset,int value)97 static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
98 {
99 struct dw8250_data *d = to_dw8250_data(p->private_data);
100
101 /* Override any modem control signals if needed */
102 if (offset == UART_MSR) {
103 value |= d->msr_mask_on;
104 value &= ~d->msr_mask_off;
105 }
106
107 return value;
108 }
109
dw8250_force_idle(struct uart_port * p)110 static void dw8250_force_idle(struct uart_port *p)
111 {
112 struct uart_8250_port *up = up_to_u8250p(p);
113 unsigned int lsr;
114
115 serial8250_clear_and_reinit_fifos(up);
116
117 /*
118 * With PSLVERR_RESP_EN parameter set to 1, the device generates an
119 * error response when an attempt to read an empty RBR with FIFO
120 * enabled.
121 */
122 if (up->fcr & UART_FCR_ENABLE_FIFO) {
123 lsr = p->serial_in(p, UART_LSR);
124 if (!(lsr & UART_LSR_DR))
125 return;
126 }
127
128 (void)p->serial_in(p, UART_RX);
129 }
130
dw8250_check_lcr(struct uart_port * p,int value)131 static void dw8250_check_lcr(struct uart_port *p, int value)
132 {
133 void __iomem *offset = p->membase + (UART_LCR << p->regshift);
134 int tries = 1000;
135
136 /* Make sure LCR write wasn't ignored */
137 while (tries--) {
138 unsigned int lcr = p->serial_in(p, UART_LCR);
139
140 if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
141 return;
142
143 dw8250_force_idle(p);
144
145 #ifdef CONFIG_64BIT
146 if (p->type == PORT_OCTEON)
147 __raw_writeq(value & 0xff, offset);
148 else
149 #endif
150 if (p->iotype == UPIO_MEM32)
151 writel(value, offset);
152 else if (p->iotype == UPIO_MEM32BE)
153 iowrite32be(value, offset);
154 else
155 writeb(value, offset);
156 }
157 /*
158 * FIXME: this deadlocks if port->lock is already held
159 * dev_err(p->dev, "Couldn't set LCR to %d\n", value);
160 */
161 }
162
163 /* Returns once the transmitter is empty or we run out of retries */
dw8250_tx_wait_empty(struct uart_port * p)164 static void dw8250_tx_wait_empty(struct uart_port *p)
165 {
166 struct uart_8250_port *up = up_to_u8250p(p);
167 unsigned int tries = 20000;
168 unsigned int delay_threshold = tries - 1000;
169 unsigned int lsr;
170
171 while (tries--) {
172 lsr = readb (p->membase + (UART_LSR << p->regshift));
173 up->lsr_saved_flags |= lsr & up->lsr_save_mask;
174
175 if (lsr & UART_LSR_TEMT)
176 break;
177
178 /* The device is first given a chance to empty without delay,
179 * to avoid slowdowns at high bitrates. If after 1000 tries
180 * the buffer has still not emptied, allow more time for low-
181 * speed links. */
182 if (tries < delay_threshold)
183 udelay (1);
184 }
185 }
186
dw8250_serial_out(struct uart_port * p,int offset,int value)187 static void dw8250_serial_out(struct uart_port *p, int offset, int value)
188 {
189 struct dw8250_data *d = to_dw8250_data(p->private_data);
190
191 writeb(value, p->membase + (offset << p->regshift));
192
193 if (offset == UART_LCR && !d->uart_16550_compatible)
194 dw8250_check_lcr(p, value);
195 }
196
dw8250_serial_out38x(struct uart_port * p,int offset,int value)197 static void dw8250_serial_out38x(struct uart_port *p, int offset, int value)
198 {
199 /* Allow the TX to drain before we reconfigure */
200 if (offset == UART_LCR)
201 dw8250_tx_wait_empty(p);
202
203 dw8250_serial_out(p, offset, value);
204 }
205
dw8250_serial_in(struct uart_port * p,int offset)206 static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
207 {
208 unsigned int value = readb(p->membase + (offset << p->regshift));
209
210 return dw8250_modify_msr(p, offset, value);
211 }
212
213 #ifdef CONFIG_64BIT
dw8250_serial_inq(struct uart_port * p,int offset)214 static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
215 {
216 unsigned int value;
217
218 value = (u8)__raw_readq(p->membase + (offset << p->regshift));
219
220 return dw8250_modify_msr(p, offset, value);
221 }
222
dw8250_serial_outq(struct uart_port * p,int offset,int value)223 static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
224 {
225 struct dw8250_data *d = to_dw8250_data(p->private_data);
226
227 value &= 0xff;
228 __raw_writeq(value, p->membase + (offset << p->regshift));
229 /* Read back to ensure register write ordering. */
230 __raw_readq(p->membase + (UART_LCR << p->regshift));
231
232 if (offset == UART_LCR && !d->uart_16550_compatible)
233 dw8250_check_lcr(p, value);
234 }
235 #endif /* CONFIG_64BIT */
236
dw8250_serial_out32(struct uart_port * p,int offset,int value)237 static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
238 {
239 struct dw8250_data *d = to_dw8250_data(p->private_data);
240
241 writel(value, p->membase + (offset << p->regshift));
242
243 if (offset == UART_LCR && !d->uart_16550_compatible)
244 dw8250_check_lcr(p, value);
245 }
246
dw8250_serial_in32(struct uart_port * p,int offset)247 static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
248 {
249 unsigned int value = readl(p->membase + (offset << p->regshift));
250
251 return dw8250_modify_msr(p, offset, value);
252 }
253
dw8250_serial_out32be(struct uart_port * p,int offset,int value)254 static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
255 {
256 struct dw8250_data *d = to_dw8250_data(p->private_data);
257
258 iowrite32be(value, p->membase + (offset << p->regshift));
259
260 if (offset == UART_LCR && !d->uart_16550_compatible)
261 dw8250_check_lcr(p, value);
262 }
263
dw8250_serial_in32be(struct uart_port * p,int offset)264 static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
265 {
266 unsigned int value = ioread32be(p->membase + (offset << p->regshift));
267
268 return dw8250_modify_msr(p, offset, value);
269 }
270
271
dw8250_handle_irq(struct uart_port * p)272 static int dw8250_handle_irq(struct uart_port *p)
273 {
274 struct uart_8250_port *up = up_to_u8250p(p);
275 struct dw8250_data *d = to_dw8250_data(p->private_data);
276 unsigned int iir = p->serial_in(p, UART_IIR);
277 bool rx_timeout = (iir & 0x3f) == UART_IIR_RX_TIMEOUT;
278 unsigned int quirks = d->pdata->quirks;
279 unsigned int status;
280 unsigned long flags;
281
282 /*
283 * There are ways to get Designware-based UARTs into a state where
284 * they are asserting UART_IIR_RX_TIMEOUT but there is no actual
285 * data available. If we see such a case then we'll do a bogus
286 * read. If we don't do this then the "RX TIMEOUT" interrupt will
287 * fire forever.
288 *
289 * This problem has only been observed so far when not in DMA mode
290 * so we limit the workaround only to non-DMA mode.
291 */
292 if (!up->dma && rx_timeout) {
293 spin_lock_irqsave(&p->lock, flags);
294 status = serial_lsr_in(up);
295
296 if (!(status & (UART_LSR_DR | UART_LSR_BI)))
297 (void) p->serial_in(p, UART_RX);
298
299 spin_unlock_irqrestore(&p->lock, flags);
300 }
301
302 /* Manually stop the Rx DMA transfer when acting as flow controller */
303 if (quirks & DW_UART_QUIRK_IS_DMA_FC && up->dma && up->dma->rx_running && rx_timeout) {
304 spin_lock_irqsave(&p->lock, flags);
305 status = serial_lsr_in(up);
306 spin_unlock_irqrestore(&p->lock, flags);
307
308 if (status & (UART_LSR_DR | UART_LSR_BI)) {
309 dw8250_writel_ext(p, RZN1_UART_RDMACR, 0);
310 dw8250_writel_ext(p, DW_UART_DMASA, 1);
311 }
312 }
313
314 if (serial8250_handle_irq(p, iir))
315 return 1;
316
317 if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
318 /* Clear the USR */
319 (void)p->serial_in(p, d->pdata->usr_reg);
320
321 return 1;
322 }
323
324 return 0;
325 }
326
dw8250_clk_work_cb(struct work_struct * work)327 static void dw8250_clk_work_cb(struct work_struct *work)
328 {
329 struct dw8250_data *d = work_to_dw8250_data(work);
330 struct uart_8250_port *up;
331 unsigned long rate;
332
333 rate = clk_get_rate(d->clk);
334 if (rate <= 0)
335 return;
336
337 up = serial8250_get_port(d->data.line);
338
339 serial8250_update_uartclk(&up->port, rate);
340 }
341
dw8250_clk_notifier_cb(struct notifier_block * nb,unsigned long event,void * data)342 static int dw8250_clk_notifier_cb(struct notifier_block *nb,
343 unsigned long event, void *data)
344 {
345 struct dw8250_data *d = clk_to_dw8250_data(nb);
346
347 /*
348 * We have no choice but to defer the uartclk update due to two
349 * deadlocks. First one is caused by a recursive mutex lock which
350 * happens when clk_set_rate() is called from dw8250_set_termios().
351 * Second deadlock is more tricky and is caused by an inverted order of
352 * the clk and tty-port mutexes lock. It happens if clock rate change
353 * is requested asynchronously while set_termios() is executed between
354 * tty-port mutex lock and clk_set_rate() function invocation and
355 * vise-versa. Anyway if we didn't have the reference clock alteration
356 * in the dw8250_set_termios() method we wouldn't have needed this
357 * deferred event handling complication.
358 */
359 if (event == POST_RATE_CHANGE) {
360 queue_work(system_unbound_wq, &d->clk_work);
361 return NOTIFY_OK;
362 }
363
364 return NOTIFY_DONE;
365 }
366
367 static void
dw8250_do_pm(struct uart_port * port,unsigned int state,unsigned int old)368 dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
369 {
370 if (!state)
371 pm_runtime_get_sync(port->dev);
372
373 serial8250_do_pm(port, state, old);
374
375 if (state)
376 pm_runtime_put_sync_suspend(port->dev);
377 }
378
dw8250_set_termios(struct uart_port * p,struct ktermios * termios,const struct ktermios * old)379 static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
380 const struct ktermios *old)
381 {
382 unsigned long newrate = tty_termios_baud_rate(termios) * 16;
383 struct dw8250_data *d = to_dw8250_data(p->private_data);
384 long rate;
385 int ret;
386
387 clk_disable_unprepare(d->clk);
388 rate = clk_round_rate(d->clk, newrate);
389 if (rate > 0) {
390 /*
391 * Note that any clock-notifer worker will block in
392 * serial8250_update_uartclk() until we are done.
393 */
394 ret = clk_set_rate(d->clk, newrate);
395 if (!ret)
396 p->uartclk = rate;
397 }
398 clk_prepare_enable(d->clk);
399
400 dw8250_do_set_termios(p, termios, old);
401 }
402
dw8250_set_ldisc(struct uart_port * p,struct ktermios * termios)403 static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
404 {
405 struct uart_8250_port *up = up_to_u8250p(p);
406 unsigned int mcr = p->serial_in(p, UART_MCR);
407
408 if (up->capabilities & UART_CAP_IRDA) {
409 if (termios->c_line == N_IRDA)
410 mcr |= DW_UART_MCR_SIRE;
411 else
412 mcr &= ~DW_UART_MCR_SIRE;
413
414 p->serial_out(p, UART_MCR, mcr);
415 }
416 serial8250_do_set_ldisc(p, termios);
417 }
418
419 /*
420 * dw8250_fallback_dma_filter will prevent the UART from getting just any free
421 * channel on platforms that have DMA engines, but don't have any channels
422 * assigned to the UART.
423 *
424 * REVISIT: This is a work around for limitation in the DMA Engine API. Once the
425 * core problem is fixed, this function is no longer needed.
426 */
dw8250_fallback_dma_filter(struct dma_chan * chan,void * param)427 static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
428 {
429 return false;
430 }
431
dw8250_idma_filter(struct dma_chan * chan,void * param)432 static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
433 {
434 return param == chan->device->dev;
435 }
436
dw8250_rzn1_get_dmacr_burst(int max_burst)437 static u32 dw8250_rzn1_get_dmacr_burst(int max_burst)
438 {
439 if (max_burst >= 8)
440 return RZN1_UART_xDMACR_8_WORD_BURST;
441 else if (max_burst >= 4)
442 return RZN1_UART_xDMACR_4_WORD_BURST;
443 else
444 return RZN1_UART_xDMACR_1_WORD_BURST;
445 }
446
dw8250_prepare_tx_dma(struct uart_8250_port * p)447 static void dw8250_prepare_tx_dma(struct uart_8250_port *p)
448 {
449 struct uart_port *up = &p->port;
450 struct uart_8250_dma *dma = p->dma;
451 u32 val;
452
453 dw8250_writel_ext(up, RZN1_UART_TDMACR, 0);
454 val = dw8250_rzn1_get_dmacr_burst(dma->txconf.dst_maxburst) |
455 RZN1_UART_xDMACR_BLK_SZ(dma->tx_size) |
456 RZN1_UART_xDMACR_DMA_EN;
457 dw8250_writel_ext(up, RZN1_UART_TDMACR, val);
458 }
459
dw8250_prepare_rx_dma(struct uart_8250_port * p)460 static void dw8250_prepare_rx_dma(struct uart_8250_port *p)
461 {
462 struct uart_port *up = &p->port;
463 struct uart_8250_dma *dma = p->dma;
464 u32 val;
465
466 dw8250_writel_ext(up, RZN1_UART_RDMACR, 0);
467 val = dw8250_rzn1_get_dmacr_burst(dma->rxconf.src_maxburst) |
468 RZN1_UART_xDMACR_BLK_SZ(dma->rx_size) |
469 RZN1_UART_xDMACR_DMA_EN;
470 dw8250_writel_ext(up, RZN1_UART_RDMACR, val);
471 }
472
dw8250_quirks(struct uart_port * p,struct dw8250_data * data)473 static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
474 {
475 unsigned int quirks = data->pdata ? data->pdata->quirks : 0;
476 u32 cpr_value = data->pdata ? data->pdata->cpr_value : 0;
477
478 if (quirks & DW_UART_QUIRK_CPR_VALUE)
479 data->data.cpr_value = cpr_value;
480
481 #ifdef CONFIG_64BIT
482 if (quirks & DW_UART_QUIRK_OCTEON) {
483 p->serial_in = dw8250_serial_inq;
484 p->serial_out = dw8250_serial_outq;
485 p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
486 p->type = PORT_OCTEON;
487 data->skip_autocfg = true;
488 }
489 #endif
490
491 if (quirks & DW_UART_QUIRK_ARMADA_38X)
492 p->serial_out = dw8250_serial_out38x;
493 if (quirks & DW_UART_QUIRK_SKIP_SET_RATE)
494 p->set_termios = dw8250_do_set_termios;
495 if (quirks & DW_UART_QUIRK_IS_DMA_FC) {
496 data->data.dma.txconf.device_fc = 1;
497 data->data.dma.rxconf.device_fc = 1;
498 data->data.dma.prepare_tx_dma = dw8250_prepare_tx_dma;
499 data->data.dma.prepare_rx_dma = dw8250_prepare_rx_dma;
500 }
501 if (quirks & DW_UART_QUIRK_APMC0D08) {
502 p->iotype = UPIO_MEM32;
503 p->regshift = 2;
504 p->serial_in = dw8250_serial_in32;
505 data->uart_16550_compatible = true;
506 }
507
508 /* Platforms with iDMA 64-bit */
509 if (platform_get_resource_byname(to_platform_device(p->dev),
510 IORESOURCE_MEM, "lpss_priv")) {
511 data->data.dma.rx_param = p->dev->parent;
512 data->data.dma.tx_param = p->dev->parent;
513 data->data.dma.fn = dw8250_idma_filter;
514 }
515 }
516
dw8250_clk_disable_unprepare(void * data)517 static void dw8250_clk_disable_unprepare(void *data)
518 {
519 clk_disable_unprepare(data);
520 }
521
dw8250_reset_control_assert(void * data)522 static void dw8250_reset_control_assert(void *data)
523 {
524 reset_control_assert(data);
525 }
526
dw8250_probe(struct platform_device * pdev)527 static int dw8250_probe(struct platform_device *pdev)
528 {
529 struct uart_8250_port uart = {}, *up = &uart;
530 struct uart_port *p = &up->port;
531 struct device *dev = &pdev->dev;
532 struct dw8250_data *data;
533 struct resource *regs;
534 int err;
535
536 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
537 if (!regs)
538 return dev_err_probe(dev, -EINVAL, "no registers defined\n");
539
540 spin_lock_init(&p->lock);
541 p->handle_irq = dw8250_handle_irq;
542 p->pm = dw8250_do_pm;
543 p->type = PORT_8250;
544 p->flags = UPF_FIXED_PORT;
545 p->dev = dev;
546 p->set_ldisc = dw8250_set_ldisc;
547 p->set_termios = dw8250_set_termios;
548
549 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
550 if (!data)
551 return -ENOMEM;
552
553 data->data.dma.fn = dw8250_fallback_dma_filter;
554 data->pdata = device_get_match_data(p->dev);
555 p->private_data = &data->data;
556
557 data->uart_16550_compatible = device_property_read_bool(dev,
558 "snps,uart-16550-compatible");
559
560 p->mapbase = regs->start;
561 p->mapsize = resource_size(regs);
562
563 p->membase = devm_ioremap(dev, p->mapbase, p->mapsize);
564 if (!p->membase)
565 return -ENOMEM;
566
567 err = uart_read_port_properties(p);
568 /* no interrupt -> fall back to polling */
569 if (err == -ENXIO)
570 err = 0;
571 if (err)
572 return err;
573
574 switch (p->iotype) {
575 case UPIO_MEM:
576 p->serial_in = dw8250_serial_in;
577 p->serial_out = dw8250_serial_out;
578 break;
579 case UPIO_MEM32:
580 p->serial_in = dw8250_serial_in32;
581 p->serial_out = dw8250_serial_out32;
582 break;
583 case UPIO_MEM32BE:
584 p->serial_in = dw8250_serial_in32be;
585 p->serial_out = dw8250_serial_out32be;
586 break;
587 default:
588 return -ENODEV;
589 }
590
591 if (device_property_read_bool(dev, "dcd-override")) {
592 /* Always report DCD as active */
593 data->msr_mask_on |= UART_MSR_DCD;
594 data->msr_mask_off |= UART_MSR_DDCD;
595 }
596
597 if (device_property_read_bool(dev, "dsr-override")) {
598 /* Always report DSR as active */
599 data->msr_mask_on |= UART_MSR_DSR;
600 data->msr_mask_off |= UART_MSR_DDSR;
601 }
602
603 if (device_property_read_bool(dev, "cts-override")) {
604 /* Always report CTS as active */
605 data->msr_mask_on |= UART_MSR_CTS;
606 data->msr_mask_off |= UART_MSR_DCTS;
607 }
608
609 if (device_property_read_bool(dev, "ri-override")) {
610 /* Always report Ring indicator as inactive */
611 data->msr_mask_off |= UART_MSR_RI;
612 data->msr_mask_off |= UART_MSR_TERI;
613 }
614
615 /* If there is separate baudclk, get the rate from it. */
616 data->clk = devm_clk_get_optional(dev, "baudclk");
617 if (data->clk == NULL)
618 data->clk = devm_clk_get_optional(dev, NULL);
619 if (IS_ERR(data->clk))
620 return PTR_ERR(data->clk);
621
622 INIT_WORK(&data->clk_work, dw8250_clk_work_cb);
623 data->clk_notifier.notifier_call = dw8250_clk_notifier_cb;
624
625 err = clk_prepare_enable(data->clk);
626 if (err)
627 return dev_err_probe(dev, err, "could not enable optional baudclk\n");
628
629 err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->clk);
630 if (err)
631 return err;
632
633 if (data->clk)
634 p->uartclk = clk_get_rate(data->clk);
635
636 /* If no clock rate is defined, fail. */
637 if (!p->uartclk)
638 return dev_err_probe(dev, -EINVAL, "clock rate not defined\n");
639
640 data->pclk = devm_clk_get_optional(dev, "apb_pclk");
641 if (IS_ERR(data->pclk))
642 return PTR_ERR(data->pclk);
643
644 err = clk_prepare_enable(data->pclk);
645 if (err)
646 return dev_err_probe(dev, err, "could not enable apb_pclk\n");
647
648 err = devm_add_action_or_reset(dev, dw8250_clk_disable_unprepare, data->pclk);
649 if (err)
650 return err;
651
652 data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
653 if (IS_ERR(data->rst))
654 return PTR_ERR(data->rst);
655
656 reset_control_deassert(data->rst);
657
658 err = devm_add_action_or_reset(dev, dw8250_reset_control_assert, data->rst);
659 if (err)
660 return err;
661
662 dw8250_quirks(p, data);
663
664 /* If the Busy Functionality is not implemented, don't handle it */
665 if (data->uart_16550_compatible)
666 p->handle_irq = NULL;
667
668 if (!data->skip_autocfg)
669 dw8250_setup_port(p);
670
671 /* If we have a valid fifosize, try hooking up DMA */
672 if (p->fifosize) {
673 data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
674 data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
675 up->dma = &data->data.dma;
676 }
677
678 data->data.line = serial8250_register_8250_port(up);
679 if (data->data.line < 0)
680 return data->data.line;
681
682 /*
683 * Some platforms may provide a reference clock shared between several
684 * devices. In this case any clock state change must be known to the
685 * UART port at least post factum.
686 */
687 if (data->clk) {
688 err = clk_notifier_register(data->clk, &data->clk_notifier);
689 if (err)
690 return dev_err_probe(dev, err, "Failed to set the clock notifier\n");
691 queue_work(system_unbound_wq, &data->clk_work);
692 }
693
694 platform_set_drvdata(pdev, data);
695
696 pm_runtime_set_active(dev);
697 pm_runtime_enable(dev);
698
699 return 0;
700 }
701
dw8250_remove(struct platform_device * pdev)702 static int dw8250_remove(struct platform_device *pdev)
703 {
704 struct dw8250_data *data = platform_get_drvdata(pdev);
705 struct device *dev = &pdev->dev;
706
707 pm_runtime_get_sync(dev);
708
709 if (data->clk) {
710 clk_notifier_unregister(data->clk, &data->clk_notifier);
711
712 flush_work(&data->clk_work);
713 }
714
715 serial8250_unregister_port(data->data.line);
716
717 pm_runtime_disable(dev);
718 pm_runtime_put_noidle(dev);
719
720 return 0;
721 }
722
dw8250_suspend(struct device * dev)723 static int dw8250_suspend(struct device *dev)
724 {
725 struct dw8250_data *data = dev_get_drvdata(dev);
726
727 serial8250_suspend_port(data->data.line);
728
729 return 0;
730 }
731
dw8250_resume(struct device * dev)732 static int dw8250_resume(struct device *dev)
733 {
734 struct dw8250_data *data = dev_get_drvdata(dev);
735
736 serial8250_resume_port(data->data.line);
737
738 return 0;
739 }
740
dw8250_runtime_suspend(struct device * dev)741 static int dw8250_runtime_suspend(struct device *dev)
742 {
743 struct dw8250_data *data = dev_get_drvdata(dev);
744
745 clk_disable_unprepare(data->clk);
746
747 clk_disable_unprepare(data->pclk);
748
749 return 0;
750 }
751
dw8250_runtime_resume(struct device * dev)752 static int dw8250_runtime_resume(struct device *dev)
753 {
754 struct dw8250_data *data = dev_get_drvdata(dev);
755
756 clk_prepare_enable(data->pclk);
757
758 clk_prepare_enable(data->clk);
759
760 return 0;
761 }
762
763 static const struct dev_pm_ops dw8250_pm_ops = {
764 SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
765 RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
766 };
767
768 static const struct dw8250_platform_data dw8250_dw_apb = {
769 .usr_reg = DW_UART_USR,
770 };
771
772 static const struct dw8250_platform_data dw8250_octeon_3860_data = {
773 .usr_reg = OCTEON_UART_USR,
774 .quirks = DW_UART_QUIRK_OCTEON,
775 };
776
777 static const struct dw8250_platform_data dw8250_armada_38x_data = {
778 .usr_reg = DW_UART_USR,
779 .quirks = DW_UART_QUIRK_ARMADA_38X,
780 };
781
782 static const struct dw8250_platform_data dw8250_renesas_rzn1_data = {
783 .usr_reg = DW_UART_USR,
784 .cpr_value = 0x00012f32,
785 .quirks = DW_UART_QUIRK_CPR_VALUE | DW_UART_QUIRK_IS_DMA_FC,
786 };
787
788 static const struct dw8250_platform_data dw8250_skip_set_rate_data = {
789 .usr_reg = DW_UART_USR,
790 .quirks = DW_UART_QUIRK_SKIP_SET_RATE,
791 };
792
793 static const struct of_device_id dw8250_of_match[] = {
794 { .compatible = "snps,dw-apb-uart", .data = &dw8250_dw_apb },
795 { .compatible = "cavium,octeon-3860-uart", .data = &dw8250_octeon_3860_data },
796 { .compatible = "marvell,armada-38x-uart", .data = &dw8250_armada_38x_data },
797 { .compatible = "renesas,rzn1-uart", .data = &dw8250_renesas_rzn1_data },
798 { .compatible = "sophgo,sg2044-uart", .data = &dw8250_skip_set_rate_data },
799 { .compatible = "starfive,jh7100-uart", .data = &dw8250_skip_set_rate_data },
800 { /* Sentinel */ }
801 };
802 MODULE_DEVICE_TABLE(of, dw8250_of_match);
803
804 static const struct dw8250_platform_data dw8250_apmc0d08 = {
805 .usr_reg = DW_UART_USR,
806 .quirks = DW_UART_QUIRK_APMC0D08,
807 };
808
809 static const struct acpi_device_id dw8250_acpi_match[] = {
810 { "80860F0A", (kernel_ulong_t)&dw8250_dw_apb },
811 { "8086228A", (kernel_ulong_t)&dw8250_dw_apb },
812 { "AMD0020", (kernel_ulong_t)&dw8250_dw_apb },
813 { "AMDI0020", (kernel_ulong_t)&dw8250_dw_apb },
814 { "AMDI0022", (kernel_ulong_t)&dw8250_dw_apb },
815 { "APMC0D08", (kernel_ulong_t)&dw8250_apmc0d08 },
816 { "BRCM2032", (kernel_ulong_t)&dw8250_dw_apb },
817 { "HISI0031", (kernel_ulong_t)&dw8250_dw_apb },
818 { "INT33C4", (kernel_ulong_t)&dw8250_dw_apb },
819 { "INT33C5", (kernel_ulong_t)&dw8250_dw_apb },
820 { "INT3434", (kernel_ulong_t)&dw8250_dw_apb },
821 { "INT3435", (kernel_ulong_t)&dw8250_dw_apb },
822 { "INTC10EE", (kernel_ulong_t)&dw8250_dw_apb },
823 { },
824 };
825 MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
826
827 static struct platform_driver dw8250_platform_driver = {
828 .driver = {
829 .name = "dw-apb-uart",
830 .pm = pm_ptr(&dw8250_pm_ops),
831 .of_match_table = dw8250_of_match,
832 .acpi_match_table = dw8250_acpi_match,
833 },
834 .probe = dw8250_probe,
835 .remove = dw8250_remove,
836 };
837
838 module_platform_driver(dw8250_platform_driver);
839
840 MODULE_AUTHOR("Jamie Iles");
841 MODULE_LICENSE("GPL");
842 MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
843 MODULE_ALIAS("platform:dw-apb-uart");
844