1 /* 2 * Driver for 8250/16550-type serial ports 3 * 4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 5 * 6 * Copyright (C) 2001 Russell King. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * A note about mapbase / membase 14 * 15 * mapbase is the physical address of the IO port. 16 * membase is an 'ioremapped' cookie. 17 */ 18 19 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 20 #define SUPPORT_SYSRQ 21 #endif 22 23 #include <linux/module.h> 24 #include <linux/moduleparam.h> 25 #include <linux/ioport.h> 26 #include <linux/init.h> 27 #include <linux/console.h> 28 #include <linux/sysrq.h> 29 #include <linux/delay.h> 30 #include <linux/platform_device.h> 31 #include <linux/tty.h> 32 #include <linux/ratelimit.h> 33 #include <linux/tty_flip.h> 34 #include <linux/serial.h> 35 #include <linux/serial_8250.h> 36 #include <linux/nmi.h> 37 #include <linux/mutex.h> 38 #include <linux/slab.h> 39 #include <linux/uaccess.h> 40 #include <linux/pm_runtime.h> 41 #ifdef CONFIG_SPARC 42 #include <linux/sunserialcore.h> 43 #endif 44 45 #include <asm/io.h> 46 #include <asm/irq.h> 47 48 #include "8250.h" 49 50 /* 51 * Configuration: 52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option 53 * is unsafe when used on edge-triggered interrupts. 54 */ 55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS; 56 57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS; 58 59 static struct uart_driver serial8250_reg; 60 61 static int serial_index(struct uart_port *port) 62 { 63 return port->minor - 64; 64 } 65 66 static unsigned int skip_txen_test; /* force skip of txen test at init time */ 67 68 /* 69 * Debugging. 70 */ 71 #if 0 72 #define DEBUG_AUTOCONF(fmt...) printk(fmt) 73 #else 74 #define DEBUG_AUTOCONF(fmt...) do { } while (0) 75 #endif 76 77 #if 0 78 #define DEBUG_INTR(fmt...) printk(fmt) 79 #else 80 #define DEBUG_INTR(fmt...) do { } while (0) 81 #endif 82 83 #define PASS_LIMIT 512 84 85 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE) 86 87 88 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ 89 #define CONFIG_SERIAL_DETECT_IRQ 1 90 #endif 91 #ifdef CONFIG_SERIAL_8250_MANY_PORTS 92 #define CONFIG_SERIAL_MANY_PORTS 1 93 #endif 94 95 /* 96 * HUB6 is always on. This will be removed once the header 97 * files have been cleaned. 98 */ 99 #define CONFIG_HUB6 1 100 101 #include <asm/serial.h> 102 /* 103 * SERIAL_PORT_DFNS tells us about built-in ports that have no 104 * standard enumeration mechanism. Platforms that can find all 105 * serial ports via mechanisms like ACPI or PCI need not supply it. 106 */ 107 #ifndef SERIAL_PORT_DFNS 108 #define SERIAL_PORT_DFNS 109 #endif 110 111 static const struct old_serial_port old_serial_port[] = { 112 SERIAL_PORT_DFNS /* defined in asm/serial.h */ 113 }; 114 115 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS 116 117 #ifdef CONFIG_SERIAL_8250_RSA 118 119 #define PORT_RSA_MAX 4 120 static unsigned long probe_rsa[PORT_RSA_MAX]; 121 static unsigned int probe_rsa_count; 122 #endif /* CONFIG_SERIAL_8250_RSA */ 123 124 struct irq_info { 125 struct hlist_node node; 126 int irq; 127 spinlock_t lock; /* Protects list not the hash */ 128 struct list_head *head; 129 }; 130 131 #define NR_IRQ_HASH 32 /* Can be adjusted later */ 132 static struct hlist_head irq_lists[NR_IRQ_HASH]; 133 static DEFINE_MUTEX(hash_mutex); /* Used to walk the hash */ 134 135 /* 136 * Here we define the default xmit fifo size used for each type of UART. 137 */ 138 static const struct serial8250_config uart_config[] = { 139 [PORT_UNKNOWN] = { 140 .name = "unknown", 141 .fifo_size = 1, 142 .tx_loadsz = 1, 143 }, 144 [PORT_8250] = { 145 .name = "8250", 146 .fifo_size = 1, 147 .tx_loadsz = 1, 148 }, 149 [PORT_16450] = { 150 .name = "16450", 151 .fifo_size = 1, 152 .tx_loadsz = 1, 153 }, 154 [PORT_16550] = { 155 .name = "16550", 156 .fifo_size = 1, 157 .tx_loadsz = 1, 158 }, 159 [PORT_16550A] = { 160 .name = "16550A", 161 .fifo_size = 16, 162 .tx_loadsz = 16, 163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 164 .rxtrig_bytes = {1, 4, 8, 14}, 165 .flags = UART_CAP_FIFO, 166 }, 167 [PORT_CIRRUS] = { 168 .name = "Cirrus", 169 .fifo_size = 1, 170 .tx_loadsz = 1, 171 }, 172 [PORT_16650] = { 173 .name = "ST16650", 174 .fifo_size = 1, 175 .tx_loadsz = 1, 176 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 177 }, 178 [PORT_16650V2] = { 179 .name = "ST16650V2", 180 .fifo_size = 32, 181 .tx_loadsz = 16, 182 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 183 UART_FCR_T_TRIG_00, 184 .rxtrig_bytes = {8, 16, 24, 28}, 185 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 186 }, 187 [PORT_16750] = { 188 .name = "TI16750", 189 .fifo_size = 64, 190 .tx_loadsz = 64, 191 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | 192 UART_FCR7_64BYTE, 193 .rxtrig_bytes = {1, 16, 32, 56}, 194 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, 195 }, 196 [PORT_STARTECH] = { 197 .name = "Startech", 198 .fifo_size = 1, 199 .tx_loadsz = 1, 200 }, 201 [PORT_16C950] = { 202 .name = "16C950/954", 203 .fifo_size = 128, 204 .tx_loadsz = 128, 205 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 206 /* UART_CAP_EFR breaks billionon CF bluetooth card. */ 207 .flags = UART_CAP_FIFO | UART_CAP_SLEEP, 208 }, 209 [PORT_16654] = { 210 .name = "ST16654", 211 .fifo_size = 64, 212 .tx_loadsz = 32, 213 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 214 UART_FCR_T_TRIG_10, 215 .rxtrig_bytes = {8, 16, 56, 60}, 216 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 217 }, 218 [PORT_16850] = { 219 .name = "XR16850", 220 .fifo_size = 128, 221 .tx_loadsz = 128, 222 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 223 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, 224 }, 225 [PORT_RSA] = { 226 .name = "RSA", 227 .fifo_size = 2048, 228 .tx_loadsz = 2048, 229 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, 230 .flags = UART_CAP_FIFO, 231 }, 232 [PORT_NS16550A] = { 233 .name = "NS16550A", 234 .fifo_size = 16, 235 .tx_loadsz = 16, 236 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 237 .flags = UART_CAP_FIFO | UART_NATSEMI, 238 }, 239 [PORT_XSCALE] = { 240 .name = "XScale", 241 .fifo_size = 32, 242 .tx_loadsz = 32, 243 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 244 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE, 245 }, 246 [PORT_OCTEON] = { 247 .name = "OCTEON", 248 .fifo_size = 64, 249 .tx_loadsz = 64, 250 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 251 .flags = UART_CAP_FIFO, 252 }, 253 [PORT_AR7] = { 254 .name = "AR7", 255 .fifo_size = 16, 256 .tx_loadsz = 16, 257 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00, 258 .flags = UART_CAP_FIFO | UART_CAP_AFE, 259 }, 260 [PORT_U6_16550A] = { 261 .name = "U6_16550A", 262 .fifo_size = 64, 263 .tx_loadsz = 64, 264 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 265 .flags = UART_CAP_FIFO | UART_CAP_AFE, 266 }, 267 [PORT_TEGRA] = { 268 .name = "Tegra", 269 .fifo_size = 32, 270 .tx_loadsz = 8, 271 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | 272 UART_FCR_T_TRIG_01, 273 .rxtrig_bytes = {1, 4, 8, 14}, 274 .flags = UART_CAP_FIFO | UART_CAP_RTOIE, 275 }, 276 [PORT_XR17D15X] = { 277 .name = "XR17D15X", 278 .fifo_size = 64, 279 .tx_loadsz = 64, 280 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 281 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR | 282 UART_CAP_SLEEP, 283 }, 284 [PORT_XR17V35X] = { 285 .name = "XR17V35X", 286 .fifo_size = 256, 287 .tx_loadsz = 256, 288 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 | 289 UART_FCR_T_TRIG_11, 290 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR | 291 UART_CAP_SLEEP, 292 }, 293 [PORT_LPC3220] = { 294 .name = "LPC3220", 295 .fifo_size = 64, 296 .tx_loadsz = 32, 297 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO | 298 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00, 299 .flags = UART_CAP_FIFO, 300 }, 301 [PORT_BRCM_TRUMANAGE] = { 302 .name = "TruManage", 303 .fifo_size = 1, 304 .tx_loadsz = 1024, 305 .flags = UART_CAP_HFIFO, 306 }, 307 [PORT_8250_CIR] = { 308 .name = "CIR port" 309 }, 310 [PORT_ALTR_16550_F32] = { 311 .name = "Altera 16550 FIFO32", 312 .fifo_size = 32, 313 .tx_loadsz = 32, 314 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 315 .flags = UART_CAP_FIFO | UART_CAP_AFE, 316 }, 317 [PORT_ALTR_16550_F64] = { 318 .name = "Altera 16550 FIFO64", 319 .fifo_size = 64, 320 .tx_loadsz = 64, 321 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 322 .flags = UART_CAP_FIFO | UART_CAP_AFE, 323 }, 324 [PORT_ALTR_16550_F128] = { 325 .name = "Altera 16550 FIFO128", 326 .fifo_size = 128, 327 .tx_loadsz = 128, 328 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 329 .flags = UART_CAP_FIFO | UART_CAP_AFE, 330 }, 331 /* tx_loadsz is set to 63-bytes instead of 64-bytes to implement 332 workaround of errata A-008006 which states that tx_loadsz should be 333 configured less than Maximum supported fifo bytes */ 334 [PORT_16550A_FSL64] = { 335 .name = "16550A_FSL64", 336 .fifo_size = 64, 337 .tx_loadsz = 63, 338 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | 339 UART_FCR7_64BYTE, 340 .flags = UART_CAP_FIFO, 341 }, 342 }; 343 344 /* Uart divisor latch read */ 345 static int default_serial_dl_read(struct uart_8250_port *up) 346 { 347 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8; 348 } 349 350 /* Uart divisor latch write */ 351 static void default_serial_dl_write(struct uart_8250_port *up, int value) 352 { 353 serial_out(up, UART_DLL, value & 0xff); 354 serial_out(up, UART_DLM, value >> 8 & 0xff); 355 } 356 357 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X) 358 359 /* Au1x00/RT288x UART hardware has a weird register layout */ 360 static const s8 au_io_in_map[8] = { 361 0, /* UART_RX */ 362 2, /* UART_IER */ 363 3, /* UART_IIR */ 364 5, /* UART_LCR */ 365 6, /* UART_MCR */ 366 7, /* UART_LSR */ 367 8, /* UART_MSR */ 368 -1, /* UART_SCR (unmapped) */ 369 }; 370 371 static const s8 au_io_out_map[8] = { 372 1, /* UART_TX */ 373 2, /* UART_IER */ 374 4, /* UART_FCR */ 375 5, /* UART_LCR */ 376 6, /* UART_MCR */ 377 -1, /* UART_LSR (unmapped) */ 378 -1, /* UART_MSR (unmapped) */ 379 -1, /* UART_SCR (unmapped) */ 380 }; 381 382 static unsigned int au_serial_in(struct uart_port *p, int offset) 383 { 384 if (offset >= ARRAY_SIZE(au_io_in_map)) 385 return UINT_MAX; 386 offset = au_io_in_map[offset]; 387 if (offset < 0) 388 return UINT_MAX; 389 return __raw_readl(p->membase + (offset << p->regshift)); 390 } 391 392 static void au_serial_out(struct uart_port *p, int offset, int value) 393 { 394 if (offset >= ARRAY_SIZE(au_io_out_map)) 395 return; 396 offset = au_io_out_map[offset]; 397 if (offset < 0) 398 return; 399 __raw_writel(value, p->membase + (offset << p->regshift)); 400 } 401 402 /* Au1x00 haven't got a standard divisor latch */ 403 static int au_serial_dl_read(struct uart_8250_port *up) 404 { 405 return __raw_readl(up->port.membase + 0x28); 406 } 407 408 static void au_serial_dl_write(struct uart_8250_port *up, int value) 409 { 410 __raw_writel(value, up->port.membase + 0x28); 411 } 412 413 #endif 414 415 static unsigned int hub6_serial_in(struct uart_port *p, int offset) 416 { 417 offset = offset << p->regshift; 418 outb(p->hub6 - 1 + offset, p->iobase); 419 return inb(p->iobase + 1); 420 } 421 422 static void hub6_serial_out(struct uart_port *p, int offset, int value) 423 { 424 offset = offset << p->regshift; 425 outb(p->hub6 - 1 + offset, p->iobase); 426 outb(value, p->iobase + 1); 427 } 428 429 static unsigned int mem_serial_in(struct uart_port *p, int offset) 430 { 431 offset = offset << p->regshift; 432 return readb(p->membase + offset); 433 } 434 435 static void mem_serial_out(struct uart_port *p, int offset, int value) 436 { 437 offset = offset << p->regshift; 438 writeb(value, p->membase + offset); 439 } 440 441 static void mem32_serial_out(struct uart_port *p, int offset, int value) 442 { 443 offset = offset << p->regshift; 444 writel(value, p->membase + offset); 445 } 446 447 static unsigned int mem32_serial_in(struct uart_port *p, int offset) 448 { 449 offset = offset << p->regshift; 450 return readl(p->membase + offset); 451 } 452 453 static void mem32be_serial_out(struct uart_port *p, int offset, int value) 454 { 455 offset = offset << p->regshift; 456 iowrite32be(value, p->membase + offset); 457 } 458 459 static unsigned int mem32be_serial_in(struct uart_port *p, int offset) 460 { 461 offset = offset << p->regshift; 462 return ioread32be(p->membase + offset); 463 } 464 465 static unsigned int io_serial_in(struct uart_port *p, int offset) 466 { 467 offset = offset << p->regshift; 468 return inb(p->iobase + offset); 469 } 470 471 static void io_serial_out(struct uart_port *p, int offset, int value) 472 { 473 offset = offset << p->regshift; 474 outb(value, p->iobase + offset); 475 } 476 477 static int serial8250_default_handle_irq(struct uart_port *port); 478 static int exar_handle_irq(struct uart_port *port); 479 480 static void set_io_from_upio(struct uart_port *p) 481 { 482 struct uart_8250_port *up = up_to_u8250p(p); 483 484 up->dl_read = default_serial_dl_read; 485 up->dl_write = default_serial_dl_write; 486 487 switch (p->iotype) { 488 case UPIO_HUB6: 489 p->serial_in = hub6_serial_in; 490 p->serial_out = hub6_serial_out; 491 break; 492 493 case UPIO_MEM: 494 p->serial_in = mem_serial_in; 495 p->serial_out = mem_serial_out; 496 break; 497 498 case UPIO_MEM32: 499 p->serial_in = mem32_serial_in; 500 p->serial_out = mem32_serial_out; 501 break; 502 503 case UPIO_MEM32BE: 504 p->serial_in = mem32be_serial_in; 505 p->serial_out = mem32be_serial_out; 506 break; 507 508 #if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X) 509 case UPIO_AU: 510 p->serial_in = au_serial_in; 511 p->serial_out = au_serial_out; 512 up->dl_read = au_serial_dl_read; 513 up->dl_write = au_serial_dl_write; 514 break; 515 #endif 516 517 default: 518 p->serial_in = io_serial_in; 519 p->serial_out = io_serial_out; 520 break; 521 } 522 /* Remember loaded iotype */ 523 up->cur_iotype = p->iotype; 524 p->handle_irq = serial8250_default_handle_irq; 525 } 526 527 static void 528 serial_port_out_sync(struct uart_port *p, int offset, int value) 529 { 530 switch (p->iotype) { 531 case UPIO_MEM: 532 case UPIO_MEM32: 533 case UPIO_MEM32BE: 534 case UPIO_AU: 535 p->serial_out(p, offset, value); 536 p->serial_in(p, UART_LCR); /* safe, no side-effects */ 537 break; 538 default: 539 p->serial_out(p, offset, value); 540 } 541 } 542 543 /* 544 * For the 16C950 545 */ 546 static void serial_icr_write(struct uart_8250_port *up, int offset, int value) 547 { 548 serial_out(up, UART_SCR, offset); 549 serial_out(up, UART_ICR, value); 550 } 551 552 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) 553 { 554 unsigned int value; 555 556 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); 557 serial_out(up, UART_SCR, offset); 558 value = serial_in(up, UART_ICR); 559 serial_icr_write(up, UART_ACR, up->acr); 560 561 return value; 562 } 563 564 /* 565 * FIFO support. 566 */ 567 static void serial8250_clear_fifos(struct uart_8250_port *p) 568 { 569 if (p->capabilities & UART_CAP_FIFO) { 570 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO); 571 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO | 572 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 573 serial_out(p, UART_FCR, 0); 574 } 575 } 576 577 void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p) 578 { 579 serial8250_clear_fifos(p); 580 serial_out(p, UART_FCR, p->fcr); 581 } 582 EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos); 583 584 void serial8250_rpm_get(struct uart_8250_port *p) 585 { 586 if (!(p->capabilities & UART_CAP_RPM)) 587 return; 588 pm_runtime_get_sync(p->port.dev); 589 } 590 EXPORT_SYMBOL_GPL(serial8250_rpm_get); 591 592 void serial8250_rpm_put(struct uart_8250_port *p) 593 { 594 if (!(p->capabilities & UART_CAP_RPM)) 595 return; 596 pm_runtime_mark_last_busy(p->port.dev); 597 pm_runtime_put_autosuspend(p->port.dev); 598 } 599 EXPORT_SYMBOL_GPL(serial8250_rpm_put); 600 601 /* 602 * These two wrappers ensure that enable_runtime_pm_tx() can be called more than 603 * once and disable_runtime_pm_tx() will still disable RPM because the fifo is 604 * empty and the HW can idle again. 605 */ 606 static void serial8250_rpm_get_tx(struct uart_8250_port *p) 607 { 608 unsigned char rpm_active; 609 610 if (!(p->capabilities & UART_CAP_RPM)) 611 return; 612 613 rpm_active = xchg(&p->rpm_tx_active, 1); 614 if (rpm_active) 615 return; 616 pm_runtime_get_sync(p->port.dev); 617 } 618 619 static void serial8250_rpm_put_tx(struct uart_8250_port *p) 620 { 621 unsigned char rpm_active; 622 623 if (!(p->capabilities & UART_CAP_RPM)) 624 return; 625 626 rpm_active = xchg(&p->rpm_tx_active, 0); 627 if (!rpm_active) 628 return; 629 pm_runtime_mark_last_busy(p->port.dev); 630 pm_runtime_put_autosuspend(p->port.dev); 631 } 632 633 /* 634 * IER sleep support. UARTs which have EFRs need the "extended 635 * capability" bit enabled. Note that on XR16C850s, we need to 636 * reset LCR to write to IER. 637 */ 638 static void serial8250_set_sleep(struct uart_8250_port *p, int sleep) 639 { 640 unsigned char lcr = 0, efr = 0; 641 /* 642 * Exar UARTs have a SLEEP register that enables or disables 643 * each UART to enter sleep mode separately. On the XR17V35x the 644 * register is accessible to each UART at the UART_EXAR_SLEEP 645 * offset but the UART channel may only write to the corresponding 646 * bit. 647 */ 648 serial8250_rpm_get(p); 649 if ((p->port.type == PORT_XR17V35X) || 650 (p->port.type == PORT_XR17D15X)) { 651 serial_out(p, UART_EXAR_SLEEP, sleep ? 0xff : 0); 652 goto out; 653 } 654 655 if (p->capabilities & UART_CAP_SLEEP) { 656 if (p->capabilities & UART_CAP_EFR) { 657 lcr = serial_in(p, UART_LCR); 658 efr = serial_in(p, UART_EFR); 659 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); 660 serial_out(p, UART_EFR, UART_EFR_ECB); 661 serial_out(p, UART_LCR, 0); 662 } 663 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); 664 if (p->capabilities & UART_CAP_EFR) { 665 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B); 666 serial_out(p, UART_EFR, efr); 667 serial_out(p, UART_LCR, lcr); 668 } 669 } 670 out: 671 serial8250_rpm_put(p); 672 } 673 674 #ifdef CONFIG_SERIAL_8250_RSA 675 /* 676 * Attempts to turn on the RSA FIFO. Returns zero on failure. 677 * We set the port uart clock rate if we succeed. 678 */ 679 static int __enable_rsa(struct uart_8250_port *up) 680 { 681 unsigned char mode; 682 int result; 683 684 mode = serial_in(up, UART_RSA_MSR); 685 result = mode & UART_RSA_MSR_FIFO; 686 687 if (!result) { 688 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); 689 mode = serial_in(up, UART_RSA_MSR); 690 result = mode & UART_RSA_MSR_FIFO; 691 } 692 693 if (result) 694 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; 695 696 return result; 697 } 698 699 static void enable_rsa(struct uart_8250_port *up) 700 { 701 if (up->port.type == PORT_RSA) { 702 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { 703 spin_lock_irq(&up->port.lock); 704 __enable_rsa(up); 705 spin_unlock_irq(&up->port.lock); 706 } 707 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) 708 serial_out(up, UART_RSA_FRR, 0); 709 } 710 } 711 712 /* 713 * Attempts to turn off the RSA FIFO. Returns zero on failure. 714 * It is unknown why interrupts were disabled in here. However, 715 * the caller is expected to preserve this behaviour by grabbing 716 * the spinlock before calling this function. 717 */ 718 static void disable_rsa(struct uart_8250_port *up) 719 { 720 unsigned char mode; 721 int result; 722 723 if (up->port.type == PORT_RSA && 724 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { 725 spin_lock_irq(&up->port.lock); 726 727 mode = serial_in(up, UART_RSA_MSR); 728 result = !(mode & UART_RSA_MSR_FIFO); 729 730 if (!result) { 731 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); 732 mode = serial_in(up, UART_RSA_MSR); 733 result = !(mode & UART_RSA_MSR_FIFO); 734 } 735 736 if (result) 737 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; 738 spin_unlock_irq(&up->port.lock); 739 } 740 } 741 #endif /* CONFIG_SERIAL_8250_RSA */ 742 743 /* 744 * This is a quickie test to see how big the FIFO is. 745 * It doesn't work at all the time, more's the pity. 746 */ 747 static int size_fifo(struct uart_8250_port *up) 748 { 749 unsigned char old_fcr, old_mcr, old_lcr; 750 unsigned short old_dl; 751 int count; 752 753 old_lcr = serial_in(up, UART_LCR); 754 serial_out(up, UART_LCR, 0); 755 old_fcr = serial_in(up, UART_FCR); 756 old_mcr = serial_in(up, UART_MCR); 757 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 758 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); 759 serial_out(up, UART_MCR, UART_MCR_LOOP); 760 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 761 old_dl = serial_dl_read(up); 762 serial_dl_write(up, 0x0001); 763 serial_out(up, UART_LCR, 0x03); 764 for (count = 0; count < 256; count++) 765 serial_out(up, UART_TX, count); 766 mdelay(20);/* FIXME - schedule_timeout */ 767 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) && 768 (count < 256); count++) 769 serial_in(up, UART_RX); 770 serial_out(up, UART_FCR, old_fcr); 771 serial_out(up, UART_MCR, old_mcr); 772 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 773 serial_dl_write(up, old_dl); 774 serial_out(up, UART_LCR, old_lcr); 775 776 return count; 777 } 778 779 /* 780 * Read UART ID using the divisor method - set DLL and DLM to zero 781 * and the revision will be in DLL and device type in DLM. We 782 * preserve the device state across this. 783 */ 784 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) 785 { 786 unsigned char old_dll, old_dlm, old_lcr; 787 unsigned int id; 788 789 old_lcr = serial_in(p, UART_LCR); 790 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A); 791 792 old_dll = serial_in(p, UART_DLL); 793 old_dlm = serial_in(p, UART_DLM); 794 795 serial_out(p, UART_DLL, 0); 796 serial_out(p, UART_DLM, 0); 797 798 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8; 799 800 serial_out(p, UART_DLL, old_dll); 801 serial_out(p, UART_DLM, old_dlm); 802 serial_out(p, UART_LCR, old_lcr); 803 804 return id; 805 } 806 807 /* 808 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. 809 * When this function is called we know it is at least a StarTech 810 * 16650 V2, but it might be one of several StarTech UARTs, or one of 811 * its clones. (We treat the broken original StarTech 16650 V1 as a 812 * 16550, and why not? Startech doesn't seem to even acknowledge its 813 * existence.) 814 * 815 * What evil have men's minds wrought... 816 */ 817 static void autoconfig_has_efr(struct uart_8250_port *up) 818 { 819 unsigned int id1, id2, id3, rev; 820 821 /* 822 * Everything with an EFR has SLEEP 823 */ 824 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; 825 826 /* 827 * First we check to see if it's an Oxford Semiconductor UART. 828 * 829 * If we have to do this here because some non-National 830 * Semiconductor clone chips lock up if you try writing to the 831 * LSR register (which serial_icr_read does) 832 */ 833 834 /* 835 * Check for Oxford Semiconductor 16C950. 836 * 837 * EFR [4] must be set else this test fails. 838 * 839 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) 840 * claims that it's needed for 952 dual UART's (which are not 841 * recommended for new designs). 842 */ 843 up->acr = 0; 844 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 845 serial_out(up, UART_EFR, UART_EFR_ECB); 846 serial_out(up, UART_LCR, 0x00); 847 id1 = serial_icr_read(up, UART_ID1); 848 id2 = serial_icr_read(up, UART_ID2); 849 id3 = serial_icr_read(up, UART_ID3); 850 rev = serial_icr_read(up, UART_REV); 851 852 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev); 853 854 if (id1 == 0x16 && id2 == 0xC9 && 855 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) { 856 up->port.type = PORT_16C950; 857 858 /* 859 * Enable work around for the Oxford Semiconductor 952 rev B 860 * chip which causes it to seriously miscalculate baud rates 861 * when DLL is 0. 862 */ 863 if (id3 == 0x52 && rev == 0x01) 864 up->bugs |= UART_BUG_QUOT; 865 return; 866 } 867 868 /* 869 * We check for a XR16C850 by setting DLL and DLM to 0, and then 870 * reading back DLL and DLM. The chip type depends on the DLM 871 * value read back: 872 * 0x10 - XR16C850 and the DLL contains the chip revision. 873 * 0x12 - XR16C2850. 874 * 0x14 - XR16C854. 875 */ 876 id1 = autoconfig_read_divisor_id(up); 877 DEBUG_AUTOCONF("850id=%04x ", id1); 878 879 id2 = id1 >> 8; 880 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) { 881 up->port.type = PORT_16850; 882 return; 883 } 884 885 /* 886 * It wasn't an XR16C850. 887 * 888 * We distinguish between the '654 and the '650 by counting 889 * how many bytes are in the FIFO. I'm using this for now, 890 * since that's the technique that was sent to me in the 891 * serial driver update, but I'm not convinced this works. 892 * I've had problems doing this in the past. -TYT 893 */ 894 if (size_fifo(up) == 64) 895 up->port.type = PORT_16654; 896 else 897 up->port.type = PORT_16650V2; 898 } 899 900 /* 901 * We detected a chip without a FIFO. Only two fall into 902 * this category - the original 8250 and the 16450. The 903 * 16450 has a scratch register (accessible with LCR=0) 904 */ 905 static void autoconfig_8250(struct uart_8250_port *up) 906 { 907 unsigned char scratch, status1, status2; 908 909 up->port.type = PORT_8250; 910 911 scratch = serial_in(up, UART_SCR); 912 serial_out(up, UART_SCR, 0xa5); 913 status1 = serial_in(up, UART_SCR); 914 serial_out(up, UART_SCR, 0x5a); 915 status2 = serial_in(up, UART_SCR); 916 serial_out(up, UART_SCR, scratch); 917 918 if (status1 == 0xa5 && status2 == 0x5a) 919 up->port.type = PORT_16450; 920 } 921 922 static int broken_efr(struct uart_8250_port *up) 923 { 924 /* 925 * Exar ST16C2550 "A2" devices incorrectly detect as 926 * having an EFR, and report an ID of 0x0201. See 927 * http://linux.derkeiler.com/Mailing-Lists/Kernel/2004-11/4812.html 928 */ 929 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16) 930 return 1; 931 932 return 0; 933 } 934 935 /* 936 * We know that the chip has FIFOs. Does it have an EFR? The 937 * EFR is located in the same register position as the IIR and 938 * we know the top two bits of the IIR are currently set. The 939 * EFR should contain zero. Try to read the EFR. 940 */ 941 static void autoconfig_16550a(struct uart_8250_port *up) 942 { 943 unsigned char status1, status2; 944 unsigned int iersave; 945 946 up->port.type = PORT_16550A; 947 up->capabilities |= UART_CAP_FIFO; 948 949 /* 950 * XR17V35x UARTs have an extra divisor register, DLD 951 * that gets enabled with when DLAB is set which will 952 * cause the device to incorrectly match and assign 953 * port type to PORT_16650. The EFR for this UART is 954 * found at offset 0x09. Instead check the Deice ID (DVID) 955 * register for a 2, 4 or 8 port UART. 956 */ 957 if (up->port.flags & UPF_EXAR_EFR) { 958 status1 = serial_in(up, UART_EXAR_DVID); 959 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) { 960 DEBUG_AUTOCONF("Exar XR17V35x "); 961 up->port.type = PORT_XR17V35X; 962 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR | 963 UART_CAP_SLEEP; 964 965 return; 966 } 967 968 } 969 970 /* 971 * Check for presence of the EFR when DLAB is set. 972 * Only ST16C650V1 UARTs pass this test. 973 */ 974 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 975 if (serial_in(up, UART_EFR) == 0) { 976 serial_out(up, UART_EFR, 0xA8); 977 if (serial_in(up, UART_EFR) != 0) { 978 DEBUG_AUTOCONF("EFRv1 "); 979 up->port.type = PORT_16650; 980 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; 981 } else { 982 serial_out(up, UART_LCR, 0); 983 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | 984 UART_FCR7_64BYTE); 985 status1 = serial_in(up, UART_IIR) >> 5; 986 serial_out(up, UART_FCR, 0); 987 serial_out(up, UART_LCR, 0); 988 989 if (status1 == 7) 990 up->port.type = PORT_16550A_FSL64; 991 else 992 DEBUG_AUTOCONF("Motorola 8xxx DUART "); 993 } 994 serial_out(up, UART_EFR, 0); 995 return; 996 } 997 998 /* 999 * Maybe it requires 0xbf to be written to the LCR. 1000 * (other ST16C650V2 UARTs, TI16C752A, etc) 1001 */ 1002 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1003 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) { 1004 DEBUG_AUTOCONF("EFRv2 "); 1005 autoconfig_has_efr(up); 1006 return; 1007 } 1008 1009 /* 1010 * Check for a National Semiconductor SuperIO chip. 1011 * Attempt to switch to bank 2, read the value of the LOOP bit 1012 * from EXCR1. Switch back to bank 0, change it in MCR. Then 1013 * switch back to bank 2, read it from EXCR1 again and check 1014 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2 1015 */ 1016 serial_out(up, UART_LCR, 0); 1017 status1 = serial_in(up, UART_MCR); 1018 serial_out(up, UART_LCR, 0xE0); 1019 status2 = serial_in(up, 0x02); /* EXCR1 */ 1020 1021 if (!((status2 ^ status1) & UART_MCR_LOOP)) { 1022 serial_out(up, UART_LCR, 0); 1023 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP); 1024 serial_out(up, UART_LCR, 0xE0); 1025 status2 = serial_in(up, 0x02); /* EXCR1 */ 1026 serial_out(up, UART_LCR, 0); 1027 serial_out(up, UART_MCR, status1); 1028 1029 if ((status2 ^ status1) & UART_MCR_LOOP) { 1030 unsigned short quot; 1031 1032 serial_out(up, UART_LCR, 0xE0); 1033 1034 quot = serial_dl_read(up); 1035 quot <<= 3; 1036 1037 if (ns16550a_goto_highspeed(up)) 1038 serial_dl_write(up, quot); 1039 1040 serial_out(up, UART_LCR, 0); 1041 1042 up->port.uartclk = 921600*16; 1043 up->port.type = PORT_NS16550A; 1044 up->capabilities |= UART_NATSEMI; 1045 return; 1046 } 1047 } 1048 1049 /* 1050 * No EFR. Try to detect a TI16750, which only sets bit 5 of 1051 * the IIR when 64 byte FIFO mode is enabled when DLAB is set. 1052 * Try setting it with and without DLAB set. Cheap clones 1053 * set bit 5 without DLAB set. 1054 */ 1055 serial_out(up, UART_LCR, 0); 1056 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 1057 status1 = serial_in(up, UART_IIR) >> 5; 1058 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1059 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A); 1060 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE); 1061 status2 = serial_in(up, UART_IIR) >> 5; 1062 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1063 serial_out(up, UART_LCR, 0); 1064 1065 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2); 1066 1067 if (status1 == 6 && status2 == 7) { 1068 up->port.type = PORT_16750; 1069 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP; 1070 return; 1071 } 1072 1073 /* 1074 * Try writing and reading the UART_IER_UUE bit (b6). 1075 * If it works, this is probably one of the Xscale platform's 1076 * internal UARTs. 1077 * We're going to explicitly set the UUE bit to 0 before 1078 * trying to write and read a 1 just to make sure it's not 1079 * already a 1 and maybe locked there before we even start start. 1080 */ 1081 iersave = serial_in(up, UART_IER); 1082 serial_out(up, UART_IER, iersave & ~UART_IER_UUE); 1083 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) { 1084 /* 1085 * OK it's in a known zero state, try writing and reading 1086 * without disturbing the current state of the other bits. 1087 */ 1088 serial_out(up, UART_IER, iersave | UART_IER_UUE); 1089 if (serial_in(up, UART_IER) & UART_IER_UUE) { 1090 /* 1091 * It's an Xscale. 1092 * We'll leave the UART_IER_UUE bit set to 1 (enabled). 1093 */ 1094 DEBUG_AUTOCONF("Xscale "); 1095 up->port.type = PORT_XSCALE; 1096 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE; 1097 return; 1098 } 1099 } else { 1100 /* 1101 * If we got here we couldn't force the IER_UUE bit to 0. 1102 * Log it and continue. 1103 */ 1104 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 "); 1105 } 1106 serial_out(up, UART_IER, iersave); 1107 1108 /* 1109 * Exar uarts have EFR in a weird location 1110 */ 1111 if (up->port.flags & UPF_EXAR_EFR) { 1112 DEBUG_AUTOCONF("Exar XR17D15x "); 1113 up->port.type = PORT_XR17D15X; 1114 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR | 1115 UART_CAP_SLEEP; 1116 1117 return; 1118 } 1119 1120 /* 1121 * We distinguish between 16550A and U6 16550A by counting 1122 * how many bytes are in the FIFO. 1123 */ 1124 if (up->port.type == PORT_16550A && size_fifo(up) == 64) { 1125 up->port.type = PORT_U6_16550A; 1126 up->capabilities |= UART_CAP_AFE; 1127 } 1128 } 1129 1130 /* 1131 * This routine is called by rs_init() to initialize a specific serial 1132 * port. It determines what type of UART chip this serial port is 1133 * using: 8250, 16450, 16550, 16550A. The important question is 1134 * whether or not this UART is a 16550A or not, since this will 1135 * determine whether or not we can use its FIFO features or not. 1136 */ 1137 static void autoconfig(struct uart_8250_port *up) 1138 { 1139 unsigned char status1, scratch, scratch2, scratch3; 1140 unsigned char save_lcr, save_mcr; 1141 struct uart_port *port = &up->port; 1142 unsigned long flags; 1143 unsigned int old_capabilities; 1144 1145 if (!port->iobase && !port->mapbase && !port->membase) 1146 return; 1147 1148 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ", 1149 serial_index(port), port->iobase, port->membase); 1150 1151 /* 1152 * We really do need global IRQs disabled here - we're going to 1153 * be frobbing the chips IRQ enable register to see if it exists. 1154 */ 1155 spin_lock_irqsave(&port->lock, flags); 1156 1157 up->capabilities = 0; 1158 up->bugs = 0; 1159 1160 if (!(port->flags & UPF_BUGGY_UART)) { 1161 /* 1162 * Do a simple existence test first; if we fail this, 1163 * there's no point trying anything else. 1164 * 1165 * 0x80 is used as a nonsense port to prevent against 1166 * false positives due to ISA bus float. The 1167 * assumption is that 0x80 is a non-existent port; 1168 * which should be safe since include/asm/io.h also 1169 * makes this assumption. 1170 * 1171 * Note: this is safe as long as MCR bit 4 is clear 1172 * and the device is in "PC" mode. 1173 */ 1174 scratch = serial_in(up, UART_IER); 1175 serial_out(up, UART_IER, 0); 1176 #ifdef __i386__ 1177 outb(0xff, 0x080); 1178 #endif 1179 /* 1180 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL 1181 * 16C754B) allow only to modify them if an EFR bit is set. 1182 */ 1183 scratch2 = serial_in(up, UART_IER) & 0x0f; 1184 serial_out(up, UART_IER, 0x0F); 1185 #ifdef __i386__ 1186 outb(0, 0x080); 1187 #endif 1188 scratch3 = serial_in(up, UART_IER) & 0x0f; 1189 serial_out(up, UART_IER, scratch); 1190 if (scratch2 != 0 || scratch3 != 0x0F) { 1191 /* 1192 * We failed; there's nothing here 1193 */ 1194 spin_unlock_irqrestore(&port->lock, flags); 1195 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ", 1196 scratch2, scratch3); 1197 goto out; 1198 } 1199 } 1200 1201 save_mcr = serial_in(up, UART_MCR); 1202 save_lcr = serial_in(up, UART_LCR); 1203 1204 /* 1205 * Check to see if a UART is really there. Certain broken 1206 * internal modems based on the Rockwell chipset fail this 1207 * test, because they apparently don't implement the loopback 1208 * test mode. So this test is skipped on the COM 1 through 1209 * COM 4 ports. This *should* be safe, since no board 1210 * manufacturer would be stupid enough to design a board 1211 * that conflicts with COM 1-4 --- we hope! 1212 */ 1213 if (!(port->flags & UPF_SKIP_TEST)) { 1214 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A); 1215 status1 = serial_in(up, UART_MSR) & 0xF0; 1216 serial_out(up, UART_MCR, save_mcr); 1217 if (status1 != 0x90) { 1218 spin_unlock_irqrestore(&port->lock, flags); 1219 DEBUG_AUTOCONF("LOOP test failed (%02x) ", 1220 status1); 1221 goto out; 1222 } 1223 } 1224 1225 /* 1226 * We're pretty sure there's a port here. Lets find out what 1227 * type of port it is. The IIR top two bits allows us to find 1228 * out if it's 8250 or 16450, 16550, 16550A or later. This 1229 * determines what we test for next. 1230 * 1231 * We also initialise the EFR (if any) to zero for later. The 1232 * EFR occupies the same register location as the FCR and IIR. 1233 */ 1234 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 1235 serial_out(up, UART_EFR, 0); 1236 serial_out(up, UART_LCR, 0); 1237 1238 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO); 1239 scratch = serial_in(up, UART_IIR) >> 6; 1240 1241 switch (scratch) { 1242 case 0: 1243 autoconfig_8250(up); 1244 break; 1245 case 1: 1246 port->type = PORT_UNKNOWN; 1247 break; 1248 case 2: 1249 port->type = PORT_16550; 1250 break; 1251 case 3: 1252 autoconfig_16550a(up); 1253 break; 1254 } 1255 1256 #ifdef CONFIG_SERIAL_8250_RSA 1257 /* 1258 * Only probe for RSA ports if we got the region. 1259 */ 1260 if (port->type == PORT_16550A && up->probe & UART_PROBE_RSA && 1261 __enable_rsa(up)) 1262 port->type = PORT_RSA; 1263 #endif 1264 1265 serial_out(up, UART_LCR, save_lcr); 1266 1267 port->fifosize = uart_config[up->port.type].fifo_size; 1268 old_capabilities = up->capabilities; 1269 up->capabilities = uart_config[port->type].flags; 1270 up->tx_loadsz = uart_config[port->type].tx_loadsz; 1271 1272 if (port->type == PORT_UNKNOWN) 1273 goto out_lock; 1274 1275 /* 1276 * Reset the UART. 1277 */ 1278 #ifdef CONFIG_SERIAL_8250_RSA 1279 if (port->type == PORT_RSA) 1280 serial_out(up, UART_RSA_FRR, 0); 1281 #endif 1282 serial_out(up, UART_MCR, save_mcr); 1283 serial8250_clear_fifos(up); 1284 serial_in(up, UART_RX); 1285 if (up->capabilities & UART_CAP_UUE) 1286 serial_out(up, UART_IER, UART_IER_UUE); 1287 else 1288 serial_out(up, UART_IER, 0); 1289 1290 out_lock: 1291 spin_unlock_irqrestore(&port->lock, flags); 1292 if (up->capabilities != old_capabilities) { 1293 printk(KERN_WARNING 1294 "ttyS%d: detected caps %08x should be %08x\n", 1295 serial_index(port), old_capabilities, 1296 up->capabilities); 1297 } 1298 out: 1299 DEBUG_AUTOCONF("iir=%d ", scratch); 1300 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name); 1301 } 1302 1303 static void autoconfig_irq(struct uart_8250_port *up) 1304 { 1305 struct uart_port *port = &up->port; 1306 unsigned char save_mcr, save_ier; 1307 unsigned char save_ICP = 0; 1308 unsigned int ICP = 0; 1309 unsigned long irqs; 1310 int irq; 1311 1312 if (port->flags & UPF_FOURPORT) { 1313 ICP = (port->iobase & 0xfe0) | 0x1f; 1314 save_ICP = inb_p(ICP); 1315 outb_p(0x80, ICP); 1316 inb_p(ICP); 1317 } 1318 1319 /* forget possible initially masked and pending IRQ */ 1320 probe_irq_off(probe_irq_on()); 1321 save_mcr = serial_in(up, UART_MCR); 1322 save_ier = serial_in(up, UART_IER); 1323 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2); 1324 1325 irqs = probe_irq_on(); 1326 serial_out(up, UART_MCR, 0); 1327 udelay(10); 1328 if (port->flags & UPF_FOURPORT) { 1329 serial_out(up, UART_MCR, 1330 UART_MCR_DTR | UART_MCR_RTS); 1331 } else { 1332 serial_out(up, UART_MCR, 1333 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2); 1334 } 1335 serial_out(up, UART_IER, 0x0f); /* enable all intrs */ 1336 serial_in(up, UART_LSR); 1337 serial_in(up, UART_RX); 1338 serial_in(up, UART_IIR); 1339 serial_in(up, UART_MSR); 1340 serial_out(up, UART_TX, 0xFF); 1341 udelay(20); 1342 irq = probe_irq_off(irqs); 1343 1344 serial_out(up, UART_MCR, save_mcr); 1345 serial_out(up, UART_IER, save_ier); 1346 1347 if (port->flags & UPF_FOURPORT) 1348 outb_p(save_ICP, ICP); 1349 1350 port->irq = (irq > 0) ? irq : 0; 1351 } 1352 1353 static inline void __stop_tx(struct uart_8250_port *p) 1354 { 1355 if (p->ier & UART_IER_THRI) { 1356 p->ier &= ~UART_IER_THRI; 1357 serial_out(p, UART_IER, p->ier); 1358 serial8250_rpm_put_tx(p); 1359 } 1360 } 1361 1362 static void serial8250_stop_tx(struct uart_port *port) 1363 { 1364 struct uart_8250_port *up = up_to_u8250p(port); 1365 1366 serial8250_rpm_get(up); 1367 __stop_tx(up); 1368 1369 /* 1370 * We really want to stop the transmitter from sending. 1371 */ 1372 if (port->type == PORT_16C950) { 1373 up->acr |= UART_ACR_TXDIS; 1374 serial_icr_write(up, UART_ACR, up->acr); 1375 } 1376 serial8250_rpm_put(up); 1377 } 1378 1379 static void serial8250_start_tx(struct uart_port *port) 1380 { 1381 struct uart_8250_port *up = up_to_u8250p(port); 1382 1383 serial8250_rpm_get_tx(up); 1384 1385 if (up->dma && !up->dma->tx_dma(up)) 1386 return; 1387 1388 if (!(up->ier & UART_IER_THRI)) { 1389 up->ier |= UART_IER_THRI; 1390 serial_port_out(port, UART_IER, up->ier); 1391 1392 if (up->bugs & UART_BUG_TXEN) { 1393 unsigned char lsr; 1394 lsr = serial_in(up, UART_LSR); 1395 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; 1396 if (lsr & UART_LSR_THRE) 1397 serial8250_tx_chars(up); 1398 } 1399 } 1400 1401 /* 1402 * Re-enable the transmitter if we disabled it. 1403 */ 1404 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) { 1405 up->acr &= ~UART_ACR_TXDIS; 1406 serial_icr_write(up, UART_ACR, up->acr); 1407 } 1408 } 1409 1410 static void serial8250_throttle(struct uart_port *port) 1411 { 1412 port->throttle(port); 1413 } 1414 1415 static void serial8250_unthrottle(struct uart_port *port) 1416 { 1417 port->unthrottle(port); 1418 } 1419 1420 static void serial8250_stop_rx(struct uart_port *port) 1421 { 1422 struct uart_8250_port *up = up_to_u8250p(port); 1423 1424 serial8250_rpm_get(up); 1425 1426 up->ier &= ~(UART_IER_RLSI | UART_IER_RDI); 1427 up->port.read_status_mask &= ~UART_LSR_DR; 1428 serial_port_out(port, UART_IER, up->ier); 1429 1430 serial8250_rpm_put(up); 1431 } 1432 1433 static void serial8250_disable_ms(struct uart_port *port) 1434 { 1435 struct uart_8250_port *up = 1436 container_of(port, struct uart_8250_port, port); 1437 1438 /* no MSR capabilities */ 1439 if (up->bugs & UART_BUG_NOMSR) 1440 return; 1441 1442 up->ier &= ~UART_IER_MSI; 1443 serial_port_out(port, UART_IER, up->ier); 1444 } 1445 1446 static void serial8250_enable_ms(struct uart_port *port) 1447 { 1448 struct uart_8250_port *up = up_to_u8250p(port); 1449 1450 /* no MSR capabilities */ 1451 if (up->bugs & UART_BUG_NOMSR) 1452 return; 1453 1454 up->ier |= UART_IER_MSI; 1455 1456 serial8250_rpm_get(up); 1457 serial_port_out(port, UART_IER, up->ier); 1458 serial8250_rpm_put(up); 1459 } 1460 1461 /* 1462 * serial8250_rx_chars: processes according to the passed in LSR 1463 * value, and returns the remaining LSR bits not handled 1464 * by this Rx routine. 1465 */ 1466 unsigned char 1467 serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr) 1468 { 1469 struct uart_port *port = &up->port; 1470 unsigned char ch; 1471 int max_count = 256; 1472 char flag; 1473 1474 do { 1475 if (likely(lsr & UART_LSR_DR)) 1476 ch = serial_in(up, UART_RX); 1477 else 1478 /* 1479 * Intel 82571 has a Serial Over Lan device that will 1480 * set UART_LSR_BI without setting UART_LSR_DR when 1481 * it receives a break. To avoid reading from the 1482 * receive buffer without UART_LSR_DR bit set, we 1483 * just force the read character to be 0 1484 */ 1485 ch = 0; 1486 1487 flag = TTY_NORMAL; 1488 port->icount.rx++; 1489 1490 lsr |= up->lsr_saved_flags; 1491 up->lsr_saved_flags = 0; 1492 1493 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) { 1494 if (lsr & UART_LSR_BI) { 1495 lsr &= ~(UART_LSR_FE | UART_LSR_PE); 1496 port->icount.brk++; 1497 /* 1498 * We do the SysRQ and SAK checking 1499 * here because otherwise the break 1500 * may get masked by ignore_status_mask 1501 * or read_status_mask. 1502 */ 1503 if (uart_handle_break(port)) 1504 goto ignore_char; 1505 } else if (lsr & UART_LSR_PE) 1506 port->icount.parity++; 1507 else if (lsr & UART_LSR_FE) 1508 port->icount.frame++; 1509 if (lsr & UART_LSR_OE) 1510 port->icount.overrun++; 1511 1512 /* 1513 * Mask off conditions which should be ignored. 1514 */ 1515 lsr &= port->read_status_mask; 1516 1517 if (lsr & UART_LSR_BI) { 1518 DEBUG_INTR("handling break...."); 1519 flag = TTY_BREAK; 1520 } else if (lsr & UART_LSR_PE) 1521 flag = TTY_PARITY; 1522 else if (lsr & UART_LSR_FE) 1523 flag = TTY_FRAME; 1524 } 1525 if (uart_handle_sysrq_char(port, ch)) 1526 goto ignore_char; 1527 1528 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag); 1529 1530 ignore_char: 1531 lsr = serial_in(up, UART_LSR); 1532 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (--max_count > 0)); 1533 spin_unlock(&port->lock); 1534 tty_flip_buffer_push(&port->state->port); 1535 spin_lock(&port->lock); 1536 return lsr; 1537 } 1538 EXPORT_SYMBOL_GPL(serial8250_rx_chars); 1539 1540 void serial8250_tx_chars(struct uart_8250_port *up) 1541 { 1542 struct uart_port *port = &up->port; 1543 struct circ_buf *xmit = &port->state->xmit; 1544 int count; 1545 1546 if (port->x_char) { 1547 serial_out(up, UART_TX, port->x_char); 1548 port->icount.tx++; 1549 port->x_char = 0; 1550 return; 1551 } 1552 if (uart_tx_stopped(port)) { 1553 serial8250_stop_tx(port); 1554 return; 1555 } 1556 if (uart_circ_empty(xmit)) { 1557 __stop_tx(up); 1558 return; 1559 } 1560 1561 count = up->tx_loadsz; 1562 do { 1563 serial_out(up, UART_TX, xmit->buf[xmit->tail]); 1564 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 1565 port->icount.tx++; 1566 if (uart_circ_empty(xmit)) 1567 break; 1568 if (up->capabilities & UART_CAP_HFIFO) { 1569 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) != 1570 BOTH_EMPTY) 1571 break; 1572 } 1573 } while (--count > 0); 1574 1575 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 1576 uart_write_wakeup(port); 1577 1578 DEBUG_INTR("THRE..."); 1579 1580 /* 1581 * With RPM enabled, we have to wait until the FIFO is empty before the 1582 * HW can go idle. So we get here once again with empty FIFO and disable 1583 * the interrupt and RPM in __stop_tx() 1584 */ 1585 if (uart_circ_empty(xmit) && !(up->capabilities & UART_CAP_RPM)) 1586 __stop_tx(up); 1587 } 1588 EXPORT_SYMBOL_GPL(serial8250_tx_chars); 1589 1590 /* Caller holds uart port lock */ 1591 unsigned int serial8250_modem_status(struct uart_8250_port *up) 1592 { 1593 struct uart_port *port = &up->port; 1594 unsigned int status = serial_in(up, UART_MSR); 1595 1596 status |= up->msr_saved_flags; 1597 up->msr_saved_flags = 0; 1598 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI && 1599 port->state != NULL) { 1600 if (status & UART_MSR_TERI) 1601 port->icount.rng++; 1602 if (status & UART_MSR_DDSR) 1603 port->icount.dsr++; 1604 if (status & UART_MSR_DDCD) 1605 uart_handle_dcd_change(port, status & UART_MSR_DCD); 1606 if (status & UART_MSR_DCTS) 1607 uart_handle_cts_change(port, status & UART_MSR_CTS); 1608 1609 wake_up_interruptible(&port->state->port.delta_msr_wait); 1610 } 1611 1612 return status; 1613 } 1614 EXPORT_SYMBOL_GPL(serial8250_modem_status); 1615 1616 /* 1617 * This handles the interrupt from one port. 1618 */ 1619 int serial8250_handle_irq(struct uart_port *port, unsigned int iir) 1620 { 1621 unsigned char status; 1622 unsigned long flags; 1623 struct uart_8250_port *up = up_to_u8250p(port); 1624 int dma_err = 0; 1625 1626 if (iir & UART_IIR_NO_INT) 1627 return 0; 1628 1629 spin_lock_irqsave(&port->lock, flags); 1630 1631 status = serial_port_in(port, UART_LSR); 1632 1633 DEBUG_INTR("status = %x...", status); 1634 1635 if (status & (UART_LSR_DR | UART_LSR_BI)) { 1636 if (up->dma) 1637 dma_err = up->dma->rx_dma(up, iir); 1638 1639 if (!up->dma || dma_err) 1640 status = serial8250_rx_chars(up, status); 1641 } 1642 serial8250_modem_status(up); 1643 if ((!up->dma || (up->dma && up->dma->tx_err)) && 1644 (status & UART_LSR_THRE)) 1645 serial8250_tx_chars(up); 1646 1647 spin_unlock_irqrestore(&port->lock, flags); 1648 return 1; 1649 } 1650 EXPORT_SYMBOL_GPL(serial8250_handle_irq); 1651 1652 static int serial8250_default_handle_irq(struct uart_port *port) 1653 { 1654 struct uart_8250_port *up = up_to_u8250p(port); 1655 unsigned int iir; 1656 int ret; 1657 1658 serial8250_rpm_get(up); 1659 1660 iir = serial_port_in(port, UART_IIR); 1661 ret = serial8250_handle_irq(port, iir); 1662 1663 serial8250_rpm_put(up); 1664 return ret; 1665 } 1666 1667 /* 1668 * These Exar UARTs have an extra interrupt indicator that could 1669 * fire for a few unimplemented interrupts. One of which is a 1670 * wakeup event when coming out of sleep. Put this here just 1671 * to be on the safe side that these interrupts don't go unhandled. 1672 */ 1673 static int exar_handle_irq(struct uart_port *port) 1674 { 1675 unsigned char int0, int1, int2, int3; 1676 unsigned int iir = serial_port_in(port, UART_IIR); 1677 int ret; 1678 1679 ret = serial8250_handle_irq(port, iir); 1680 1681 if ((port->type == PORT_XR17V35X) || 1682 (port->type == PORT_XR17D15X)) { 1683 int0 = serial_port_in(port, 0x80); 1684 int1 = serial_port_in(port, 0x81); 1685 int2 = serial_port_in(port, 0x82); 1686 int3 = serial_port_in(port, 0x83); 1687 } 1688 1689 return ret; 1690 } 1691 1692 /* 1693 * This is the serial driver's interrupt routine. 1694 * 1695 * Arjan thinks the old way was overly complex, so it got simplified. 1696 * Alan disagrees, saying that need the complexity to handle the weird 1697 * nature of ISA shared interrupts. (This is a special exception.) 1698 * 1699 * In order to handle ISA shared interrupts properly, we need to check 1700 * that all ports have been serviced, and therefore the ISA interrupt 1701 * line has been de-asserted. 1702 * 1703 * This means we need to loop through all ports. checking that they 1704 * don't have an interrupt pending. 1705 */ 1706 static irqreturn_t serial8250_interrupt(int irq, void *dev_id) 1707 { 1708 struct irq_info *i = dev_id; 1709 struct list_head *l, *end = NULL; 1710 int pass_counter = 0, handled = 0; 1711 1712 DEBUG_INTR("serial8250_interrupt(%d)...", irq); 1713 1714 spin_lock(&i->lock); 1715 1716 l = i->head; 1717 do { 1718 struct uart_8250_port *up; 1719 struct uart_port *port; 1720 1721 up = list_entry(l, struct uart_8250_port, list); 1722 port = &up->port; 1723 1724 if (port->handle_irq(port)) { 1725 handled = 1; 1726 end = NULL; 1727 } else if (end == NULL) 1728 end = l; 1729 1730 l = l->next; 1731 1732 if (l == i->head && pass_counter++ > PASS_LIMIT) { 1733 /* If we hit this, we're dead. */ 1734 printk_ratelimited(KERN_ERR 1735 "serial8250: too much work for irq%d\n", irq); 1736 break; 1737 } 1738 } while (l != end); 1739 1740 spin_unlock(&i->lock); 1741 1742 DEBUG_INTR("end.\n"); 1743 1744 return IRQ_RETVAL(handled); 1745 } 1746 1747 /* 1748 * To support ISA shared interrupts, we need to have one interrupt 1749 * handler that ensures that the IRQ line has been deasserted 1750 * before returning. Failing to do this will result in the IRQ 1751 * line being stuck active, and, since ISA irqs are edge triggered, 1752 * no more IRQs will be seen. 1753 */ 1754 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up) 1755 { 1756 spin_lock_irq(&i->lock); 1757 1758 if (!list_empty(i->head)) { 1759 if (i->head == &up->list) 1760 i->head = i->head->next; 1761 list_del(&up->list); 1762 } else { 1763 BUG_ON(i->head != &up->list); 1764 i->head = NULL; 1765 } 1766 spin_unlock_irq(&i->lock); 1767 /* List empty so throw away the hash node */ 1768 if (i->head == NULL) { 1769 hlist_del(&i->node); 1770 kfree(i); 1771 } 1772 } 1773 1774 static int serial_link_irq_chain(struct uart_8250_port *up) 1775 { 1776 struct hlist_head *h; 1777 struct hlist_node *n; 1778 struct irq_info *i; 1779 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0; 1780 1781 mutex_lock(&hash_mutex); 1782 1783 h = &irq_lists[up->port.irq % NR_IRQ_HASH]; 1784 1785 hlist_for_each(n, h) { 1786 i = hlist_entry(n, struct irq_info, node); 1787 if (i->irq == up->port.irq) 1788 break; 1789 } 1790 1791 if (n == NULL) { 1792 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL); 1793 if (i == NULL) { 1794 mutex_unlock(&hash_mutex); 1795 return -ENOMEM; 1796 } 1797 spin_lock_init(&i->lock); 1798 i->irq = up->port.irq; 1799 hlist_add_head(&i->node, h); 1800 } 1801 mutex_unlock(&hash_mutex); 1802 1803 spin_lock_irq(&i->lock); 1804 1805 if (i->head) { 1806 list_add(&up->list, i->head); 1807 spin_unlock_irq(&i->lock); 1808 1809 ret = 0; 1810 } else { 1811 INIT_LIST_HEAD(&up->list); 1812 i->head = &up->list; 1813 spin_unlock_irq(&i->lock); 1814 irq_flags |= up->port.irqflags; 1815 ret = request_irq(up->port.irq, serial8250_interrupt, 1816 irq_flags, "serial", i); 1817 if (ret < 0) 1818 serial_do_unlink(i, up); 1819 } 1820 1821 return ret; 1822 } 1823 1824 static void serial_unlink_irq_chain(struct uart_8250_port *up) 1825 { 1826 /* 1827 * yes, some broken gcc emit "warning: 'i' may be used uninitialized" 1828 * but no, we are not going to take a patch that assigns NULL below. 1829 */ 1830 struct irq_info *i; 1831 struct hlist_node *n; 1832 struct hlist_head *h; 1833 1834 mutex_lock(&hash_mutex); 1835 1836 h = &irq_lists[up->port.irq % NR_IRQ_HASH]; 1837 1838 hlist_for_each(n, h) { 1839 i = hlist_entry(n, struct irq_info, node); 1840 if (i->irq == up->port.irq) 1841 break; 1842 } 1843 1844 BUG_ON(n == NULL); 1845 BUG_ON(i->head == NULL); 1846 1847 if (list_empty(i->head)) 1848 free_irq(up->port.irq, i); 1849 1850 serial_do_unlink(i, up); 1851 mutex_unlock(&hash_mutex); 1852 } 1853 1854 /* 1855 * This function is used to handle ports that do not have an 1856 * interrupt. This doesn't work very well for 16450's, but gives 1857 * barely passable results for a 16550A. (Although at the expense 1858 * of much CPU overhead). 1859 */ 1860 static void serial8250_timeout(unsigned long data) 1861 { 1862 struct uart_8250_port *up = (struct uart_8250_port *)data; 1863 1864 up->port.handle_irq(&up->port); 1865 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port)); 1866 } 1867 1868 static void serial8250_backup_timeout(unsigned long data) 1869 { 1870 struct uart_8250_port *up = (struct uart_8250_port *)data; 1871 unsigned int iir, ier = 0, lsr; 1872 unsigned long flags; 1873 1874 spin_lock_irqsave(&up->port.lock, flags); 1875 1876 /* 1877 * Must disable interrupts or else we risk racing with the interrupt 1878 * based handler. 1879 */ 1880 if (up->port.irq) { 1881 ier = serial_in(up, UART_IER); 1882 serial_out(up, UART_IER, 0); 1883 } 1884 1885 iir = serial_in(up, UART_IIR); 1886 1887 /* 1888 * This should be a safe test for anyone who doesn't trust the 1889 * IIR bits on their UART, but it's specifically designed for 1890 * the "Diva" UART used on the management processor on many HP 1891 * ia64 and parisc boxes. 1892 */ 1893 lsr = serial_in(up, UART_LSR); 1894 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; 1895 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) && 1896 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) && 1897 (lsr & UART_LSR_THRE)) { 1898 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT); 1899 iir |= UART_IIR_THRI; 1900 } 1901 1902 if (!(iir & UART_IIR_NO_INT)) 1903 serial8250_tx_chars(up); 1904 1905 if (up->port.irq) 1906 serial_out(up, UART_IER, ier); 1907 1908 spin_unlock_irqrestore(&up->port.lock, flags); 1909 1910 /* Standard timer interval plus 0.2s to keep the port running */ 1911 mod_timer(&up->timer, 1912 jiffies + uart_poll_timeout(&up->port) + HZ / 5); 1913 } 1914 1915 static int univ8250_setup_irq(struct uart_8250_port *up) 1916 { 1917 struct uart_port *port = &up->port; 1918 int retval = 0; 1919 1920 /* 1921 * The above check will only give an accurate result the first time 1922 * the port is opened so this value needs to be preserved. 1923 */ 1924 if (up->bugs & UART_BUG_THRE) { 1925 pr_debug("ttyS%d - using backup timer\n", serial_index(port)); 1926 1927 up->timer.function = serial8250_backup_timeout; 1928 up->timer.data = (unsigned long)up; 1929 mod_timer(&up->timer, jiffies + 1930 uart_poll_timeout(port) + HZ / 5); 1931 } 1932 1933 /* 1934 * If the "interrupt" for this port doesn't correspond with any 1935 * hardware interrupt, we use a timer-based system. The original 1936 * driver used to do this with IRQ0. 1937 */ 1938 if (!port->irq) { 1939 up->timer.data = (unsigned long)up; 1940 mod_timer(&up->timer, jiffies + uart_poll_timeout(port)); 1941 } else 1942 retval = serial_link_irq_chain(up); 1943 1944 return retval; 1945 } 1946 1947 static void univ8250_release_irq(struct uart_8250_port *up) 1948 { 1949 struct uart_port *port = &up->port; 1950 1951 del_timer_sync(&up->timer); 1952 up->timer.function = serial8250_timeout; 1953 if (port->irq) 1954 serial_unlink_irq_chain(up); 1955 } 1956 1957 static unsigned int serial8250_tx_empty(struct uart_port *port) 1958 { 1959 struct uart_8250_port *up = up_to_u8250p(port); 1960 unsigned long flags; 1961 unsigned int lsr; 1962 1963 serial8250_rpm_get(up); 1964 1965 spin_lock_irqsave(&port->lock, flags); 1966 lsr = serial_port_in(port, UART_LSR); 1967 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS; 1968 spin_unlock_irqrestore(&port->lock, flags); 1969 1970 serial8250_rpm_put(up); 1971 1972 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0; 1973 } 1974 1975 static unsigned int serial8250_get_mctrl(struct uart_port *port) 1976 { 1977 struct uart_8250_port *up = up_to_u8250p(port); 1978 unsigned int status; 1979 unsigned int ret; 1980 1981 serial8250_rpm_get(up); 1982 status = serial8250_modem_status(up); 1983 serial8250_rpm_put(up); 1984 1985 ret = 0; 1986 if (status & UART_MSR_DCD) 1987 ret |= TIOCM_CAR; 1988 if (status & UART_MSR_RI) 1989 ret |= TIOCM_RNG; 1990 if (status & UART_MSR_DSR) 1991 ret |= TIOCM_DSR; 1992 if (status & UART_MSR_CTS) 1993 ret |= TIOCM_CTS; 1994 return ret; 1995 } 1996 1997 void serial8250_do_set_mctrl(struct uart_port *port, unsigned int mctrl) 1998 { 1999 struct uart_8250_port *up = up_to_u8250p(port); 2000 unsigned char mcr = 0; 2001 2002 if (mctrl & TIOCM_RTS) 2003 mcr |= UART_MCR_RTS; 2004 if (mctrl & TIOCM_DTR) 2005 mcr |= UART_MCR_DTR; 2006 if (mctrl & TIOCM_OUT1) 2007 mcr |= UART_MCR_OUT1; 2008 if (mctrl & TIOCM_OUT2) 2009 mcr |= UART_MCR_OUT2; 2010 if (mctrl & TIOCM_LOOP) 2011 mcr |= UART_MCR_LOOP; 2012 2013 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr; 2014 2015 serial_port_out(port, UART_MCR, mcr); 2016 } 2017 EXPORT_SYMBOL_GPL(serial8250_do_set_mctrl); 2018 2019 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl) 2020 { 2021 if (port->set_mctrl) 2022 return port->set_mctrl(port, mctrl); 2023 return serial8250_do_set_mctrl(port, mctrl); 2024 } 2025 2026 static void serial8250_break_ctl(struct uart_port *port, int break_state) 2027 { 2028 struct uart_8250_port *up = up_to_u8250p(port); 2029 unsigned long flags; 2030 2031 serial8250_rpm_get(up); 2032 spin_lock_irqsave(&port->lock, flags); 2033 if (break_state == -1) 2034 up->lcr |= UART_LCR_SBC; 2035 else 2036 up->lcr &= ~UART_LCR_SBC; 2037 serial_port_out(port, UART_LCR, up->lcr); 2038 spin_unlock_irqrestore(&port->lock, flags); 2039 serial8250_rpm_put(up); 2040 } 2041 2042 /* 2043 * Wait for transmitter & holding register to empty 2044 */ 2045 static void wait_for_xmitr(struct uart_8250_port *up, int bits) 2046 { 2047 unsigned int status, tmout = 10000; 2048 2049 /* Wait up to 10ms for the character(s) to be sent. */ 2050 for (;;) { 2051 status = serial_in(up, UART_LSR); 2052 2053 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS; 2054 2055 if ((status & bits) == bits) 2056 break; 2057 if (--tmout == 0) 2058 break; 2059 udelay(1); 2060 } 2061 2062 /* Wait up to 1s for flow control if necessary */ 2063 if (up->port.flags & UPF_CONS_FLOW) { 2064 unsigned int tmout; 2065 for (tmout = 1000000; tmout; tmout--) { 2066 unsigned int msr = serial_in(up, UART_MSR); 2067 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS; 2068 if (msr & UART_MSR_CTS) 2069 break; 2070 udelay(1); 2071 touch_nmi_watchdog(); 2072 } 2073 } 2074 } 2075 2076 #ifdef CONFIG_CONSOLE_POLL 2077 /* 2078 * Console polling routines for writing and reading from the uart while 2079 * in an interrupt or debug context. 2080 */ 2081 2082 static int serial8250_get_poll_char(struct uart_port *port) 2083 { 2084 struct uart_8250_port *up = up_to_u8250p(port); 2085 unsigned char lsr; 2086 int status; 2087 2088 serial8250_rpm_get(up); 2089 2090 lsr = serial_port_in(port, UART_LSR); 2091 2092 if (!(lsr & UART_LSR_DR)) { 2093 status = NO_POLL_CHAR; 2094 goto out; 2095 } 2096 2097 status = serial_port_in(port, UART_RX); 2098 out: 2099 serial8250_rpm_put(up); 2100 return status; 2101 } 2102 2103 2104 static void serial8250_put_poll_char(struct uart_port *port, 2105 unsigned char c) 2106 { 2107 unsigned int ier; 2108 struct uart_8250_port *up = up_to_u8250p(port); 2109 2110 serial8250_rpm_get(up); 2111 /* 2112 * First save the IER then disable the interrupts 2113 */ 2114 ier = serial_port_in(port, UART_IER); 2115 if (up->capabilities & UART_CAP_UUE) 2116 serial_port_out(port, UART_IER, UART_IER_UUE); 2117 else 2118 serial_port_out(port, UART_IER, 0); 2119 2120 wait_for_xmitr(up, BOTH_EMPTY); 2121 /* 2122 * Send the character out. 2123 */ 2124 serial_port_out(port, UART_TX, c); 2125 2126 /* 2127 * Finally, wait for transmitter to become empty 2128 * and restore the IER 2129 */ 2130 wait_for_xmitr(up, BOTH_EMPTY); 2131 serial_port_out(port, UART_IER, ier); 2132 serial8250_rpm_put(up); 2133 } 2134 2135 #endif /* CONFIG_CONSOLE_POLL */ 2136 2137 int serial8250_do_startup(struct uart_port *port) 2138 { 2139 struct uart_8250_port *up = up_to_u8250p(port); 2140 unsigned long flags; 2141 unsigned char lsr, iir; 2142 int retval; 2143 2144 if (port->type == PORT_8250_CIR) 2145 return -ENODEV; 2146 2147 if (!port->fifosize) 2148 port->fifosize = uart_config[port->type].fifo_size; 2149 if (!up->tx_loadsz) 2150 up->tx_loadsz = uart_config[port->type].tx_loadsz; 2151 if (!up->capabilities) 2152 up->capabilities = uart_config[port->type].flags; 2153 up->mcr = 0; 2154 2155 if (port->iotype != up->cur_iotype) 2156 set_io_from_upio(port); 2157 2158 serial8250_rpm_get(up); 2159 if (port->type == PORT_16C950) { 2160 /* Wake up and initialize UART */ 2161 up->acr = 0; 2162 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 2163 serial_port_out(port, UART_EFR, UART_EFR_ECB); 2164 serial_port_out(port, UART_IER, 0); 2165 serial_port_out(port, UART_LCR, 0); 2166 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */ 2167 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 2168 serial_port_out(port, UART_EFR, UART_EFR_ECB); 2169 serial_port_out(port, UART_LCR, 0); 2170 } 2171 2172 #ifdef CONFIG_SERIAL_8250_RSA 2173 /* 2174 * If this is an RSA port, see if we can kick it up to the 2175 * higher speed clock. 2176 */ 2177 enable_rsa(up); 2178 #endif 2179 /* 2180 * Clear the FIFO buffers and disable them. 2181 * (they will be reenabled in set_termios()) 2182 */ 2183 serial8250_clear_fifos(up); 2184 2185 /* 2186 * Clear the interrupt registers. 2187 */ 2188 serial_port_in(port, UART_LSR); 2189 serial_port_in(port, UART_RX); 2190 serial_port_in(port, UART_IIR); 2191 serial_port_in(port, UART_MSR); 2192 2193 /* 2194 * At this point, there's no way the LSR could still be 0xff; 2195 * if it is, then bail out, because there's likely no UART 2196 * here. 2197 */ 2198 if (!(port->flags & UPF_BUGGY_UART) && 2199 (serial_port_in(port, UART_LSR) == 0xff)) { 2200 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n", 2201 serial_index(port)); 2202 retval = -ENODEV; 2203 goto out; 2204 } 2205 2206 /* 2207 * For a XR16C850, we need to set the trigger levels 2208 */ 2209 if (port->type == PORT_16850) { 2210 unsigned char fctr; 2211 2212 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); 2213 2214 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX); 2215 serial_port_out(port, UART_FCTR, 2216 fctr | UART_FCTR_TRGD | UART_FCTR_RX); 2217 serial_port_out(port, UART_TRG, UART_TRG_96); 2218 serial_port_out(port, UART_FCTR, 2219 fctr | UART_FCTR_TRGD | UART_FCTR_TX); 2220 serial_port_out(port, UART_TRG, UART_TRG_96); 2221 2222 serial_port_out(port, UART_LCR, 0); 2223 } 2224 2225 if (port->irq) { 2226 unsigned char iir1; 2227 /* 2228 * Test for UARTs that do not reassert THRE when the 2229 * transmitter is idle and the interrupt has already 2230 * been cleared. Real 16550s should always reassert 2231 * this interrupt whenever the transmitter is idle and 2232 * the interrupt is enabled. Delays are necessary to 2233 * allow register changes to become visible. 2234 */ 2235 spin_lock_irqsave(&port->lock, flags); 2236 if (up->port.irqflags & IRQF_SHARED) 2237 disable_irq_nosync(port->irq); 2238 2239 wait_for_xmitr(up, UART_LSR_THRE); 2240 serial_port_out_sync(port, UART_IER, UART_IER_THRI); 2241 udelay(1); /* allow THRE to set */ 2242 iir1 = serial_port_in(port, UART_IIR); 2243 serial_port_out(port, UART_IER, 0); 2244 serial_port_out_sync(port, UART_IER, UART_IER_THRI); 2245 udelay(1); /* allow a working UART time to re-assert THRE */ 2246 iir = serial_port_in(port, UART_IIR); 2247 serial_port_out(port, UART_IER, 0); 2248 2249 if (port->irqflags & IRQF_SHARED) 2250 enable_irq(port->irq); 2251 spin_unlock_irqrestore(&port->lock, flags); 2252 2253 /* 2254 * If the interrupt is not reasserted, or we otherwise 2255 * don't trust the iir, setup a timer to kick the UART 2256 * on a regular basis. 2257 */ 2258 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) || 2259 up->port.flags & UPF_BUG_THRE) { 2260 up->bugs |= UART_BUG_THRE; 2261 } 2262 } 2263 2264 retval = up->ops->setup_irq(up); 2265 if (retval) 2266 goto out; 2267 2268 /* 2269 * Now, initialize the UART 2270 */ 2271 serial_port_out(port, UART_LCR, UART_LCR_WLEN8); 2272 2273 spin_lock_irqsave(&port->lock, flags); 2274 if (up->port.flags & UPF_FOURPORT) { 2275 if (!up->port.irq) 2276 up->port.mctrl |= TIOCM_OUT1; 2277 } else 2278 /* 2279 * Most PC uarts need OUT2 raised to enable interrupts. 2280 */ 2281 if (port->irq) 2282 up->port.mctrl |= TIOCM_OUT2; 2283 2284 serial8250_set_mctrl(port, port->mctrl); 2285 2286 /* Serial over Lan (SoL) hack: 2287 Intel 8257x Gigabit ethernet chips have a 2288 16550 emulation, to be used for Serial Over Lan. 2289 Those chips take a longer time than a normal 2290 serial device to signalize that a transmission 2291 data was queued. Due to that, the above test generally 2292 fails. One solution would be to delay the reading of 2293 iir. However, this is not reliable, since the timeout 2294 is variable. So, let's just don't test if we receive 2295 TX irq. This way, we'll never enable UART_BUG_TXEN. 2296 */ 2297 if (up->port.flags & UPF_NO_TXEN_TEST) 2298 goto dont_test_tx_en; 2299 2300 /* 2301 * Do a quick test to see if we receive an 2302 * interrupt when we enable the TX irq. 2303 */ 2304 serial_port_out(port, UART_IER, UART_IER_THRI); 2305 lsr = serial_port_in(port, UART_LSR); 2306 iir = serial_port_in(port, UART_IIR); 2307 serial_port_out(port, UART_IER, 0); 2308 2309 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) { 2310 if (!(up->bugs & UART_BUG_TXEN)) { 2311 up->bugs |= UART_BUG_TXEN; 2312 pr_debug("ttyS%d - enabling bad tx status workarounds\n", 2313 serial_index(port)); 2314 } 2315 } else { 2316 up->bugs &= ~UART_BUG_TXEN; 2317 } 2318 2319 dont_test_tx_en: 2320 spin_unlock_irqrestore(&port->lock, flags); 2321 2322 /* 2323 * Clear the interrupt registers again for luck, and clear the 2324 * saved flags to avoid getting false values from polling 2325 * routines or the previous session. 2326 */ 2327 serial_port_in(port, UART_LSR); 2328 serial_port_in(port, UART_RX); 2329 serial_port_in(port, UART_IIR); 2330 serial_port_in(port, UART_MSR); 2331 up->lsr_saved_flags = 0; 2332 up->msr_saved_flags = 0; 2333 2334 /* 2335 * Request DMA channels for both RX and TX. 2336 */ 2337 if (up->dma) { 2338 retval = serial8250_request_dma(up); 2339 if (retval) { 2340 pr_warn_ratelimited("ttyS%d - failed to request DMA\n", 2341 serial_index(port)); 2342 up->dma = NULL; 2343 } 2344 } 2345 2346 /* 2347 * Finally, enable interrupts. Note: Modem status interrupts 2348 * are set via set_termios(), which will be occurring imminently 2349 * anyway, so we don't enable them here. 2350 */ 2351 up->ier = UART_IER_RLSI | UART_IER_RDI; 2352 serial_port_out(port, UART_IER, up->ier); 2353 2354 if (port->flags & UPF_FOURPORT) { 2355 unsigned int icp; 2356 /* 2357 * Enable interrupts on the AST Fourport board 2358 */ 2359 icp = (port->iobase & 0xfe0) | 0x01f; 2360 outb_p(0x80, icp); 2361 inb_p(icp); 2362 } 2363 retval = 0; 2364 out: 2365 serial8250_rpm_put(up); 2366 return retval; 2367 } 2368 EXPORT_SYMBOL_GPL(serial8250_do_startup); 2369 2370 static int serial8250_startup(struct uart_port *port) 2371 { 2372 if (port->startup) 2373 return port->startup(port); 2374 return serial8250_do_startup(port); 2375 } 2376 2377 void serial8250_do_shutdown(struct uart_port *port) 2378 { 2379 struct uart_8250_port *up = up_to_u8250p(port); 2380 unsigned long flags; 2381 2382 serial8250_rpm_get(up); 2383 /* 2384 * Disable interrupts from this port 2385 */ 2386 up->ier = 0; 2387 serial_port_out(port, UART_IER, 0); 2388 2389 if (up->dma) 2390 serial8250_release_dma(up); 2391 2392 spin_lock_irqsave(&port->lock, flags); 2393 if (port->flags & UPF_FOURPORT) { 2394 /* reset interrupts on the AST Fourport board */ 2395 inb((port->iobase & 0xfe0) | 0x1f); 2396 port->mctrl |= TIOCM_OUT1; 2397 } else 2398 port->mctrl &= ~TIOCM_OUT2; 2399 2400 serial8250_set_mctrl(port, port->mctrl); 2401 spin_unlock_irqrestore(&port->lock, flags); 2402 2403 /* 2404 * Disable break condition and FIFOs 2405 */ 2406 serial_port_out(port, UART_LCR, 2407 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC); 2408 serial8250_clear_fifos(up); 2409 2410 #ifdef CONFIG_SERIAL_8250_RSA 2411 /* 2412 * Reset the RSA board back to 115kbps compat mode. 2413 */ 2414 disable_rsa(up); 2415 #endif 2416 2417 /* 2418 * Read data port to reset things, and then unlink from 2419 * the IRQ chain. 2420 */ 2421 serial_port_in(port, UART_RX); 2422 serial8250_rpm_put(up); 2423 2424 up->ops->release_irq(up); 2425 } 2426 EXPORT_SYMBOL_GPL(serial8250_do_shutdown); 2427 2428 static void serial8250_shutdown(struct uart_port *port) 2429 { 2430 if (port->shutdown) 2431 port->shutdown(port); 2432 else 2433 serial8250_do_shutdown(port); 2434 } 2435 2436 /* 2437 * XR17V35x UARTs have an extra fractional divisor register (DLD) 2438 * Calculate divisor with extra 4-bit fractional portion 2439 */ 2440 static unsigned int xr17v35x_get_divisor(struct uart_8250_port *up, 2441 unsigned int baud, 2442 unsigned int *frac) 2443 { 2444 struct uart_port *port = &up->port; 2445 unsigned int quot_16; 2446 2447 quot_16 = DIV_ROUND_CLOSEST(port->uartclk, baud); 2448 *frac = quot_16 & 0x0f; 2449 2450 return quot_16 >> 4; 2451 } 2452 2453 static unsigned int serial8250_get_divisor(struct uart_8250_port *up, 2454 unsigned int baud, 2455 unsigned int *frac) 2456 { 2457 struct uart_port *port = &up->port; 2458 unsigned int quot; 2459 2460 /* 2461 * Handle magic divisors for baud rates above baud_base on 2462 * SMSC SuperIO chips. 2463 * 2464 */ 2465 if ((port->flags & UPF_MAGIC_MULTIPLIER) && 2466 baud == (port->uartclk/4)) 2467 quot = 0x8001; 2468 else if ((port->flags & UPF_MAGIC_MULTIPLIER) && 2469 baud == (port->uartclk/8)) 2470 quot = 0x8002; 2471 else if (up->port.type == PORT_XR17V35X) 2472 quot = xr17v35x_get_divisor(up, baud, frac); 2473 else 2474 quot = uart_get_divisor(port, baud); 2475 2476 /* 2477 * Oxford Semi 952 rev B workaround 2478 */ 2479 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0) 2480 quot++; 2481 2482 return quot; 2483 } 2484 2485 static unsigned char serial8250_compute_lcr(struct uart_8250_port *up, 2486 tcflag_t c_cflag) 2487 { 2488 unsigned char cval; 2489 2490 switch (c_cflag & CSIZE) { 2491 case CS5: 2492 cval = UART_LCR_WLEN5; 2493 break; 2494 case CS6: 2495 cval = UART_LCR_WLEN6; 2496 break; 2497 case CS7: 2498 cval = UART_LCR_WLEN7; 2499 break; 2500 default: 2501 case CS8: 2502 cval = UART_LCR_WLEN8; 2503 break; 2504 } 2505 2506 if (c_cflag & CSTOPB) 2507 cval |= UART_LCR_STOP; 2508 if (c_cflag & PARENB) { 2509 cval |= UART_LCR_PARITY; 2510 if (up->bugs & UART_BUG_PARITY) 2511 up->fifo_bug = true; 2512 } 2513 if (!(c_cflag & PARODD)) 2514 cval |= UART_LCR_EPAR; 2515 #ifdef CMSPAR 2516 if (c_cflag & CMSPAR) 2517 cval |= UART_LCR_SPAR; 2518 #endif 2519 2520 return cval; 2521 } 2522 2523 static void serial8250_set_divisor(struct uart_port *port, unsigned int baud, 2524 unsigned int quot, unsigned int quot_frac) 2525 { 2526 struct uart_8250_port *up = up_to_u8250p(port); 2527 2528 /* Workaround to enable 115200 baud on OMAP1510 internal ports */ 2529 if (is_omap1510_8250(up)) { 2530 if (baud == 115200) { 2531 quot = 1; 2532 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1); 2533 } else 2534 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0); 2535 } 2536 2537 /* 2538 * For NatSemi, switch to bank 2 not bank 1, to avoid resetting EXCR2, 2539 * otherwise just set DLAB 2540 */ 2541 if (up->capabilities & UART_NATSEMI) 2542 serial_port_out(port, UART_LCR, 0xe0); 2543 else 2544 serial_port_out(port, UART_LCR, up->lcr | UART_LCR_DLAB); 2545 2546 serial_dl_write(up, quot); 2547 2548 /* XR17V35x UARTs have an extra fractional divisor register (DLD) */ 2549 if (up->port.type == PORT_XR17V35X) 2550 serial_port_out(port, 0x2, quot_frac); 2551 } 2552 2553 void 2554 serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios, 2555 struct ktermios *old) 2556 { 2557 struct uart_8250_port *up = up_to_u8250p(port); 2558 unsigned char cval; 2559 unsigned long flags; 2560 unsigned int baud, quot, frac = 0; 2561 2562 cval = serial8250_compute_lcr(up, termios->c_cflag); 2563 2564 /* 2565 * Ask the core to calculate the divisor for us. 2566 */ 2567 baud = uart_get_baud_rate(port, termios, old, 2568 port->uartclk / 16 / 0xffff, 2569 port->uartclk / 16); 2570 quot = serial8250_get_divisor(up, baud, &frac); 2571 2572 /* 2573 * Ok, we're now changing the port state. Do it with 2574 * interrupts disabled. 2575 */ 2576 serial8250_rpm_get(up); 2577 spin_lock_irqsave(&port->lock, flags); 2578 2579 up->lcr = cval; /* Save computed LCR */ 2580 2581 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) { 2582 /* NOTE: If fifo_bug is not set, a user can set RX_trigger. */ 2583 if ((baud < 2400 && !up->dma) || up->fifo_bug) { 2584 up->fcr &= ~UART_FCR_TRIGGER_MASK; 2585 up->fcr |= UART_FCR_TRIGGER_1; 2586 } 2587 } 2588 2589 /* 2590 * MCR-based auto flow control. When AFE is enabled, RTS will be 2591 * deasserted when the receive FIFO contains more characters than 2592 * the trigger, or the MCR RTS bit is cleared. In the case where 2593 * the remote UART is not using CTS auto flow control, we must 2594 * have sufficient FIFO entries for the latency of the remote 2595 * UART to respond. IOW, at least 32 bytes of FIFO. 2596 */ 2597 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) { 2598 up->mcr &= ~UART_MCR_AFE; 2599 if (termios->c_cflag & CRTSCTS) 2600 up->mcr |= UART_MCR_AFE; 2601 } 2602 2603 /* 2604 * Update the per-port timeout. 2605 */ 2606 uart_update_timeout(port, termios->c_cflag, baud); 2607 2608 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 2609 if (termios->c_iflag & INPCK) 2610 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 2611 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK)) 2612 port->read_status_mask |= UART_LSR_BI; 2613 2614 /* 2615 * Characteres to ignore 2616 */ 2617 port->ignore_status_mask = 0; 2618 if (termios->c_iflag & IGNPAR) 2619 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE; 2620 if (termios->c_iflag & IGNBRK) { 2621 port->ignore_status_mask |= UART_LSR_BI; 2622 /* 2623 * If we're ignoring parity and break indicators, 2624 * ignore overruns too (for real raw support). 2625 */ 2626 if (termios->c_iflag & IGNPAR) 2627 port->ignore_status_mask |= UART_LSR_OE; 2628 } 2629 2630 /* 2631 * ignore all characters if CREAD is not set 2632 */ 2633 if ((termios->c_cflag & CREAD) == 0) 2634 port->ignore_status_mask |= UART_LSR_DR; 2635 2636 /* 2637 * CTS flow control flag and modem status interrupts 2638 */ 2639 up->ier &= ~UART_IER_MSI; 2640 if (!(up->bugs & UART_BUG_NOMSR) && 2641 UART_ENABLE_MS(&up->port, termios->c_cflag)) 2642 up->ier |= UART_IER_MSI; 2643 if (up->capabilities & UART_CAP_UUE) 2644 up->ier |= UART_IER_UUE; 2645 if (up->capabilities & UART_CAP_RTOIE) 2646 up->ier |= UART_IER_RTOIE; 2647 2648 serial_port_out(port, UART_IER, up->ier); 2649 2650 if (up->capabilities & UART_CAP_EFR) { 2651 unsigned char efr = 0; 2652 /* 2653 * TI16C752/Startech hardware flow control. FIXME: 2654 * - TI16C752 requires control thresholds to be set. 2655 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled. 2656 */ 2657 if (termios->c_cflag & CRTSCTS) 2658 efr |= UART_EFR_CTS; 2659 2660 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B); 2661 if (port->flags & UPF_EXAR_EFR) 2662 serial_port_out(port, UART_XR_EFR, efr); 2663 else 2664 serial_port_out(port, UART_EFR, efr); 2665 } 2666 2667 serial8250_set_divisor(port, baud, quot, frac); 2668 2669 /* 2670 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR 2671 * is written without DLAB set, this mode will be disabled. 2672 */ 2673 if (port->type == PORT_16750) 2674 serial_port_out(port, UART_FCR, up->fcr); 2675 2676 serial_port_out(port, UART_LCR, up->lcr); /* reset DLAB */ 2677 if (port->type != PORT_16750) { 2678 /* emulated UARTs (Lucent Venus 167x) need two steps */ 2679 if (up->fcr & UART_FCR_ENABLE_FIFO) 2680 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO); 2681 serial_port_out(port, UART_FCR, up->fcr); /* set fcr */ 2682 } 2683 serial8250_set_mctrl(port, port->mctrl); 2684 spin_unlock_irqrestore(&port->lock, flags); 2685 serial8250_rpm_put(up); 2686 2687 /* Don't rewrite B0 */ 2688 if (tty_termios_baud_rate(termios)) 2689 tty_termios_encode_baud_rate(termios, baud, baud); 2690 } 2691 EXPORT_SYMBOL(serial8250_do_set_termios); 2692 2693 static void 2694 serial8250_set_termios(struct uart_port *port, struct ktermios *termios, 2695 struct ktermios *old) 2696 { 2697 if (port->set_termios) 2698 port->set_termios(port, termios, old); 2699 else 2700 serial8250_do_set_termios(port, termios, old); 2701 } 2702 2703 static void 2704 serial8250_set_ldisc(struct uart_port *port, struct ktermios *termios) 2705 { 2706 if (termios->c_line == N_PPS) { 2707 port->flags |= UPF_HARDPPS_CD; 2708 spin_lock_irq(&port->lock); 2709 serial8250_enable_ms(port); 2710 spin_unlock_irq(&port->lock); 2711 } else { 2712 port->flags &= ~UPF_HARDPPS_CD; 2713 if (!UART_ENABLE_MS(port, termios->c_cflag)) { 2714 spin_lock_irq(&port->lock); 2715 serial8250_disable_ms(port); 2716 spin_unlock_irq(&port->lock); 2717 } 2718 } 2719 } 2720 2721 2722 void serial8250_do_pm(struct uart_port *port, unsigned int state, 2723 unsigned int oldstate) 2724 { 2725 struct uart_8250_port *p = up_to_u8250p(port); 2726 2727 serial8250_set_sleep(p, state != 0); 2728 } 2729 EXPORT_SYMBOL(serial8250_do_pm); 2730 2731 static void 2732 serial8250_pm(struct uart_port *port, unsigned int state, 2733 unsigned int oldstate) 2734 { 2735 if (port->pm) 2736 port->pm(port, state, oldstate); 2737 else 2738 serial8250_do_pm(port, state, oldstate); 2739 } 2740 2741 static unsigned int serial8250_port_size(struct uart_8250_port *pt) 2742 { 2743 if (pt->port.mapsize) 2744 return pt->port.mapsize; 2745 if (pt->port.iotype == UPIO_AU) { 2746 if (pt->port.type == PORT_RT2880) 2747 return 0x100; 2748 return 0x1000; 2749 } 2750 if (is_omap1_8250(pt)) 2751 return 0x16 << pt->port.regshift; 2752 2753 return 8 << pt->port.regshift; 2754 } 2755 2756 /* 2757 * Resource handling. 2758 */ 2759 static int serial8250_request_std_resource(struct uart_8250_port *up) 2760 { 2761 unsigned int size = serial8250_port_size(up); 2762 struct uart_port *port = &up->port; 2763 int ret = 0; 2764 2765 switch (port->iotype) { 2766 case UPIO_AU: 2767 case UPIO_TSI: 2768 case UPIO_MEM32: 2769 case UPIO_MEM32BE: 2770 case UPIO_MEM: 2771 if (!port->mapbase) 2772 break; 2773 2774 if (!request_mem_region(port->mapbase, size, "serial")) { 2775 ret = -EBUSY; 2776 break; 2777 } 2778 2779 if (port->flags & UPF_IOREMAP) { 2780 port->membase = ioremap_nocache(port->mapbase, size); 2781 if (!port->membase) { 2782 release_mem_region(port->mapbase, size); 2783 ret = -ENOMEM; 2784 } 2785 } 2786 break; 2787 2788 case UPIO_HUB6: 2789 case UPIO_PORT: 2790 if (!request_region(port->iobase, size, "serial")) 2791 ret = -EBUSY; 2792 break; 2793 } 2794 return ret; 2795 } 2796 2797 static void serial8250_release_std_resource(struct uart_8250_port *up) 2798 { 2799 unsigned int size = serial8250_port_size(up); 2800 struct uart_port *port = &up->port; 2801 2802 switch (port->iotype) { 2803 case UPIO_AU: 2804 case UPIO_TSI: 2805 case UPIO_MEM32: 2806 case UPIO_MEM32BE: 2807 case UPIO_MEM: 2808 if (!port->mapbase) 2809 break; 2810 2811 if (port->flags & UPF_IOREMAP) { 2812 iounmap(port->membase); 2813 port->membase = NULL; 2814 } 2815 2816 release_mem_region(port->mapbase, size); 2817 break; 2818 2819 case UPIO_HUB6: 2820 case UPIO_PORT: 2821 release_region(port->iobase, size); 2822 break; 2823 } 2824 } 2825 2826 #ifdef CONFIG_SERIAL_8250_RSA 2827 static int serial8250_request_rsa_resource(struct uart_8250_port *up) 2828 { 2829 unsigned long start = UART_RSA_BASE << up->port.regshift; 2830 unsigned int size = 8 << up->port.regshift; 2831 struct uart_port *port = &up->port; 2832 int ret = -EINVAL; 2833 2834 switch (port->iotype) { 2835 case UPIO_HUB6: 2836 case UPIO_PORT: 2837 start += port->iobase; 2838 if (request_region(start, size, "serial-rsa")) 2839 ret = 0; 2840 else 2841 ret = -EBUSY; 2842 break; 2843 } 2844 2845 return ret; 2846 } 2847 2848 static void serial8250_release_rsa_resource(struct uart_8250_port *up) 2849 { 2850 unsigned long offset = UART_RSA_BASE << up->port.regshift; 2851 unsigned int size = 8 << up->port.regshift; 2852 struct uart_port *port = &up->port; 2853 2854 switch (port->iotype) { 2855 case UPIO_HUB6: 2856 case UPIO_PORT: 2857 release_region(port->iobase + offset, size); 2858 break; 2859 } 2860 } 2861 #endif 2862 2863 static void serial8250_release_port(struct uart_port *port) 2864 { 2865 struct uart_8250_port *up = up_to_u8250p(port); 2866 2867 serial8250_release_std_resource(up); 2868 } 2869 2870 static int serial8250_request_port(struct uart_port *port) 2871 { 2872 struct uart_8250_port *up = up_to_u8250p(port); 2873 int ret; 2874 2875 if (port->type == PORT_8250_CIR) 2876 return -ENODEV; 2877 2878 ret = serial8250_request_std_resource(up); 2879 2880 return ret; 2881 } 2882 2883 static int fcr_get_rxtrig_bytes(struct uart_8250_port *up) 2884 { 2885 const struct serial8250_config *conf_type = &uart_config[up->port.type]; 2886 unsigned char bytes; 2887 2888 bytes = conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(up->fcr)]; 2889 2890 return bytes ? bytes : -EOPNOTSUPP; 2891 } 2892 2893 static int bytes_to_fcr_rxtrig(struct uart_8250_port *up, unsigned char bytes) 2894 { 2895 const struct serial8250_config *conf_type = &uart_config[up->port.type]; 2896 int i; 2897 2898 if (!conf_type->rxtrig_bytes[UART_FCR_R_TRIG_BITS(UART_FCR_R_TRIG_00)]) 2899 return -EOPNOTSUPP; 2900 2901 for (i = 1; i < UART_FCR_R_TRIG_MAX_STATE; i++) { 2902 if (bytes < conf_type->rxtrig_bytes[i]) 2903 /* Use the nearest lower value */ 2904 return (--i) << UART_FCR_R_TRIG_SHIFT; 2905 } 2906 2907 return UART_FCR_R_TRIG_11; 2908 } 2909 2910 static int do_get_rxtrig(struct tty_port *port) 2911 { 2912 struct uart_state *state = container_of(port, struct uart_state, port); 2913 struct uart_port *uport = state->uart_port; 2914 struct uart_8250_port *up = 2915 container_of(uport, struct uart_8250_port, port); 2916 2917 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1) 2918 return -EINVAL; 2919 2920 return fcr_get_rxtrig_bytes(up); 2921 } 2922 2923 static int do_serial8250_get_rxtrig(struct tty_port *port) 2924 { 2925 int rxtrig_bytes; 2926 2927 mutex_lock(&port->mutex); 2928 rxtrig_bytes = do_get_rxtrig(port); 2929 mutex_unlock(&port->mutex); 2930 2931 return rxtrig_bytes; 2932 } 2933 2934 static ssize_t serial8250_get_attr_rx_trig_bytes(struct device *dev, 2935 struct device_attribute *attr, char *buf) 2936 { 2937 struct tty_port *port = dev_get_drvdata(dev); 2938 int rxtrig_bytes; 2939 2940 rxtrig_bytes = do_serial8250_get_rxtrig(port); 2941 if (rxtrig_bytes < 0) 2942 return rxtrig_bytes; 2943 2944 return snprintf(buf, PAGE_SIZE, "%d\n", rxtrig_bytes); 2945 } 2946 2947 static int do_set_rxtrig(struct tty_port *port, unsigned char bytes) 2948 { 2949 struct uart_state *state = container_of(port, struct uart_state, port); 2950 struct uart_port *uport = state->uart_port; 2951 struct uart_8250_port *up = 2952 container_of(uport, struct uart_8250_port, port); 2953 int rxtrig; 2954 2955 if (!(up->capabilities & UART_CAP_FIFO) || uport->fifosize <= 1 || 2956 up->fifo_bug) 2957 return -EINVAL; 2958 2959 rxtrig = bytes_to_fcr_rxtrig(up, bytes); 2960 if (rxtrig < 0) 2961 return rxtrig; 2962 2963 serial8250_clear_fifos(up); 2964 up->fcr &= ~UART_FCR_TRIGGER_MASK; 2965 up->fcr |= (unsigned char)rxtrig; 2966 serial_out(up, UART_FCR, up->fcr); 2967 return 0; 2968 } 2969 2970 static int do_serial8250_set_rxtrig(struct tty_port *port, unsigned char bytes) 2971 { 2972 int ret; 2973 2974 mutex_lock(&port->mutex); 2975 ret = do_set_rxtrig(port, bytes); 2976 mutex_unlock(&port->mutex); 2977 2978 return ret; 2979 } 2980 2981 static ssize_t serial8250_set_attr_rx_trig_bytes(struct device *dev, 2982 struct device_attribute *attr, const char *buf, size_t count) 2983 { 2984 struct tty_port *port = dev_get_drvdata(dev); 2985 unsigned char bytes; 2986 int ret; 2987 2988 if (!count) 2989 return -EINVAL; 2990 2991 ret = kstrtou8(buf, 10, &bytes); 2992 if (ret < 0) 2993 return ret; 2994 2995 ret = do_serial8250_set_rxtrig(port, bytes); 2996 if (ret < 0) 2997 return ret; 2998 2999 return count; 3000 } 3001 3002 static DEVICE_ATTR(rx_trig_bytes, S_IRUSR | S_IWUSR | S_IRGRP, 3003 serial8250_get_attr_rx_trig_bytes, 3004 serial8250_set_attr_rx_trig_bytes); 3005 3006 static struct attribute *serial8250_dev_attrs[] = { 3007 &dev_attr_rx_trig_bytes.attr, 3008 NULL, 3009 }; 3010 3011 static struct attribute_group serial8250_dev_attr_group = { 3012 .attrs = serial8250_dev_attrs, 3013 }; 3014 3015 static void register_dev_spec_attr_grp(struct uart_8250_port *up) 3016 { 3017 const struct serial8250_config *conf_type = &uart_config[up->port.type]; 3018 3019 if (conf_type->rxtrig_bytes[0]) 3020 up->port.attr_group = &serial8250_dev_attr_group; 3021 } 3022 3023 static void serial8250_config_port(struct uart_port *port, int flags) 3024 { 3025 struct uart_8250_port *up = up_to_u8250p(port); 3026 int ret; 3027 3028 if (port->type == PORT_8250_CIR) 3029 return; 3030 3031 /* 3032 * Find the region that we can probe for. This in turn 3033 * tells us whether we can probe for the type of port. 3034 */ 3035 ret = serial8250_request_std_resource(up); 3036 if (ret < 0) 3037 return; 3038 3039 if (port->iotype != up->cur_iotype) 3040 set_io_from_upio(port); 3041 3042 if (flags & UART_CONFIG_TYPE) 3043 autoconfig(up); 3044 3045 /* if access method is AU, it is a 16550 with a quirk */ 3046 if (port->type == PORT_16550A && port->iotype == UPIO_AU) 3047 up->bugs |= UART_BUG_NOMSR; 3048 3049 /* HW bugs may trigger IRQ while IIR == NO_INT */ 3050 if (port->type == PORT_TEGRA) 3051 up->bugs |= UART_BUG_NOMSR; 3052 3053 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ) 3054 autoconfig_irq(up); 3055 3056 if (port->type == PORT_UNKNOWN) 3057 serial8250_release_std_resource(up); 3058 3059 /* Fixme: probably not the best place for this */ 3060 if ((port->type == PORT_XR17V35X) || 3061 (port->type == PORT_XR17D15X)) 3062 port->handle_irq = exar_handle_irq; 3063 3064 register_dev_spec_attr_grp(up); 3065 up->fcr = uart_config[up->port.type].fcr; 3066 } 3067 3068 static int 3069 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser) 3070 { 3071 if (ser->irq >= nr_irqs || ser->irq < 0 || 3072 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN || 3073 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS || 3074 ser->type == PORT_STARTECH) 3075 return -EINVAL; 3076 return 0; 3077 } 3078 3079 static const char * 3080 serial8250_type(struct uart_port *port) 3081 { 3082 int type = port->type; 3083 3084 if (type >= ARRAY_SIZE(uart_config)) 3085 type = 0; 3086 return uart_config[type].name; 3087 } 3088 3089 static const struct uart_ops serial8250_pops = { 3090 .tx_empty = serial8250_tx_empty, 3091 .set_mctrl = serial8250_set_mctrl, 3092 .get_mctrl = serial8250_get_mctrl, 3093 .stop_tx = serial8250_stop_tx, 3094 .start_tx = serial8250_start_tx, 3095 .throttle = serial8250_throttle, 3096 .unthrottle = serial8250_unthrottle, 3097 .stop_rx = serial8250_stop_rx, 3098 .enable_ms = serial8250_enable_ms, 3099 .break_ctl = serial8250_break_ctl, 3100 .startup = serial8250_startup, 3101 .shutdown = serial8250_shutdown, 3102 .set_termios = serial8250_set_termios, 3103 .set_ldisc = serial8250_set_ldisc, 3104 .pm = serial8250_pm, 3105 .type = serial8250_type, 3106 .release_port = serial8250_release_port, 3107 .request_port = serial8250_request_port, 3108 .config_port = serial8250_config_port, 3109 .verify_port = serial8250_verify_port, 3110 #ifdef CONFIG_CONSOLE_POLL 3111 .poll_get_char = serial8250_get_poll_char, 3112 .poll_put_char = serial8250_put_poll_char, 3113 #endif 3114 }; 3115 3116 static const struct uart_ops *base_ops; 3117 static struct uart_ops univ8250_port_ops; 3118 3119 static const struct uart_8250_ops univ8250_driver_ops = { 3120 .setup_irq = univ8250_setup_irq, 3121 .release_irq = univ8250_release_irq, 3122 }; 3123 3124 static struct uart_8250_port serial8250_ports[UART_NR]; 3125 3126 /** 3127 * serial8250_get_port - retrieve struct uart_8250_port 3128 * @line: serial line number 3129 * 3130 * This function retrieves struct uart_8250_port for the specific line. 3131 * This struct *must* *not* be used to perform a 8250 or serial core operation 3132 * which is not accessible otherwise. Its only purpose is to make the struct 3133 * accessible to the runtime-pm callbacks for context suspend/restore. 3134 * The lock assumption made here is none because runtime-pm suspend/resume 3135 * callbacks should not be invoked if there is any operation performed on the 3136 * port. 3137 */ 3138 struct uart_8250_port *serial8250_get_port(int line) 3139 { 3140 return &serial8250_ports[line]; 3141 } 3142 EXPORT_SYMBOL_GPL(serial8250_get_port); 3143 3144 static void (*serial8250_isa_config)(int port, struct uart_port *up, 3145 unsigned short *capabilities); 3146 3147 void serial8250_set_isa_configurator( 3148 void (*v)(int port, struct uart_port *up, unsigned short *capabilities)) 3149 { 3150 serial8250_isa_config = v; 3151 } 3152 EXPORT_SYMBOL(serial8250_set_isa_configurator); 3153 3154 static void serial8250_init_port(struct uart_8250_port *up) 3155 { 3156 struct uart_port *port = &up->port; 3157 3158 spin_lock_init(&port->lock); 3159 port->ops = &serial8250_pops; 3160 3161 up->cur_iotype = 0xFF; 3162 } 3163 3164 static void serial8250_set_defaults(struct uart_8250_port *up) 3165 { 3166 struct uart_port *port = &up->port; 3167 3168 if (up->port.flags & UPF_FIXED_TYPE) { 3169 unsigned int type = up->port.type; 3170 3171 if (!up->port.fifosize) 3172 up->port.fifosize = uart_config[type].fifo_size; 3173 if (!up->tx_loadsz) 3174 up->tx_loadsz = uart_config[type].tx_loadsz; 3175 if (!up->capabilities) 3176 up->capabilities = uart_config[type].flags; 3177 } 3178 3179 set_io_from_upio(port); 3180 3181 /* default dma handlers */ 3182 if (up->dma) { 3183 if (!up->dma->tx_dma) 3184 up->dma->tx_dma = serial8250_tx_dma; 3185 if (!up->dma->rx_dma) 3186 up->dma->rx_dma = serial8250_rx_dma; 3187 } 3188 } 3189 3190 #ifdef CONFIG_SERIAL_8250_RSA 3191 3192 static void univ8250_config_port(struct uart_port *port, int flags) 3193 { 3194 struct uart_8250_port *up = up_to_u8250p(port); 3195 3196 up->probe &= ~UART_PROBE_RSA; 3197 if (port->type == PORT_RSA) { 3198 if (serial8250_request_rsa_resource(up) == 0) 3199 up->probe |= UART_PROBE_RSA; 3200 } else if (flags & UART_CONFIG_TYPE) { 3201 int i; 3202 3203 for (i = 0; i < probe_rsa_count; i++) { 3204 if (probe_rsa[i] == up->port.iobase) { 3205 if (serial8250_request_rsa_resource(up) == 0) 3206 up->probe |= UART_PROBE_RSA; 3207 break; 3208 } 3209 } 3210 } 3211 3212 base_ops->config_port(port, flags); 3213 3214 if (port->type != PORT_RSA && up->probe & UART_PROBE_RSA) 3215 serial8250_release_rsa_resource(up); 3216 } 3217 3218 static int univ8250_request_port(struct uart_port *port) 3219 { 3220 struct uart_8250_port *up = up_to_u8250p(port); 3221 int ret; 3222 3223 ret = base_ops->request_port(port); 3224 if (ret == 0 && port->type == PORT_RSA) { 3225 ret = serial8250_request_rsa_resource(up); 3226 if (ret < 0) 3227 base_ops->release_port(port); 3228 } 3229 3230 return ret; 3231 } 3232 3233 static void univ8250_release_port(struct uart_port *port) 3234 { 3235 struct uart_8250_port *up = up_to_u8250p(port); 3236 3237 if (port->type == PORT_RSA) 3238 serial8250_release_rsa_resource(up); 3239 base_ops->release_port(port); 3240 } 3241 3242 static void univ8250_rsa_support(struct uart_ops *ops) 3243 { 3244 ops->config_port = univ8250_config_port; 3245 ops->request_port = univ8250_request_port; 3246 ops->release_port = univ8250_release_port; 3247 } 3248 3249 #else 3250 #define univ8250_rsa_support(x) do { } while (0) 3251 #endif /* CONFIG_SERIAL_8250_RSA */ 3252 3253 static void __init serial8250_isa_init_ports(void) 3254 { 3255 struct uart_8250_port *up; 3256 static int first = 1; 3257 int i, irqflag = 0; 3258 3259 if (!first) 3260 return; 3261 first = 0; 3262 3263 if (nr_uarts > UART_NR) 3264 nr_uarts = UART_NR; 3265 3266 for (i = 0; i < nr_uarts; i++) { 3267 struct uart_8250_port *up = &serial8250_ports[i]; 3268 struct uart_port *port = &up->port; 3269 3270 port->line = i; 3271 serial8250_init_port(up); 3272 if (!base_ops) 3273 base_ops = port->ops; 3274 port->ops = &univ8250_port_ops; 3275 3276 init_timer(&up->timer); 3277 up->timer.function = serial8250_timeout; 3278 3279 up->ops = &univ8250_driver_ops; 3280 3281 /* 3282 * ALPHA_KLUDGE_MCR needs to be killed. 3283 */ 3284 up->mcr_mask = ~ALPHA_KLUDGE_MCR; 3285 up->mcr_force = ALPHA_KLUDGE_MCR; 3286 } 3287 3288 /* chain base port ops to support Remote Supervisor Adapter */ 3289 univ8250_port_ops = *base_ops; 3290 univ8250_rsa_support(&univ8250_port_ops); 3291 3292 if (share_irqs) 3293 irqflag = IRQF_SHARED; 3294 3295 for (i = 0, up = serial8250_ports; 3296 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts; 3297 i++, up++) { 3298 struct uart_port *port = &up->port; 3299 3300 port->iobase = old_serial_port[i].port; 3301 port->irq = irq_canonicalize(old_serial_port[i].irq); 3302 port->irqflags = old_serial_port[i].irqflags; 3303 port->uartclk = old_serial_port[i].baud_base * 16; 3304 port->flags = old_serial_port[i].flags; 3305 port->hub6 = old_serial_port[i].hub6; 3306 port->membase = old_serial_port[i].iomem_base; 3307 port->iotype = old_serial_port[i].io_type; 3308 port->regshift = old_serial_port[i].iomem_reg_shift; 3309 serial8250_set_defaults(up); 3310 3311 port->irqflags |= irqflag; 3312 if (serial8250_isa_config != NULL) 3313 serial8250_isa_config(i, &up->port, &up->capabilities); 3314 } 3315 } 3316 3317 static void __init 3318 serial8250_register_ports(struct uart_driver *drv, struct device *dev) 3319 { 3320 int i; 3321 3322 for (i = 0; i < nr_uarts; i++) { 3323 struct uart_8250_port *up = &serial8250_ports[i]; 3324 3325 if (up->port.dev) 3326 continue; 3327 3328 up->port.dev = dev; 3329 3330 if (skip_txen_test) 3331 up->port.flags |= UPF_NO_TXEN_TEST; 3332 3333 uart_add_one_port(drv, &up->port); 3334 } 3335 } 3336 3337 #ifdef CONFIG_SERIAL_8250_CONSOLE 3338 3339 static void serial8250_console_putchar(struct uart_port *port, int ch) 3340 { 3341 struct uart_8250_port *up = up_to_u8250p(port); 3342 3343 wait_for_xmitr(up, UART_LSR_THRE); 3344 serial_port_out(port, UART_TX, ch); 3345 } 3346 3347 /* 3348 * Print a string to the serial port trying not to disturb 3349 * any possible real use of the port... 3350 * 3351 * The console_lock must be held when we get here. 3352 */ 3353 static void serial8250_console_write(struct uart_8250_port *up, const char *s, 3354 unsigned int count) 3355 { 3356 struct uart_port *port = &up->port; 3357 unsigned long flags; 3358 unsigned int ier; 3359 int locked = 1; 3360 3361 touch_nmi_watchdog(); 3362 3363 serial8250_rpm_get(up); 3364 3365 if (port->sysrq) 3366 locked = 0; 3367 else if (oops_in_progress) 3368 locked = spin_trylock_irqsave(&port->lock, flags); 3369 else 3370 spin_lock_irqsave(&port->lock, flags); 3371 3372 /* 3373 * First save the IER then disable the interrupts 3374 */ 3375 ier = serial_port_in(port, UART_IER); 3376 3377 if (up->capabilities & UART_CAP_UUE) 3378 serial_port_out(port, UART_IER, UART_IER_UUE); 3379 else 3380 serial_port_out(port, UART_IER, 0); 3381 3382 /* check scratch reg to see if port powered off during system sleep */ 3383 if (up->canary && (up->canary != serial_port_in(port, UART_SCR))) { 3384 struct ktermios termios; 3385 unsigned int baud, quot, frac = 0; 3386 3387 termios.c_cflag = port->cons->cflag; 3388 if (port->state->port.tty && termios.c_cflag == 0) 3389 termios.c_cflag = port->state->port.tty->termios.c_cflag; 3390 3391 baud = uart_get_baud_rate(port, &termios, NULL, 3392 port->uartclk / 16 / 0xffff, 3393 port->uartclk / 16); 3394 quot = serial8250_get_divisor(up, baud, &frac); 3395 3396 serial8250_set_divisor(port, baud, quot, frac); 3397 serial_port_out(port, UART_LCR, up->lcr); 3398 serial_port_out(port, UART_MCR, UART_MCR_DTR | UART_MCR_RTS); 3399 3400 up->canary = 0; 3401 } 3402 3403 uart_console_write(port, s, count, serial8250_console_putchar); 3404 3405 /* 3406 * Finally, wait for transmitter to become empty 3407 * and restore the IER 3408 */ 3409 wait_for_xmitr(up, BOTH_EMPTY); 3410 serial_port_out(port, UART_IER, ier); 3411 3412 /* 3413 * The receive handling will happen properly because the 3414 * receive ready bit will still be set; it is not cleared 3415 * on read. However, modem control will not, we must 3416 * call it if we have saved something in the saved flags 3417 * while processing with interrupts off. 3418 */ 3419 if (up->msr_saved_flags) 3420 serial8250_modem_status(up); 3421 3422 if (locked) 3423 spin_unlock_irqrestore(&port->lock, flags); 3424 serial8250_rpm_put(up); 3425 } 3426 3427 static void univ8250_console_write(struct console *co, const char *s, 3428 unsigned int count) 3429 { 3430 struct uart_8250_port *up = &serial8250_ports[co->index]; 3431 3432 serial8250_console_write(up, s, count); 3433 } 3434 3435 static unsigned int probe_baud(struct uart_port *port) 3436 { 3437 unsigned char lcr, dll, dlm; 3438 unsigned int quot; 3439 3440 lcr = serial_port_in(port, UART_LCR); 3441 serial_port_out(port, UART_LCR, lcr | UART_LCR_DLAB); 3442 dll = serial_port_in(port, UART_DLL); 3443 dlm = serial_port_in(port, UART_DLM); 3444 serial_port_out(port, UART_LCR, lcr); 3445 3446 quot = (dlm << 8) | dll; 3447 return (port->uartclk / 16) / quot; 3448 } 3449 3450 static int serial8250_console_setup(struct uart_port *port, char *options, bool probe) 3451 { 3452 int baud = 9600; 3453 int bits = 8; 3454 int parity = 'n'; 3455 int flow = 'n'; 3456 3457 if (!port->iobase && !port->membase) 3458 return -ENODEV; 3459 3460 if (options) 3461 uart_parse_options(options, &baud, &parity, &bits, &flow); 3462 else if (probe) 3463 baud = probe_baud(port); 3464 3465 return uart_set_options(port, port->cons, baud, parity, bits, flow); 3466 } 3467 3468 static int univ8250_console_setup(struct console *co, char *options) 3469 { 3470 struct uart_port *port; 3471 3472 /* 3473 * Check whether an invalid uart number has been specified, and 3474 * if so, search for the first available port that does have 3475 * console support. 3476 */ 3477 if (co->index >= nr_uarts) 3478 co->index = 0; 3479 port = &serial8250_ports[co->index].port; 3480 /* link port to console */ 3481 port->cons = co; 3482 3483 return serial8250_console_setup(port, options, false); 3484 } 3485 3486 /** 3487 * univ8250_console_match - non-standard console matching 3488 * @co: registering console 3489 * @name: name from console command line 3490 * @idx: index from console command line 3491 * @options: ptr to option string from console command line 3492 * 3493 * Only attempts to match console command lines of the form: 3494 * console=uart[8250],io|mmio|mmio32,<addr>[,<options>] 3495 * console=uart[8250],0x<addr>[,<options>] 3496 * This form is used to register an initial earlycon boot console and 3497 * replace it with the serial8250_console at 8250 driver init. 3498 * 3499 * Performs console setup for a match (as required by interface) 3500 * If no <options> are specified, then assume the h/w is already setup. 3501 * 3502 * Returns 0 if console matches; otherwise non-zero to use default matching 3503 */ 3504 static int univ8250_console_match(struct console *co, char *name, int idx, 3505 char *options) 3506 { 3507 char match[] = "uart"; /* 8250-specific earlycon name */ 3508 unsigned char iotype; 3509 unsigned long addr; 3510 int i; 3511 3512 if (strncmp(name, match, 4) != 0) 3513 return -ENODEV; 3514 3515 if (uart_parse_earlycon(options, &iotype, &addr, &options)) 3516 return -ENODEV; 3517 3518 /* try to match the port specified on the command line */ 3519 for (i = 0; i < nr_uarts; i++) { 3520 struct uart_port *port = &serial8250_ports[i].port; 3521 3522 if (port->iotype != iotype) 3523 continue; 3524 if ((iotype == UPIO_MEM || iotype == UPIO_MEM32) && 3525 (port->mapbase != addr)) 3526 continue; 3527 if (iotype == UPIO_PORT && port->iobase != addr) 3528 continue; 3529 3530 co->index = i; 3531 port->cons = co; 3532 return serial8250_console_setup(port, options, true); 3533 } 3534 3535 return -ENODEV; 3536 } 3537 3538 static struct console univ8250_console = { 3539 .name = "ttyS", 3540 .write = univ8250_console_write, 3541 .device = uart_console_device, 3542 .setup = univ8250_console_setup, 3543 .match = univ8250_console_match, 3544 .flags = CON_PRINTBUFFER | CON_ANYTIME, 3545 .index = -1, 3546 .data = &serial8250_reg, 3547 }; 3548 3549 static int __init univ8250_console_init(void) 3550 { 3551 serial8250_isa_init_ports(); 3552 register_console(&univ8250_console); 3553 return 0; 3554 } 3555 console_initcall(univ8250_console_init); 3556 3557 #define SERIAL8250_CONSOLE &univ8250_console 3558 #else 3559 #define SERIAL8250_CONSOLE NULL 3560 #endif 3561 3562 static struct uart_driver serial8250_reg = { 3563 .owner = THIS_MODULE, 3564 .driver_name = "serial", 3565 .dev_name = "ttyS", 3566 .major = TTY_MAJOR, 3567 .minor = 64, 3568 .cons = SERIAL8250_CONSOLE, 3569 }; 3570 3571 /* 3572 * early_serial_setup - early registration for 8250 ports 3573 * 3574 * Setup an 8250 port structure prior to console initialisation. Use 3575 * after console initialisation will cause undefined behaviour. 3576 */ 3577 int __init early_serial_setup(struct uart_port *port) 3578 { 3579 struct uart_port *p; 3580 3581 if (port->line >= ARRAY_SIZE(serial8250_ports)) 3582 return -ENODEV; 3583 3584 serial8250_isa_init_ports(); 3585 p = &serial8250_ports[port->line].port; 3586 p->iobase = port->iobase; 3587 p->membase = port->membase; 3588 p->irq = port->irq; 3589 p->irqflags = port->irqflags; 3590 p->uartclk = port->uartclk; 3591 p->fifosize = port->fifosize; 3592 p->regshift = port->regshift; 3593 p->iotype = port->iotype; 3594 p->flags = port->flags; 3595 p->mapbase = port->mapbase; 3596 p->mapsize = port->mapsize; 3597 p->private_data = port->private_data; 3598 p->type = port->type; 3599 p->line = port->line; 3600 3601 serial8250_set_defaults(up_to_u8250p(p)); 3602 3603 if (port->serial_in) 3604 p->serial_in = port->serial_in; 3605 if (port->serial_out) 3606 p->serial_out = port->serial_out; 3607 if (port->handle_irq) 3608 p->handle_irq = port->handle_irq; 3609 3610 return 0; 3611 } 3612 3613 /** 3614 * serial8250_suspend_port - suspend one serial port 3615 * @line: serial line number 3616 * 3617 * Suspend one serial port. 3618 */ 3619 void serial8250_suspend_port(int line) 3620 { 3621 struct uart_8250_port *up = &serial8250_ports[line]; 3622 struct uart_port *port = &up->port; 3623 3624 if (!console_suspend_enabled && uart_console(port) && 3625 port->type != PORT_8250) { 3626 unsigned char canary = 0xa5; 3627 serial_out(up, UART_SCR, canary); 3628 if (serial_in(up, UART_SCR) == canary) 3629 up->canary = canary; 3630 } 3631 3632 uart_suspend_port(&serial8250_reg, port); 3633 } 3634 3635 /** 3636 * serial8250_resume_port - resume one serial port 3637 * @line: serial line number 3638 * 3639 * Resume one serial port. 3640 */ 3641 void serial8250_resume_port(int line) 3642 { 3643 struct uart_8250_port *up = &serial8250_ports[line]; 3644 struct uart_port *port = &up->port; 3645 3646 up->canary = 0; 3647 3648 if (up->capabilities & UART_NATSEMI) { 3649 /* Ensure it's still in high speed mode */ 3650 serial_port_out(port, UART_LCR, 0xE0); 3651 3652 ns16550a_goto_highspeed(up); 3653 3654 serial_port_out(port, UART_LCR, 0); 3655 port->uartclk = 921600*16; 3656 } 3657 uart_resume_port(&serial8250_reg, port); 3658 } 3659 3660 /* 3661 * Register a set of serial devices attached to a platform device. The 3662 * list is terminated with a zero flags entry, which means we expect 3663 * all entries to have at least UPF_BOOT_AUTOCONF set. 3664 */ 3665 static int serial8250_probe(struct platform_device *dev) 3666 { 3667 struct plat_serial8250_port *p = dev_get_platdata(&dev->dev); 3668 struct uart_8250_port uart; 3669 int ret, i, irqflag = 0; 3670 3671 memset(&uart, 0, sizeof(uart)); 3672 3673 if (share_irqs) 3674 irqflag = IRQF_SHARED; 3675 3676 for (i = 0; p && p->flags != 0; p++, i++) { 3677 uart.port.iobase = p->iobase; 3678 uart.port.membase = p->membase; 3679 uart.port.irq = p->irq; 3680 uart.port.irqflags = p->irqflags; 3681 uart.port.uartclk = p->uartclk; 3682 uart.port.regshift = p->regshift; 3683 uart.port.iotype = p->iotype; 3684 uart.port.flags = p->flags; 3685 uart.port.mapbase = p->mapbase; 3686 uart.port.hub6 = p->hub6; 3687 uart.port.private_data = p->private_data; 3688 uart.port.type = p->type; 3689 uart.port.serial_in = p->serial_in; 3690 uart.port.serial_out = p->serial_out; 3691 uart.port.handle_irq = p->handle_irq; 3692 uart.port.handle_break = p->handle_break; 3693 uart.port.set_termios = p->set_termios; 3694 uart.port.pm = p->pm; 3695 uart.port.dev = &dev->dev; 3696 uart.port.irqflags |= irqflag; 3697 ret = serial8250_register_8250_port(&uart); 3698 if (ret < 0) { 3699 dev_err(&dev->dev, "unable to register port at index %d " 3700 "(IO%lx MEM%llx IRQ%d): %d\n", i, 3701 p->iobase, (unsigned long long)p->mapbase, 3702 p->irq, ret); 3703 } 3704 } 3705 return 0; 3706 } 3707 3708 /* 3709 * Remove serial ports registered against a platform device. 3710 */ 3711 static int serial8250_remove(struct platform_device *dev) 3712 { 3713 int i; 3714 3715 for (i = 0; i < nr_uarts; i++) { 3716 struct uart_8250_port *up = &serial8250_ports[i]; 3717 3718 if (up->port.dev == &dev->dev) 3719 serial8250_unregister_port(i); 3720 } 3721 return 0; 3722 } 3723 3724 static int serial8250_suspend(struct platform_device *dev, pm_message_t state) 3725 { 3726 int i; 3727 3728 for (i = 0; i < UART_NR; i++) { 3729 struct uart_8250_port *up = &serial8250_ports[i]; 3730 3731 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) 3732 uart_suspend_port(&serial8250_reg, &up->port); 3733 } 3734 3735 return 0; 3736 } 3737 3738 static int serial8250_resume(struct platform_device *dev) 3739 { 3740 int i; 3741 3742 for (i = 0; i < UART_NR; i++) { 3743 struct uart_8250_port *up = &serial8250_ports[i]; 3744 3745 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev) 3746 serial8250_resume_port(i); 3747 } 3748 3749 return 0; 3750 } 3751 3752 static struct platform_driver serial8250_isa_driver = { 3753 .probe = serial8250_probe, 3754 .remove = serial8250_remove, 3755 .suspend = serial8250_suspend, 3756 .resume = serial8250_resume, 3757 .driver = { 3758 .name = "serial8250", 3759 }, 3760 }; 3761 3762 /* 3763 * This "device" covers _all_ ISA 8250-compatible serial devices listed 3764 * in the table in include/asm/serial.h 3765 */ 3766 static struct platform_device *serial8250_isa_devs; 3767 3768 /* 3769 * serial8250_register_8250_port and serial8250_unregister_port allows for 3770 * 16x50 serial ports to be configured at run-time, to support PCMCIA 3771 * modems and PCI multiport cards. 3772 */ 3773 static DEFINE_MUTEX(serial_mutex); 3774 3775 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port) 3776 { 3777 int i; 3778 3779 /* 3780 * First, find a port entry which matches. 3781 */ 3782 for (i = 0; i < nr_uarts; i++) 3783 if (uart_match_port(&serial8250_ports[i].port, port)) 3784 return &serial8250_ports[i]; 3785 3786 /* try line number first if still available */ 3787 i = port->line; 3788 if (i < nr_uarts && serial8250_ports[i].port.type == PORT_UNKNOWN && 3789 serial8250_ports[i].port.iobase == 0) 3790 return &serial8250_ports[i]; 3791 /* 3792 * We didn't find a matching entry, so look for the first 3793 * free entry. We look for one which hasn't been previously 3794 * used (indicated by zero iobase). 3795 */ 3796 for (i = 0; i < nr_uarts; i++) 3797 if (serial8250_ports[i].port.type == PORT_UNKNOWN && 3798 serial8250_ports[i].port.iobase == 0) 3799 return &serial8250_ports[i]; 3800 3801 /* 3802 * That also failed. Last resort is to find any entry which 3803 * doesn't have a real port associated with it. 3804 */ 3805 for (i = 0; i < nr_uarts; i++) 3806 if (serial8250_ports[i].port.type == PORT_UNKNOWN) 3807 return &serial8250_ports[i]; 3808 3809 return NULL; 3810 } 3811 3812 /** 3813 * serial8250_register_8250_port - register a serial port 3814 * @up: serial port template 3815 * 3816 * Configure the serial port specified by the request. If the 3817 * port exists and is in use, it is hung up and unregistered 3818 * first. 3819 * 3820 * The port is then probed and if necessary the IRQ is autodetected 3821 * If this fails an error is returned. 3822 * 3823 * On success the port is ready to use and the line number is returned. 3824 */ 3825 int serial8250_register_8250_port(struct uart_8250_port *up) 3826 { 3827 struct uart_8250_port *uart; 3828 int ret = -ENOSPC; 3829 3830 if (up->port.uartclk == 0) 3831 return -EINVAL; 3832 3833 mutex_lock(&serial_mutex); 3834 3835 uart = serial8250_find_match_or_unused(&up->port); 3836 if (uart && uart->port.type != PORT_8250_CIR) { 3837 if (uart->port.dev) 3838 uart_remove_one_port(&serial8250_reg, &uart->port); 3839 3840 uart->port.iobase = up->port.iobase; 3841 uart->port.membase = up->port.membase; 3842 uart->port.irq = up->port.irq; 3843 uart->port.irqflags = up->port.irqflags; 3844 uart->port.uartclk = up->port.uartclk; 3845 uart->port.fifosize = up->port.fifosize; 3846 uart->port.regshift = up->port.regshift; 3847 uart->port.iotype = up->port.iotype; 3848 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF; 3849 uart->bugs = up->bugs; 3850 uart->port.mapbase = up->port.mapbase; 3851 uart->port.mapsize = up->port.mapsize; 3852 uart->port.private_data = up->port.private_data; 3853 uart->port.fifosize = up->port.fifosize; 3854 uart->tx_loadsz = up->tx_loadsz; 3855 uart->capabilities = up->capabilities; 3856 uart->port.throttle = up->port.throttle; 3857 uart->port.unthrottle = up->port.unthrottle; 3858 uart->port.rs485_config = up->port.rs485_config; 3859 uart->port.rs485 = up->port.rs485; 3860 uart->dma = up->dma; 3861 3862 /* Take tx_loadsz from fifosize if it wasn't set separately */ 3863 if (uart->port.fifosize && !uart->tx_loadsz) 3864 uart->tx_loadsz = uart->port.fifosize; 3865 3866 if (up->port.dev) 3867 uart->port.dev = up->port.dev; 3868 3869 if (skip_txen_test) 3870 uart->port.flags |= UPF_NO_TXEN_TEST; 3871 3872 if (up->port.flags & UPF_FIXED_TYPE) 3873 uart->port.type = up->port.type; 3874 3875 serial8250_set_defaults(uart); 3876 3877 /* Possibly override default I/O functions. */ 3878 if (up->port.serial_in) 3879 uart->port.serial_in = up->port.serial_in; 3880 if (up->port.serial_out) 3881 uart->port.serial_out = up->port.serial_out; 3882 if (up->port.handle_irq) 3883 uart->port.handle_irq = up->port.handle_irq; 3884 /* Possibly override set_termios call */ 3885 if (up->port.set_termios) 3886 uart->port.set_termios = up->port.set_termios; 3887 if (up->port.set_mctrl) 3888 uart->port.set_mctrl = up->port.set_mctrl; 3889 if (up->port.startup) 3890 uart->port.startup = up->port.startup; 3891 if (up->port.shutdown) 3892 uart->port.shutdown = up->port.shutdown; 3893 if (up->port.pm) 3894 uart->port.pm = up->port.pm; 3895 if (up->port.handle_break) 3896 uart->port.handle_break = up->port.handle_break; 3897 if (up->dl_read) 3898 uart->dl_read = up->dl_read; 3899 if (up->dl_write) 3900 uart->dl_write = up->dl_write; 3901 3902 if (serial8250_isa_config != NULL) 3903 serial8250_isa_config(0, &uart->port, 3904 &uart->capabilities); 3905 3906 ret = uart_add_one_port(&serial8250_reg, &uart->port); 3907 if (ret == 0) 3908 ret = uart->port.line; 3909 } 3910 mutex_unlock(&serial_mutex); 3911 3912 return ret; 3913 } 3914 EXPORT_SYMBOL(serial8250_register_8250_port); 3915 3916 /** 3917 * serial8250_unregister_port - remove a 16x50 serial port at runtime 3918 * @line: serial line number 3919 * 3920 * Remove one serial port. This may not be called from interrupt 3921 * context. We hand the port back to the our control. 3922 */ 3923 void serial8250_unregister_port(int line) 3924 { 3925 struct uart_8250_port *uart = &serial8250_ports[line]; 3926 3927 mutex_lock(&serial_mutex); 3928 uart_remove_one_port(&serial8250_reg, &uart->port); 3929 if (serial8250_isa_devs) { 3930 uart->port.flags &= ~UPF_BOOT_AUTOCONF; 3931 if (skip_txen_test) 3932 uart->port.flags |= UPF_NO_TXEN_TEST; 3933 uart->port.type = PORT_UNKNOWN; 3934 uart->port.dev = &serial8250_isa_devs->dev; 3935 uart->capabilities = 0; 3936 uart_add_one_port(&serial8250_reg, &uart->port); 3937 } else { 3938 uart->port.dev = NULL; 3939 } 3940 mutex_unlock(&serial_mutex); 3941 } 3942 EXPORT_SYMBOL(serial8250_unregister_port); 3943 3944 static int __init serial8250_init(void) 3945 { 3946 int ret; 3947 3948 serial8250_isa_init_ports(); 3949 3950 printk(KERN_INFO "Serial: 8250/16550 driver, " 3951 "%d ports, IRQ sharing %sabled\n", nr_uarts, 3952 share_irqs ? "en" : "dis"); 3953 3954 #ifdef CONFIG_SPARC 3955 ret = sunserial_register_minors(&serial8250_reg, UART_NR); 3956 #else 3957 serial8250_reg.nr = UART_NR; 3958 ret = uart_register_driver(&serial8250_reg); 3959 #endif 3960 if (ret) 3961 goto out; 3962 3963 ret = serial8250_pnp_init(); 3964 if (ret) 3965 goto unreg_uart_drv; 3966 3967 serial8250_isa_devs = platform_device_alloc("serial8250", 3968 PLAT8250_DEV_LEGACY); 3969 if (!serial8250_isa_devs) { 3970 ret = -ENOMEM; 3971 goto unreg_pnp; 3972 } 3973 3974 ret = platform_device_add(serial8250_isa_devs); 3975 if (ret) 3976 goto put_dev; 3977 3978 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev); 3979 3980 ret = platform_driver_register(&serial8250_isa_driver); 3981 if (ret == 0) 3982 goto out; 3983 3984 platform_device_del(serial8250_isa_devs); 3985 put_dev: 3986 platform_device_put(serial8250_isa_devs); 3987 unreg_pnp: 3988 serial8250_pnp_exit(); 3989 unreg_uart_drv: 3990 #ifdef CONFIG_SPARC 3991 sunserial_unregister_minors(&serial8250_reg, UART_NR); 3992 #else 3993 uart_unregister_driver(&serial8250_reg); 3994 #endif 3995 out: 3996 return ret; 3997 } 3998 3999 static void __exit serial8250_exit(void) 4000 { 4001 struct platform_device *isa_dev = serial8250_isa_devs; 4002 4003 /* 4004 * This tells serial8250_unregister_port() not to re-register 4005 * the ports (thereby making serial8250_isa_driver permanently 4006 * in use.) 4007 */ 4008 serial8250_isa_devs = NULL; 4009 4010 platform_driver_unregister(&serial8250_isa_driver); 4011 platform_device_unregister(isa_dev); 4012 4013 serial8250_pnp_exit(); 4014 4015 #ifdef CONFIG_SPARC 4016 sunserial_unregister_minors(&serial8250_reg, UART_NR); 4017 #else 4018 uart_unregister_driver(&serial8250_reg); 4019 #endif 4020 } 4021 4022 module_init(serial8250_init); 4023 module_exit(serial8250_exit); 4024 4025 EXPORT_SYMBOL(serial8250_suspend_port); 4026 EXPORT_SYMBOL(serial8250_resume_port); 4027 4028 MODULE_LICENSE("GPL"); 4029 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver"); 4030 4031 module_param(share_irqs, uint, 0644); 4032 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices" 4033 " (unsafe)"); 4034 4035 module_param(nr_uarts, uint, 0644); 4036 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")"); 4037 4038 module_param(skip_txen_test, uint, 0644); 4039 MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time"); 4040 4041 #ifdef CONFIG_SERIAL_8250_RSA 4042 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444); 4043 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA"); 4044 #endif 4045 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR); 4046 4047 #ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS 4048 #ifndef MODULE 4049 /* This module was renamed to 8250_core in 3.7. Keep the old "8250" name 4050 * working as well for the module options so we don't break people. We 4051 * need to keep the names identical and the convenient macros will happily 4052 * refuse to let us do that by failing the build with redefinition errors 4053 * of global variables. So we stick them inside a dummy function to avoid 4054 * those conflicts. The options still get parsed, and the redefined 4055 * MODULE_PARAM_PREFIX lets us keep the "8250." syntax alive. 4056 * 4057 * This is hacky. I'm sorry. 4058 */ 4059 static void __used s8250_options(void) 4060 { 4061 #undef MODULE_PARAM_PREFIX 4062 #define MODULE_PARAM_PREFIX "8250_core." 4063 4064 module_param_cb(share_irqs, ¶m_ops_uint, &share_irqs, 0644); 4065 module_param_cb(nr_uarts, ¶m_ops_uint, &nr_uarts, 0644); 4066 module_param_cb(skip_txen_test, ¶m_ops_uint, &skip_txen_test, 0644); 4067 #ifdef CONFIG_SERIAL_8250_RSA 4068 __module_param_call(MODULE_PARAM_PREFIX, probe_rsa, 4069 ¶m_array_ops, .arr = &__param_arr_probe_rsa, 4070 0444, -1, 0); 4071 #endif 4072 } 4073 #else 4074 MODULE_ALIAS("8250_core"); 4075 #endif 4076 #endif 4077