1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright (c) 2020, Broadcom */ 3 /* 4 * 8250-core based driver for Broadcom ns16550a UARTs 5 * 6 * This driver uses the standard 8250 driver core but adds additional 7 * optional features including the ability to use a baud rate clock 8 * mux for more accurate high speed baud rate selection and also 9 * an optional DMA engine. 10 * 11 */ 12 13 #include <linux/module.h> 14 #include <linux/types.h> 15 #include <linux/tty.h> 16 #include <linux/errno.h> 17 #include <linux/device.h> 18 #include <linux/io.h> 19 #include <linux/of.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/tty_flip.h> 22 #include <linux/delay.h> 23 #include <linux/clk.h> 24 #include <linux/debugfs.h> 25 26 #include "8250.h" 27 28 /* Register definitions for UART DMA block. Version 1.1 or later. */ 29 #define UDMA_ARB_RX 0x00 30 #define UDMA_ARB_TX 0x04 31 #define UDMA_ARB_REQ 0x00000001 32 #define UDMA_ARB_GRANT 0x00000002 33 34 #define UDMA_RX_REVISION 0x00 35 #define UDMA_RX_REVISION_REQUIRED 0x00000101 36 #define UDMA_RX_CTRL 0x04 37 #define UDMA_RX_CTRL_BUF_CLOSE_MODE 0x00010000 38 #define UDMA_RX_CTRL_MASK_WR_DONE 0x00008000 39 #define UDMA_RX_CTRL_ENDIAN_OVERRIDE 0x00004000 40 #define UDMA_RX_CTRL_ENDIAN 0x00002000 41 #define UDMA_RX_CTRL_OE_IS_ERR 0x00001000 42 #define UDMA_RX_CTRL_PE_IS_ERR 0x00000800 43 #define UDMA_RX_CTRL_FE_IS_ERR 0x00000400 44 #define UDMA_RX_CTRL_NUM_BUF_USED_MASK 0x000003c0 45 #define UDMA_RX_CTRL_NUM_BUF_USED_SHIFT 6 46 #define UDMA_RX_CTRL_BUF_CLOSE_CLK_SEL_SYS 0x00000020 47 #define UDMA_RX_CTRL_BUF_CLOSE_ENA 0x00000010 48 #define UDMA_RX_CTRL_TIMEOUT_CLK_SEL_SYS 0x00000008 49 #define UDMA_RX_CTRL_TIMEOUT_ENA 0x00000004 50 #define UDMA_RX_CTRL_ABORT 0x00000002 51 #define UDMA_RX_CTRL_ENA 0x00000001 52 #define UDMA_RX_STATUS 0x08 53 #define UDMA_RX_STATUS_ACTIVE_BUF_MASK 0x0000000f 54 #define UDMA_RX_TRANSFER_LEN 0x0c 55 #define UDMA_RX_TRANSFER_TOTAL 0x10 56 #define UDMA_RX_BUFFER_SIZE 0x14 57 #define UDMA_RX_SRC_ADDR 0x18 58 #define UDMA_RX_TIMEOUT 0x1c 59 #define UDMA_RX_BUFFER_CLOSE 0x20 60 #define UDMA_RX_BLOCKOUT_COUNTER 0x24 61 #define UDMA_RX_BUF0_PTR_LO 0x28 62 #define UDMA_RX_BUF0_PTR_HI 0x2c 63 #define UDMA_RX_BUF0_STATUS 0x30 64 #define UDMA_RX_BUFX_STATUS_OVERRUN_ERR 0x00000010 65 #define UDMA_RX_BUFX_STATUS_FRAME_ERR 0x00000008 66 #define UDMA_RX_BUFX_STATUS_PARITY_ERR 0x00000004 67 #define UDMA_RX_BUFX_STATUS_CLOSE_EXPIRED 0x00000002 68 #define UDMA_RX_BUFX_STATUS_DATA_RDY 0x00000001 69 #define UDMA_RX_BUF0_DATA_LEN 0x34 70 #define UDMA_RX_BUF1_PTR_LO 0x38 71 #define UDMA_RX_BUF1_PTR_HI 0x3c 72 #define UDMA_RX_BUF1_STATUS 0x40 73 #define UDMA_RX_BUF1_DATA_LEN 0x44 74 75 #define UDMA_TX_REVISION 0x00 76 #define UDMA_TX_REVISION_REQUIRED 0x00000101 77 #define UDMA_TX_CTRL 0x04 78 #define UDMA_TX_CTRL_ENDIAN_OVERRIDE 0x00000080 79 #define UDMA_TX_CTRL_ENDIAN 0x00000040 80 #define UDMA_TX_CTRL_NUM_BUF_USED_MASK 0x00000030 81 #define UDMA_TX_CTRL_NUM_BUF_USED_1 0x00000010 82 #define UDMA_TX_CTRL_ABORT 0x00000002 83 #define UDMA_TX_CTRL_ENA 0x00000001 84 #define UDMA_TX_DST_ADDR 0x08 85 #define UDMA_TX_BLOCKOUT_COUNTER 0x10 86 #define UDMA_TX_TRANSFER_LEN 0x14 87 #define UDMA_TX_TRANSFER_TOTAL 0x18 88 #define UDMA_TX_STATUS 0x20 89 #define UDMA_TX_BUF0_PTR_LO 0x24 90 #define UDMA_TX_BUF0_PTR_HI 0x28 91 #define UDMA_TX_BUF0_STATUS 0x2c 92 #define UDMA_TX_BUFX_LAST 0x00000002 93 #define UDMA_TX_BUFX_EMPTY 0x00000001 94 #define UDMA_TX_BUF0_DATA_LEN 0x30 95 #define UDMA_TX_BUF0_DATA_SENT 0x34 96 #define UDMA_TX_BUF1_PTR_LO 0x38 97 98 #define UDMA_INTR_STATUS 0x00 99 #define UDMA_INTR_ARB_TX_GRANT 0x00040000 100 #define UDMA_INTR_ARB_RX_GRANT 0x00020000 101 #define UDMA_INTR_TX_ALL_EMPTY 0x00010000 102 #define UDMA_INTR_TX_EMPTY_BUF1 0x00008000 103 #define UDMA_INTR_TX_EMPTY_BUF0 0x00004000 104 #define UDMA_INTR_TX_ABORT 0x00002000 105 #define UDMA_INTR_TX_DONE 0x00001000 106 #define UDMA_INTR_RX_ERROR 0x00000800 107 #define UDMA_INTR_RX_TIMEOUT 0x00000400 108 #define UDMA_INTR_RX_READY_BUF7 0x00000200 109 #define UDMA_INTR_RX_READY_BUF6 0x00000100 110 #define UDMA_INTR_RX_READY_BUF5 0x00000080 111 #define UDMA_INTR_RX_READY_BUF4 0x00000040 112 #define UDMA_INTR_RX_READY_BUF3 0x00000020 113 #define UDMA_INTR_RX_READY_BUF2 0x00000010 114 #define UDMA_INTR_RX_READY_BUF1 0x00000008 115 #define UDMA_INTR_RX_READY_BUF0 0x00000004 116 #define UDMA_INTR_RX_READY_MASK 0x000003fc 117 #define UDMA_INTR_RX_READY_SHIFT 2 118 #define UDMA_INTR_RX_ABORT 0x00000002 119 #define UDMA_INTR_RX_DONE 0x00000001 120 #define UDMA_INTR_SET 0x04 121 #define UDMA_INTR_CLEAR 0x08 122 #define UDMA_INTR_MASK_STATUS 0x0c 123 #define UDMA_INTR_MASK_SET 0x10 124 #define UDMA_INTR_MASK_CLEAR 0x14 125 126 127 #define UDMA_RX_INTERRUPTS ( \ 128 UDMA_INTR_RX_ERROR | \ 129 UDMA_INTR_RX_TIMEOUT | \ 130 UDMA_INTR_RX_READY_BUF0 | \ 131 UDMA_INTR_RX_READY_BUF1 | \ 132 UDMA_INTR_RX_READY_BUF2 | \ 133 UDMA_INTR_RX_READY_BUF3 | \ 134 UDMA_INTR_RX_READY_BUF4 | \ 135 UDMA_INTR_RX_READY_BUF5 | \ 136 UDMA_INTR_RX_READY_BUF6 | \ 137 UDMA_INTR_RX_READY_BUF7 | \ 138 UDMA_INTR_RX_ABORT | \ 139 UDMA_INTR_RX_DONE) 140 141 #define UDMA_RX_ERR_INTERRUPTS ( \ 142 UDMA_INTR_RX_ERROR | \ 143 UDMA_INTR_RX_TIMEOUT | \ 144 UDMA_INTR_RX_ABORT | \ 145 UDMA_INTR_RX_DONE) 146 147 #define UDMA_TX_INTERRUPTS ( \ 148 UDMA_INTR_TX_ABORT | \ 149 UDMA_INTR_TX_DONE) 150 151 #define UDMA_IS_RX_INTERRUPT(status) ((status) & UDMA_RX_INTERRUPTS) 152 #define UDMA_IS_TX_INTERRUPT(status) ((status) & UDMA_TX_INTERRUPTS) 153 154 155 /* Current devices have 8 sets of RX buffer registers */ 156 #define UDMA_RX_BUFS_COUNT 8 157 #define UDMA_RX_BUFS_REG_OFFSET (UDMA_RX_BUF1_PTR_LO - UDMA_RX_BUF0_PTR_LO) 158 #define UDMA_RX_BUFx_PTR_LO(x) (UDMA_RX_BUF0_PTR_LO + \ 159 ((x) * UDMA_RX_BUFS_REG_OFFSET)) 160 #define UDMA_RX_BUFx_PTR_HI(x) (UDMA_RX_BUF0_PTR_HI + \ 161 ((x) * UDMA_RX_BUFS_REG_OFFSET)) 162 #define UDMA_RX_BUFx_STATUS(x) (UDMA_RX_BUF0_STATUS + \ 163 ((x) * UDMA_RX_BUFS_REG_OFFSET)) 164 #define UDMA_RX_BUFx_DATA_LEN(x) (UDMA_RX_BUF0_DATA_LEN + \ 165 ((x) * UDMA_RX_BUFS_REG_OFFSET)) 166 167 /* Current devices have 2 sets of TX buffer registers */ 168 #define UDMA_TX_BUFS_COUNT 2 169 #define UDMA_TX_BUFS_REG_OFFSET (UDMA_TX_BUF1_PTR_LO - UDMA_TX_BUF0_PTR_LO) 170 #define UDMA_TX_BUFx_PTR_LO(x) (UDMA_TX_BUF0_PTR_LO + \ 171 ((x) * UDMA_TX_BUFS_REG_OFFSET)) 172 #define UDMA_TX_BUFx_PTR_HI(x) (UDMA_TX_BUF0_PTR_HI + \ 173 ((x) * UDMA_TX_BUFS_REG_OFFSET)) 174 #define UDMA_TX_BUFx_STATUS(x) (UDMA_TX_BUF0_STATUS + \ 175 ((x) * UDMA_TX_BUFS_REG_OFFSET)) 176 #define UDMA_TX_BUFx_DATA_LEN(x) (UDMA_TX_BUF0_DATA_LEN + \ 177 ((x) * UDMA_TX_BUFS_REG_OFFSET)) 178 #define UDMA_TX_BUFx_DATA_SENT(x) (UDMA_TX_BUF0_DATA_SENT + \ 179 ((x) * UDMA_TX_BUFS_REG_OFFSET)) 180 #define REGS_8250 0 181 #define REGS_DMA_RX 1 182 #define REGS_DMA_TX 2 183 #define REGS_DMA_ISR 3 184 #define REGS_DMA_ARB 4 185 #define REGS_MAX 5 186 187 #define TX_BUF_SIZE 4096 188 #define RX_BUF_SIZE 4096 189 #define RX_BUFS_COUNT 2 190 #define KHZ 1000 191 #define MHZ(x) ((x) * KHZ * KHZ) 192 193 static const u32 brcmstb_rate_table[] = { 194 MHZ(81), 195 MHZ(108), 196 MHZ(64), /* Actually 64285715 for some chips */ 197 MHZ(48), 198 }; 199 200 static const u32 brcmstb_rate_table_7278[] = { 201 MHZ(81), 202 MHZ(108), 203 0, 204 MHZ(48), 205 }; 206 207 struct brcmuart_priv { 208 int line; 209 struct clk *baud_mux_clk; 210 unsigned long default_mux_rate; 211 u32 real_rates[ARRAY_SIZE(brcmstb_rate_table)]; 212 const u32 *rate_table; 213 ktime_t char_wait; 214 struct uart_port *up; 215 struct hrtimer hrt; 216 bool shutdown; 217 bool dma_enabled; 218 struct uart_8250_dma dma; 219 void __iomem *regs[REGS_MAX]; 220 dma_addr_t rx_addr; 221 void *rx_bufs; 222 size_t rx_size; 223 int rx_next_buf; 224 dma_addr_t tx_addr; 225 void *tx_buf; 226 size_t tx_size; 227 bool tx_running; 228 bool rx_running; 229 struct dentry *debugfs_dir; 230 231 /* stats exposed through debugfs */ 232 u64 dma_rx_partial_buf; 233 u64 dma_rx_full_buf; 234 u32 rx_bad_timeout_late_char; 235 u32 rx_bad_timeout_no_char; 236 u32 rx_missing_close_timeout; 237 u32 rx_err; 238 u32 rx_timeout; 239 u32 rx_abort; 240 u32 saved_mctrl; 241 }; 242 243 static struct dentry *brcmuart_debugfs_root; 244 245 /* 246 * Register access routines 247 */ 248 static u32 udma_readl(struct brcmuart_priv *priv, 249 int reg_type, int offset) 250 { 251 return readl(priv->regs[reg_type] + offset); 252 } 253 254 static void udma_writel(struct brcmuart_priv *priv, 255 int reg_type, int offset, u32 value) 256 { 257 writel(value, priv->regs[reg_type] + offset); 258 } 259 260 static void udma_set(struct brcmuart_priv *priv, 261 int reg_type, int offset, u32 bits) 262 { 263 void __iomem *reg = priv->regs[reg_type] + offset; 264 u32 value; 265 266 value = readl(reg); 267 value |= bits; 268 writel(value, reg); 269 } 270 271 static void udma_unset(struct brcmuart_priv *priv, 272 int reg_type, int offset, u32 bits) 273 { 274 void __iomem *reg = priv->regs[reg_type] + offset; 275 u32 value; 276 277 value = readl(reg); 278 value &= ~bits; 279 writel(value, reg); 280 } 281 282 /* 283 * The UART DMA engine hardware can be used by multiple UARTS, but 284 * only one at a time. Sharing is not currently supported so 285 * the first UART to request the DMA engine will get it and any 286 * subsequent requests by other UARTS will fail. 287 */ 288 static int brcmuart_arbitration(struct brcmuart_priv *priv, bool acquire) 289 { 290 u32 rx_grant; 291 u32 tx_grant; 292 int waits; 293 int ret = 0; 294 295 if (acquire) { 296 udma_set(priv, REGS_DMA_ARB, UDMA_ARB_RX, UDMA_ARB_REQ); 297 udma_set(priv, REGS_DMA_ARB, UDMA_ARB_TX, UDMA_ARB_REQ); 298 299 waits = 1; 300 while (1) { 301 rx_grant = udma_readl(priv, REGS_DMA_ARB, UDMA_ARB_RX); 302 tx_grant = udma_readl(priv, REGS_DMA_ARB, UDMA_ARB_TX); 303 if (rx_grant & tx_grant & UDMA_ARB_GRANT) 304 return 0; 305 if (waits-- == 0) 306 break; 307 msleep(1); 308 } 309 ret = 1; 310 } 311 312 udma_unset(priv, REGS_DMA_ARB, UDMA_ARB_RX, UDMA_ARB_REQ); 313 udma_unset(priv, REGS_DMA_ARB, UDMA_ARB_TX, UDMA_ARB_REQ); 314 return ret; 315 } 316 317 static void brcmuart_init_dma_hardware(struct brcmuart_priv *priv) 318 { 319 u32 daddr; 320 u32 value; 321 int x; 322 323 /* Start with all interrupts disabled */ 324 udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_SET, 0xffffffff); 325 326 udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFFER_SIZE, RX_BUF_SIZE); 327 328 /* 329 * Setup buffer close to happen when 32 character times have 330 * elapsed since the last character was received. 331 */ 332 udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFFER_CLOSE, 16*10*32); 333 value = (RX_BUFS_COUNT << UDMA_RX_CTRL_NUM_BUF_USED_SHIFT) 334 | UDMA_RX_CTRL_BUF_CLOSE_MODE 335 | UDMA_RX_CTRL_BUF_CLOSE_ENA; 336 udma_writel(priv, REGS_DMA_RX, UDMA_RX_CTRL, value); 337 338 udma_writel(priv, REGS_DMA_RX, UDMA_RX_BLOCKOUT_COUNTER, 0); 339 daddr = priv->rx_addr; 340 for (x = 0; x < RX_BUFS_COUNT; x++) { 341 342 /* Set RX transfer length to 0 for unknown */ 343 udma_writel(priv, REGS_DMA_RX, UDMA_RX_TRANSFER_LEN, 0); 344 345 udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFx_PTR_LO(x), 346 lower_32_bits(daddr)); 347 udma_writel(priv, REGS_DMA_RX, UDMA_RX_BUFx_PTR_HI(x), 348 upper_32_bits(daddr)); 349 daddr += RX_BUF_SIZE; 350 } 351 352 daddr = priv->tx_addr; 353 udma_writel(priv, REGS_DMA_TX, UDMA_TX_BUFx_PTR_LO(0), 354 lower_32_bits(daddr)); 355 udma_writel(priv, REGS_DMA_TX, UDMA_TX_BUFx_PTR_HI(0), 356 upper_32_bits(daddr)); 357 udma_writel(priv, REGS_DMA_TX, UDMA_TX_CTRL, 358 UDMA_TX_CTRL_NUM_BUF_USED_1); 359 360 /* clear all interrupts then enable them */ 361 udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_CLEAR, 0xffffffff); 362 udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_CLEAR, 363 UDMA_RX_INTERRUPTS | UDMA_TX_INTERRUPTS); 364 365 } 366 367 static void start_rx_dma(struct uart_8250_port *p) 368 { 369 struct brcmuart_priv *priv = p->port.private_data; 370 int x; 371 372 udma_unset(priv, REGS_DMA_RX, UDMA_RX_CTRL, UDMA_RX_CTRL_ENA); 373 374 /* Clear the RX ready bit for all buffers */ 375 for (x = 0; x < RX_BUFS_COUNT; x++) 376 udma_unset(priv, REGS_DMA_RX, UDMA_RX_BUFx_STATUS(x), 377 UDMA_RX_BUFX_STATUS_DATA_RDY); 378 379 /* always start with buffer 0 */ 380 udma_unset(priv, REGS_DMA_RX, UDMA_RX_STATUS, 381 UDMA_RX_STATUS_ACTIVE_BUF_MASK); 382 priv->rx_next_buf = 0; 383 384 udma_set(priv, REGS_DMA_RX, UDMA_RX_CTRL, UDMA_RX_CTRL_ENA); 385 priv->rx_running = true; 386 } 387 388 static void stop_rx_dma(struct uart_8250_port *p) 389 { 390 struct brcmuart_priv *priv = p->port.private_data; 391 392 /* If RX is running, set the RX ABORT */ 393 if (priv->rx_running) 394 udma_set(priv, REGS_DMA_RX, UDMA_RX_CTRL, UDMA_RX_CTRL_ABORT); 395 } 396 397 static int stop_tx_dma(struct uart_8250_port *p) 398 { 399 struct brcmuart_priv *priv = p->port.private_data; 400 u32 value; 401 402 /* If TX is running, set the TX ABORT */ 403 value = udma_readl(priv, REGS_DMA_TX, UDMA_TX_CTRL); 404 if (value & UDMA_TX_CTRL_ENA) 405 udma_set(priv, REGS_DMA_TX, UDMA_TX_CTRL, UDMA_TX_CTRL_ABORT); 406 priv->tx_running = false; 407 return 0; 408 } 409 410 /* 411 * NOTE: printk's in this routine will hang the system if this is 412 * the console tty 413 */ 414 static int brcmuart_tx_dma(struct uart_8250_port *p) 415 { 416 struct brcmuart_priv *priv = p->port.private_data; 417 struct circ_buf *xmit = &p->port.state->xmit; 418 u32 tx_size; 419 420 if (uart_tx_stopped(&p->port) || priv->tx_running || 421 uart_circ_empty(xmit)) { 422 return 0; 423 } 424 tx_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE); 425 426 priv->dma.tx_err = 0; 427 memcpy(priv->tx_buf, &xmit->buf[xmit->tail], tx_size); 428 uart_xmit_advance(&p->port, tx_size); 429 430 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 431 uart_write_wakeup(&p->port); 432 433 udma_writel(priv, REGS_DMA_TX, UDMA_TX_TRANSFER_LEN, tx_size); 434 udma_writel(priv, REGS_DMA_TX, UDMA_TX_BUF0_DATA_LEN, tx_size); 435 udma_unset(priv, REGS_DMA_TX, UDMA_TX_BUF0_STATUS, UDMA_TX_BUFX_EMPTY); 436 udma_set(priv, REGS_DMA_TX, UDMA_TX_CTRL, UDMA_TX_CTRL_ENA); 437 priv->tx_running = true; 438 439 return 0; 440 } 441 442 static void brcmuart_rx_buf_done_isr(struct uart_port *up, int index) 443 { 444 struct brcmuart_priv *priv = up->private_data; 445 struct tty_port *tty_port = &up->state->port; 446 u32 status; 447 u32 length; 448 u32 copied; 449 450 /* Make sure we're still in sync with the hardware */ 451 status = udma_readl(priv, REGS_DMA_RX, UDMA_RX_BUFx_STATUS(index)); 452 length = udma_readl(priv, REGS_DMA_RX, UDMA_RX_BUFx_DATA_LEN(index)); 453 454 if ((status & UDMA_RX_BUFX_STATUS_DATA_RDY) == 0) { 455 dev_err(up->dev, "RX done interrupt but DATA_RDY not found\n"); 456 return; 457 } 458 if (status & (UDMA_RX_BUFX_STATUS_OVERRUN_ERR | 459 UDMA_RX_BUFX_STATUS_FRAME_ERR | 460 UDMA_RX_BUFX_STATUS_PARITY_ERR)) { 461 if (status & UDMA_RX_BUFX_STATUS_OVERRUN_ERR) { 462 up->icount.overrun++; 463 dev_warn(up->dev, "RX OVERRUN Error\n"); 464 } 465 if (status & UDMA_RX_BUFX_STATUS_FRAME_ERR) { 466 up->icount.frame++; 467 dev_warn(up->dev, "RX FRAMING Error\n"); 468 } 469 if (status & UDMA_RX_BUFX_STATUS_PARITY_ERR) { 470 up->icount.parity++; 471 dev_warn(up->dev, "RX PARITY Error\n"); 472 } 473 } 474 copied = (u32)tty_insert_flip_string( 475 tty_port, 476 priv->rx_bufs + (index * RX_BUF_SIZE), 477 length); 478 if (copied != length) { 479 dev_warn(up->dev, "Flip buffer overrun of %d bytes\n", 480 length - copied); 481 up->icount.overrun += length - copied; 482 } 483 up->icount.rx += length; 484 if (status & UDMA_RX_BUFX_STATUS_CLOSE_EXPIRED) 485 priv->dma_rx_partial_buf++; 486 else if (length != RX_BUF_SIZE) 487 /* 488 * This is a bug in the controller that doesn't cause 489 * any problems but will be fixed in the future. 490 */ 491 priv->rx_missing_close_timeout++; 492 else 493 priv->dma_rx_full_buf++; 494 495 tty_flip_buffer_push(tty_port); 496 } 497 498 static void brcmuart_rx_isr(struct uart_port *up, u32 rx_isr) 499 { 500 struct brcmuart_priv *priv = up->private_data; 501 struct device *dev = up->dev; 502 u32 rx_done_isr; 503 u32 check_isr; 504 505 rx_done_isr = (rx_isr & UDMA_INTR_RX_READY_MASK); 506 while (rx_done_isr) { 507 check_isr = UDMA_INTR_RX_READY_BUF0 << priv->rx_next_buf; 508 if (check_isr & rx_done_isr) { 509 brcmuart_rx_buf_done_isr(up, priv->rx_next_buf); 510 } else { 511 dev_err(dev, 512 "RX buffer ready out of sequence, restarting RX DMA\n"); 513 start_rx_dma(up_to_u8250p(up)); 514 break; 515 } 516 if (rx_isr & UDMA_RX_ERR_INTERRUPTS) { 517 if (rx_isr & UDMA_INTR_RX_ERROR) 518 priv->rx_err++; 519 if (rx_isr & UDMA_INTR_RX_TIMEOUT) { 520 priv->rx_timeout++; 521 dev_err(dev, "RX TIMEOUT Error\n"); 522 } 523 if (rx_isr & UDMA_INTR_RX_ABORT) 524 priv->rx_abort++; 525 priv->rx_running = false; 526 } 527 /* If not ABORT, re-enable RX buffer */ 528 if (!(rx_isr & UDMA_INTR_RX_ABORT)) 529 udma_unset(priv, REGS_DMA_RX, 530 UDMA_RX_BUFx_STATUS(priv->rx_next_buf), 531 UDMA_RX_BUFX_STATUS_DATA_RDY); 532 rx_done_isr &= ~check_isr; 533 priv->rx_next_buf++; 534 if (priv->rx_next_buf == RX_BUFS_COUNT) 535 priv->rx_next_buf = 0; 536 } 537 } 538 539 static void brcmuart_tx_isr(struct uart_port *up, u32 isr) 540 { 541 struct brcmuart_priv *priv = up->private_data; 542 struct device *dev = up->dev; 543 struct uart_8250_port *port_8250 = up_to_u8250p(up); 544 struct circ_buf *xmit = &port_8250->port.state->xmit; 545 546 if (isr & UDMA_INTR_TX_ABORT) { 547 if (priv->tx_running) 548 dev_err(dev, "Unexpected TX_ABORT interrupt\n"); 549 return; 550 } 551 priv->tx_running = false; 552 if (!uart_circ_empty(xmit) && !uart_tx_stopped(up)) 553 brcmuart_tx_dma(port_8250); 554 } 555 556 static irqreturn_t brcmuart_isr(int irq, void *dev_id) 557 { 558 struct uart_port *up = dev_id; 559 struct device *dev = up->dev; 560 struct brcmuart_priv *priv = up->private_data; 561 unsigned long flags; 562 u32 interrupts; 563 u32 rval; 564 u32 tval; 565 566 interrupts = udma_readl(priv, REGS_DMA_ISR, UDMA_INTR_STATUS); 567 if (interrupts == 0) 568 return IRQ_NONE; 569 570 spin_lock_irqsave(&up->lock, flags); 571 572 /* Clear all interrupts */ 573 udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_CLEAR, interrupts); 574 575 rval = UDMA_IS_RX_INTERRUPT(interrupts); 576 if (rval) 577 brcmuart_rx_isr(up, rval); 578 tval = UDMA_IS_TX_INTERRUPT(interrupts); 579 if (tval) 580 brcmuart_tx_isr(up, tval); 581 if ((rval | tval) == 0) 582 dev_warn(dev, "Spurious interrupt: 0x%x\n", interrupts); 583 584 spin_unlock_irqrestore(&up->lock, flags); 585 return IRQ_HANDLED; 586 } 587 588 static int brcmuart_startup(struct uart_port *port) 589 { 590 int res; 591 struct uart_8250_port *up = up_to_u8250p(port); 592 struct brcmuart_priv *priv = up->port.private_data; 593 594 priv->shutdown = false; 595 596 /* 597 * prevent serial8250_do_startup() from allocating non-existent 598 * DMA resources 599 */ 600 up->dma = NULL; 601 602 res = serial8250_do_startup(port); 603 if (!priv->dma_enabled) 604 return res; 605 /* 606 * Disable the Receive Data Interrupt because the DMA engine 607 * will handle this. 608 * 609 * Synchronize UART_IER access against the console. 610 */ 611 spin_lock_irq(&port->lock); 612 up->ier &= ~UART_IER_RDI; 613 serial_port_out(port, UART_IER, up->ier); 614 spin_unlock_irq(&port->lock); 615 616 priv->tx_running = false; 617 priv->dma.rx_dma = NULL; 618 priv->dma.tx_dma = brcmuart_tx_dma; 619 up->dma = &priv->dma; 620 621 brcmuart_init_dma_hardware(priv); 622 start_rx_dma(up); 623 return res; 624 } 625 626 static void brcmuart_shutdown(struct uart_port *port) 627 { 628 struct uart_8250_port *up = up_to_u8250p(port); 629 struct brcmuart_priv *priv = up->port.private_data; 630 unsigned long flags; 631 632 spin_lock_irqsave(&port->lock, flags); 633 priv->shutdown = true; 634 if (priv->dma_enabled) { 635 stop_rx_dma(up); 636 stop_tx_dma(up); 637 /* disable all interrupts */ 638 udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_SET, 639 UDMA_RX_INTERRUPTS | UDMA_TX_INTERRUPTS); 640 } 641 642 /* 643 * prevent serial8250_do_shutdown() from trying to free 644 * DMA resources that we never alloc'd for this driver. 645 */ 646 up->dma = NULL; 647 648 spin_unlock_irqrestore(&port->lock, flags); 649 serial8250_do_shutdown(port); 650 } 651 652 /* 653 * Not all clocks run at the exact specified rate, so set each requested 654 * rate and then get the actual rate. 655 */ 656 static void init_real_clk_rates(struct device *dev, struct brcmuart_priv *priv) 657 { 658 int x; 659 int rc; 660 661 priv->default_mux_rate = clk_get_rate(priv->baud_mux_clk); 662 for (x = 0; x < ARRAY_SIZE(priv->real_rates); x++) { 663 if (priv->rate_table[x] == 0) { 664 priv->real_rates[x] = 0; 665 continue; 666 } 667 rc = clk_set_rate(priv->baud_mux_clk, priv->rate_table[x]); 668 if (rc) { 669 dev_err(dev, "Error selecting BAUD MUX clock for %u\n", 670 priv->rate_table[x]); 671 priv->real_rates[x] = priv->rate_table[x]; 672 } else { 673 priv->real_rates[x] = clk_get_rate(priv->baud_mux_clk); 674 } 675 } 676 clk_set_rate(priv->baud_mux_clk, priv->default_mux_rate); 677 } 678 679 static u32 find_quot(struct device *dev, u32 freq, u32 baud, u32 *percent) 680 { 681 u32 quot; 682 u32 rate; 683 u64 hires_rate; 684 u64 hires_baud; 685 u64 hires_err; 686 687 rate = freq / 16; 688 quot = DIV_ROUND_CLOSEST(rate, baud); 689 if (!quot) 690 return 0; 691 692 /* increase resolution to get xx.xx percent */ 693 hires_rate = div_u64((u64)rate * 10000, (u64)quot); 694 hires_baud = (u64)baud * 10000; 695 696 /* get the delta */ 697 if (hires_rate > hires_baud) 698 hires_err = (hires_rate - hires_baud); 699 else 700 hires_err = (hires_baud - hires_rate); 701 702 *percent = (unsigned long)DIV_ROUND_CLOSEST_ULL(hires_err, baud); 703 704 dev_dbg(dev, "Baud rate: %u, MUX Clk: %u, Error: %u.%u%%\n", 705 baud, freq, *percent / 100, *percent % 100); 706 707 return quot; 708 } 709 710 static void set_clock_mux(struct uart_port *up, struct brcmuart_priv *priv, 711 u32 baud) 712 { 713 u32 percent; 714 u32 best_percent = UINT_MAX; 715 u32 quot; 716 u32 freq; 717 u32 best_quot = 1; 718 u32 best_freq = 0; 719 int rc; 720 int i; 721 int real_baud; 722 723 /* If the Baud Mux Clock was not specified, just return */ 724 if (priv->baud_mux_clk == NULL) 725 return; 726 727 /* Try default_mux_rate first */ 728 quot = find_quot(up->dev, priv->default_mux_rate, baud, &percent); 729 if (quot) { 730 best_percent = percent; 731 best_freq = priv->default_mux_rate; 732 best_quot = quot; 733 } 734 /* If more than 1% error, find the closest match for specified baud */ 735 if (best_percent > 100) { 736 for (i = 0; i < ARRAY_SIZE(priv->real_rates); i++) { 737 freq = priv->real_rates[i]; 738 if (freq == 0 || freq == priv->default_mux_rate) 739 continue; 740 quot = find_quot(up->dev, freq, baud, &percent); 741 if (!quot) 742 continue; 743 744 if (percent < best_percent) { 745 best_percent = percent; 746 best_freq = freq; 747 best_quot = quot; 748 } 749 } 750 } 751 if (!best_freq) { 752 dev_err(up->dev, "Error, %d BAUD rate is too fast.\n", baud); 753 return; 754 } 755 rc = clk_set_rate(priv->baud_mux_clk, best_freq); 756 if (rc) 757 dev_err(up->dev, "Error selecting BAUD MUX clock\n"); 758 759 /* Error over 3 percent will cause data errors */ 760 if (best_percent > 300) 761 dev_err(up->dev, "Error, baud: %d has %u.%u%% error\n", 762 baud, percent / 100, percent % 100); 763 764 real_baud = best_freq / 16 / best_quot; 765 dev_dbg(up->dev, "Selecting BAUD MUX rate: %u\n", best_freq); 766 dev_dbg(up->dev, "Requested baud: %u, Actual baud: %u\n", 767 baud, real_baud); 768 769 /* calc nanoseconds for 1.5 characters time at the given baud rate */ 770 i = NSEC_PER_SEC / real_baud / 10; 771 i += (i / 2); 772 priv->char_wait = ns_to_ktime(i); 773 774 up->uartclk = best_freq; 775 } 776 777 static void brcmstb_set_termios(struct uart_port *up, 778 struct ktermios *termios, 779 const struct ktermios *old) 780 { 781 struct uart_8250_port *p8250 = up_to_u8250p(up); 782 struct brcmuart_priv *priv = up->private_data; 783 784 if (priv->dma_enabled) 785 stop_rx_dma(p8250); 786 set_clock_mux(up, priv, tty_termios_baud_rate(termios)); 787 serial8250_do_set_termios(up, termios, old); 788 if (p8250->mcr & UART_MCR_AFE) 789 p8250->port.status |= UPSTAT_AUTOCTS; 790 if (priv->dma_enabled) 791 start_rx_dma(p8250); 792 } 793 794 static int brcmuart_handle_irq(struct uart_port *p) 795 { 796 unsigned int iir = serial_port_in(p, UART_IIR); 797 struct brcmuart_priv *priv = p->private_data; 798 struct uart_8250_port *up = up_to_u8250p(p); 799 unsigned int status; 800 unsigned long flags; 801 unsigned int ier; 802 unsigned int mcr; 803 int handled = 0; 804 805 /* 806 * There's a bug in some 8250 cores where we get a timeout 807 * interrupt but there is no data ready. 808 */ 809 if (((iir & UART_IIR_ID) == UART_IIR_RX_TIMEOUT) && !(priv->shutdown)) { 810 spin_lock_irqsave(&p->lock, flags); 811 status = serial_port_in(p, UART_LSR); 812 if ((status & UART_LSR_DR) == 0) { 813 814 ier = serial_port_in(p, UART_IER); 815 /* 816 * if Receive Data Interrupt is enabled and 817 * we're uing hardware flow control, deassert 818 * RTS and wait for any chars in the pipline to 819 * arrive and then check for DR again. 820 */ 821 if ((ier & UART_IER_RDI) && (up->mcr & UART_MCR_AFE)) { 822 ier &= ~(UART_IER_RLSI | UART_IER_RDI); 823 serial_port_out(p, UART_IER, ier); 824 mcr = serial_port_in(p, UART_MCR); 825 mcr &= ~UART_MCR_RTS; 826 serial_port_out(p, UART_MCR, mcr); 827 hrtimer_start(&priv->hrt, priv->char_wait, 828 HRTIMER_MODE_REL); 829 } else { 830 serial_port_in(p, UART_RX); 831 } 832 833 handled = 1; 834 } 835 spin_unlock_irqrestore(&p->lock, flags); 836 if (handled) 837 return 1; 838 } 839 return serial8250_handle_irq(p, iir); 840 } 841 842 static enum hrtimer_restart brcmuart_hrtimer_func(struct hrtimer *t) 843 { 844 struct brcmuart_priv *priv = container_of(t, struct brcmuart_priv, hrt); 845 struct uart_port *p = priv->up; 846 struct uart_8250_port *up = up_to_u8250p(p); 847 unsigned int status; 848 unsigned long flags; 849 850 if (priv->shutdown) 851 return HRTIMER_NORESTART; 852 853 spin_lock_irqsave(&p->lock, flags); 854 status = serial_port_in(p, UART_LSR); 855 856 /* 857 * If a character did not arrive after the timeout, clear the false 858 * receive timeout. 859 */ 860 if ((status & UART_LSR_DR) == 0) { 861 serial_port_in(p, UART_RX); 862 priv->rx_bad_timeout_no_char++; 863 } else { 864 priv->rx_bad_timeout_late_char++; 865 } 866 867 /* re-enable receive unless upper layer has disabled it */ 868 if ((up->ier & (UART_IER_RLSI | UART_IER_RDI)) == 869 (UART_IER_RLSI | UART_IER_RDI)) { 870 status = serial_port_in(p, UART_IER); 871 status |= (UART_IER_RLSI | UART_IER_RDI); 872 serial_port_out(p, UART_IER, status); 873 status = serial_port_in(p, UART_MCR); 874 status |= UART_MCR_RTS; 875 serial_port_out(p, UART_MCR, status); 876 } 877 spin_unlock_irqrestore(&p->lock, flags); 878 return HRTIMER_NORESTART; 879 } 880 881 static const struct of_device_id brcmuart_dt_ids[] = { 882 { 883 .compatible = "brcm,bcm7278-uart", 884 .data = brcmstb_rate_table_7278, 885 }, 886 { 887 .compatible = "brcm,bcm7271-uart", 888 .data = brcmstb_rate_table, 889 }, 890 {}, 891 }; 892 893 MODULE_DEVICE_TABLE(of, brcmuart_dt_ids); 894 895 static void brcmuart_free_bufs(struct device *dev, struct brcmuart_priv *priv) 896 { 897 if (priv->rx_bufs) 898 dma_free_coherent(dev, priv->rx_size, priv->rx_bufs, 899 priv->rx_addr); 900 if (priv->tx_buf) 901 dma_free_coherent(dev, priv->tx_size, priv->tx_buf, 902 priv->tx_addr); 903 } 904 905 static void brcmuart_throttle(struct uart_port *port) 906 { 907 struct brcmuart_priv *priv = port->private_data; 908 909 udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_SET, UDMA_RX_INTERRUPTS); 910 } 911 912 static void brcmuart_unthrottle(struct uart_port *port) 913 { 914 struct brcmuart_priv *priv = port->private_data; 915 916 udma_writel(priv, REGS_DMA_ISR, UDMA_INTR_MASK_CLEAR, 917 UDMA_RX_INTERRUPTS); 918 } 919 920 static int debugfs_stats_show(struct seq_file *s, void *unused) 921 { 922 struct brcmuart_priv *priv = s->private; 923 924 seq_printf(s, "rx_err:\t\t\t\t%u\n", 925 priv->rx_err); 926 seq_printf(s, "rx_timeout:\t\t\t%u\n", 927 priv->rx_timeout); 928 seq_printf(s, "rx_abort:\t\t\t%u\n", 929 priv->rx_abort); 930 seq_printf(s, "rx_bad_timeout_late_char:\t%u\n", 931 priv->rx_bad_timeout_late_char); 932 seq_printf(s, "rx_bad_timeout_no_char:\t\t%u\n", 933 priv->rx_bad_timeout_no_char); 934 seq_printf(s, "rx_missing_close_timeout:\t%u\n", 935 priv->rx_missing_close_timeout); 936 if (priv->dma_enabled) { 937 seq_printf(s, "dma_rx_partial_buf:\t\t%llu\n", 938 priv->dma_rx_partial_buf); 939 seq_printf(s, "dma_rx_full_buf:\t\t%llu\n", 940 priv->dma_rx_full_buf); 941 } 942 return 0; 943 } 944 DEFINE_SHOW_ATTRIBUTE(debugfs_stats); 945 946 static void brcmuart_init_debugfs(struct brcmuart_priv *priv, 947 const char *device) 948 { 949 priv->debugfs_dir = debugfs_create_dir(device, brcmuart_debugfs_root); 950 debugfs_create_file("stats", 0444, priv->debugfs_dir, priv, 951 &debugfs_stats_fops); 952 } 953 954 955 static int brcmuart_probe(struct platform_device *pdev) 956 { 957 struct resource *regs; 958 struct device_node *np = pdev->dev.of_node; 959 const struct of_device_id *of_id = NULL; 960 struct uart_8250_port *new_port; 961 struct device *dev = &pdev->dev; 962 struct brcmuart_priv *priv; 963 struct clk *baud_mux_clk; 964 struct uart_8250_port up; 965 int irq; 966 void __iomem *membase = NULL; 967 resource_size_t mapbase = 0; 968 u32 clk_rate = 0; 969 int ret; 970 int x; 971 int dma_irq; 972 static const char * const reg_names[REGS_MAX] = { 973 "uart", "dma_rx", "dma_tx", "dma_intr2", "dma_arb" 974 }; 975 976 irq = platform_get_irq(pdev, 0); 977 if (irq < 0) 978 return irq; 979 priv = devm_kzalloc(dev, sizeof(struct brcmuart_priv), 980 GFP_KERNEL); 981 if (!priv) 982 return -ENOMEM; 983 984 of_id = of_match_node(brcmuart_dt_ids, np); 985 if (!of_id || !of_id->data) 986 priv->rate_table = brcmstb_rate_table; 987 else 988 priv->rate_table = of_id->data; 989 990 for (x = 0; x < REGS_MAX; x++) { 991 regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, 992 reg_names[x]); 993 if (!regs) 994 break; 995 priv->regs[x] = devm_ioremap(dev, regs->start, 996 resource_size(regs)); 997 if (!priv->regs[x]) 998 return -ENOMEM; 999 if (x == REGS_8250) { 1000 mapbase = regs->start; 1001 membase = priv->regs[x]; 1002 } 1003 } 1004 1005 /* We should have just the uart base registers or all the registers */ 1006 if (x != 1 && x != REGS_MAX) { 1007 dev_warn(dev, "%s registers not specified\n", reg_names[x]); 1008 return -EINVAL; 1009 } 1010 1011 /* if the DMA registers were specified, try to enable DMA */ 1012 if (x > REGS_DMA_RX) { 1013 if (brcmuart_arbitration(priv, 1) == 0) { 1014 u32 txrev = 0; 1015 u32 rxrev = 0; 1016 1017 txrev = udma_readl(priv, REGS_DMA_RX, UDMA_RX_REVISION); 1018 rxrev = udma_readl(priv, REGS_DMA_TX, UDMA_TX_REVISION); 1019 if ((txrev >= UDMA_TX_REVISION_REQUIRED) && 1020 (rxrev >= UDMA_RX_REVISION_REQUIRED)) { 1021 1022 /* Enable the use of the DMA hardware */ 1023 priv->dma_enabled = true; 1024 } else { 1025 brcmuart_arbitration(priv, 0); 1026 dev_err(dev, 1027 "Unsupported DMA Hardware Revision\n"); 1028 } 1029 } else { 1030 dev_err(dev, 1031 "Timeout arbitrating for UART DMA hardware\n"); 1032 } 1033 } 1034 1035 of_property_read_u32(np, "clock-frequency", &clk_rate); 1036 1037 /* See if a Baud clock has been specified */ 1038 baud_mux_clk = devm_clk_get(dev, "sw_baud"); 1039 if (IS_ERR(baud_mux_clk)) { 1040 if (PTR_ERR(baud_mux_clk) == -EPROBE_DEFER) { 1041 ret = -EPROBE_DEFER; 1042 goto release_dma; 1043 } 1044 dev_dbg(dev, "BAUD MUX clock not specified\n"); 1045 } else { 1046 dev_dbg(dev, "BAUD MUX clock found\n"); 1047 ret = clk_prepare_enable(baud_mux_clk); 1048 if (ret) 1049 goto release_dma; 1050 priv->baud_mux_clk = baud_mux_clk; 1051 init_real_clk_rates(dev, priv); 1052 clk_rate = priv->default_mux_rate; 1053 } 1054 1055 if (clk_rate == 0) { 1056 dev_err(dev, "clock-frequency or clk not defined\n"); 1057 ret = -EINVAL; 1058 goto err_clk_disable; 1059 } 1060 1061 dev_dbg(dev, "DMA is %senabled\n", priv->dma_enabled ? "" : "not "); 1062 1063 memset(&up, 0, sizeof(up)); 1064 up.port.type = PORT_BCM7271; 1065 up.port.uartclk = clk_rate; 1066 up.port.dev = dev; 1067 up.port.mapbase = mapbase; 1068 up.port.membase = membase; 1069 up.port.irq = irq; 1070 up.port.handle_irq = brcmuart_handle_irq; 1071 up.port.regshift = 2; 1072 up.port.iotype = of_device_is_big_endian(np) ? 1073 UPIO_MEM32BE : UPIO_MEM32; 1074 up.port.flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF 1075 | UPF_FIXED_PORT | UPF_FIXED_TYPE; 1076 up.port.dev = dev; 1077 up.port.private_data = priv; 1078 1079 /* Check for a fixed line number */ 1080 ret = of_alias_get_id(np, "serial"); 1081 if (ret >= 0) 1082 up.port.line = ret; 1083 1084 /* setup HR timer */ 1085 hrtimer_init(&priv->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_ABS); 1086 priv->hrt.function = brcmuart_hrtimer_func; 1087 1088 up.port.shutdown = brcmuart_shutdown; 1089 up.port.startup = brcmuart_startup; 1090 up.port.throttle = brcmuart_throttle; 1091 up.port.unthrottle = brcmuart_unthrottle; 1092 up.port.set_termios = brcmstb_set_termios; 1093 1094 if (priv->dma_enabled) { 1095 priv->rx_size = RX_BUF_SIZE * RX_BUFS_COUNT; 1096 priv->rx_bufs = dma_alloc_coherent(dev, 1097 priv->rx_size, 1098 &priv->rx_addr, GFP_KERNEL); 1099 if (!priv->rx_bufs) { 1100 ret = -ENOMEM; 1101 goto err; 1102 } 1103 priv->tx_size = UART_XMIT_SIZE; 1104 priv->tx_buf = dma_alloc_coherent(dev, 1105 priv->tx_size, 1106 &priv->tx_addr, GFP_KERNEL); 1107 if (!priv->tx_buf) { 1108 ret = -ENOMEM; 1109 goto err; 1110 } 1111 } 1112 1113 ret = serial8250_register_8250_port(&up); 1114 if (ret < 0) { 1115 dev_err(dev, "unable to register 8250 port\n"); 1116 goto err; 1117 } 1118 priv->line = ret; 1119 new_port = serial8250_get_port(ret); 1120 priv->up = &new_port->port; 1121 if (priv->dma_enabled) { 1122 dma_irq = platform_get_irq_byname(pdev, "dma"); 1123 if (dma_irq < 0) { 1124 ret = dma_irq; 1125 dev_err(dev, "no IRQ resource info\n"); 1126 goto err1; 1127 } 1128 ret = devm_request_irq(dev, dma_irq, brcmuart_isr, 1129 IRQF_SHARED, "uart DMA irq", &new_port->port); 1130 if (ret) { 1131 dev_err(dev, "unable to register IRQ handler\n"); 1132 goto err1; 1133 } 1134 } 1135 platform_set_drvdata(pdev, priv); 1136 brcmuart_init_debugfs(priv, dev_name(&pdev->dev)); 1137 return 0; 1138 1139 err1: 1140 serial8250_unregister_port(priv->line); 1141 err: 1142 brcmuart_free_bufs(dev, priv); 1143 err_clk_disable: 1144 clk_disable_unprepare(baud_mux_clk); 1145 release_dma: 1146 if (priv->dma_enabled) 1147 brcmuart_arbitration(priv, 0); 1148 return ret; 1149 } 1150 1151 static int brcmuart_remove(struct platform_device *pdev) 1152 { 1153 struct brcmuart_priv *priv = platform_get_drvdata(pdev); 1154 1155 debugfs_remove_recursive(priv->debugfs_dir); 1156 hrtimer_cancel(&priv->hrt); 1157 serial8250_unregister_port(priv->line); 1158 brcmuart_free_bufs(&pdev->dev, priv); 1159 clk_disable_unprepare(priv->baud_mux_clk); 1160 if (priv->dma_enabled) 1161 brcmuart_arbitration(priv, 0); 1162 return 0; 1163 } 1164 1165 static int __maybe_unused brcmuart_suspend(struct device *dev) 1166 { 1167 struct brcmuart_priv *priv = dev_get_drvdata(dev); 1168 struct uart_8250_port *up = serial8250_get_port(priv->line); 1169 struct uart_port *port = &up->port; 1170 unsigned long flags; 1171 1172 /* 1173 * This will prevent resume from enabling RTS before the 1174 * baud rate has been restored. 1175 */ 1176 spin_lock_irqsave(&port->lock, flags); 1177 priv->saved_mctrl = port->mctrl; 1178 port->mctrl &= ~TIOCM_RTS; 1179 spin_unlock_irqrestore(&port->lock, flags); 1180 1181 serial8250_suspend_port(priv->line); 1182 clk_disable_unprepare(priv->baud_mux_clk); 1183 1184 return 0; 1185 } 1186 1187 static int __maybe_unused brcmuart_resume(struct device *dev) 1188 { 1189 struct brcmuart_priv *priv = dev_get_drvdata(dev); 1190 struct uart_8250_port *up = serial8250_get_port(priv->line); 1191 struct uart_port *port = &up->port; 1192 unsigned long flags; 1193 int ret; 1194 1195 ret = clk_prepare_enable(priv->baud_mux_clk); 1196 if (ret) 1197 dev_err(dev, "Error enabling BAUD MUX clock\n"); 1198 1199 /* 1200 * The hardware goes back to it's default after suspend 1201 * so get the "clk" back in sync. 1202 */ 1203 ret = clk_set_rate(priv->baud_mux_clk, priv->default_mux_rate); 1204 if (ret) 1205 dev_err(dev, "Error restoring default BAUD MUX clock\n"); 1206 if (priv->dma_enabled) { 1207 if (brcmuart_arbitration(priv, 1)) { 1208 dev_err(dev, "Timeout arbitrating for DMA hardware on resume\n"); 1209 return(-EBUSY); 1210 } 1211 brcmuart_init_dma_hardware(priv); 1212 start_rx_dma(serial8250_get_port(priv->line)); 1213 } 1214 serial8250_resume_port(priv->line); 1215 1216 if (priv->saved_mctrl & TIOCM_RTS) { 1217 /* Restore RTS */ 1218 spin_lock_irqsave(&port->lock, flags); 1219 port->mctrl |= TIOCM_RTS; 1220 port->ops->set_mctrl(port, port->mctrl); 1221 spin_unlock_irqrestore(&port->lock, flags); 1222 } 1223 1224 return 0; 1225 } 1226 1227 static const struct dev_pm_ops brcmuart_dev_pm_ops = { 1228 SET_SYSTEM_SLEEP_PM_OPS(brcmuart_suspend, brcmuart_resume) 1229 }; 1230 1231 static struct platform_driver brcmuart_platform_driver = { 1232 .driver = { 1233 .name = "bcm7271-uart", 1234 .pm = &brcmuart_dev_pm_ops, 1235 .of_match_table = brcmuart_dt_ids, 1236 }, 1237 .probe = brcmuart_probe, 1238 .remove = brcmuart_remove, 1239 }; 1240 1241 static int __init brcmuart_init(void) 1242 { 1243 int ret; 1244 1245 brcmuart_debugfs_root = debugfs_create_dir( 1246 brcmuart_platform_driver.driver.name, NULL); 1247 ret = platform_driver_register(&brcmuart_platform_driver); 1248 if (ret) { 1249 debugfs_remove_recursive(brcmuart_debugfs_root); 1250 return ret; 1251 } 1252 1253 return 0; 1254 } 1255 module_init(brcmuart_init); 1256 1257 static void __exit brcmuart_deinit(void) 1258 { 1259 platform_driver_unregister(&brcmuart_platform_driver); 1260 debugfs_remove_recursive(brcmuart_debugfs_root); 1261 } 1262 module_exit(brcmuart_deinit); 1263 1264 MODULE_AUTHOR("Al Cooper"); 1265 MODULE_DESCRIPTION("Broadcom NS16550A compatible serial port driver"); 1266 MODULE_LICENSE("GPL v2"); 1267