1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * mxser.c -- MOXA Smartio/Industio family multiport serial driver. 4 * 5 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com). 6 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com> 7 * 8 * This code is loosely based on the 1.8 moxa driver which is based on 9 * Linux serial driver, written by Linus Torvalds, Theodore T'so and 10 * others. 11 * 12 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox 13 * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on 14 * www.moxa.com. 15 * - Fixed x86_64 cleanness 16 */ 17 18 #include <linux/module.h> 19 #include <linux/errno.h> 20 #include <linux/signal.h> 21 #include <linux/sched.h> 22 #include <linux/timer.h> 23 #include <linux/interrupt.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/serial.h> 27 #include <linux/serial_reg.h> 28 #include <linux/major.h> 29 #include <linux/string.h> 30 #include <linux/fcntl.h> 31 #include <linux/ptrace.h> 32 #include <linux/ioport.h> 33 #include <linux/mm.h> 34 #include <linux/delay.h> 35 #include <linux/pci.h> 36 #include <linux/bitops.h> 37 #include <linux/slab.h> 38 #include <linux/ratelimit.h> 39 40 #include <asm/io.h> 41 #include <asm/irq.h> 42 #include <linux/uaccess.h> 43 44 /* 45 * Semi-public control interfaces 46 */ 47 48 /* 49 * MOXA ioctls 50 */ 51 52 #define MOXA 0x400 53 #define MOXA_SET_OP_MODE (MOXA + 66) 54 #define MOXA_GET_OP_MODE (MOXA + 67) 55 56 #define RS232_MODE 0 57 #define RS485_2WIRE_MODE 1 58 #define RS422_MODE 2 59 #define RS485_4WIRE_MODE 3 60 #define OP_MODE_MASK 3 61 62 /* --------------------------------------------------- */ 63 64 /* 65 * Follow just what Moxa Must chip defines. 66 * 67 * When LCR register (offset 0x03) is written the following value, the Must chip 68 * will enter enhanced mode. And a write to EFR (offset 0x02) bit 6,7 will 69 * change bank. 70 */ 71 #define MOXA_MUST_ENTER_ENHANCED 0xBF 72 73 /* when enhanced mode is enabled, access to general bank register */ 74 #define MOXA_MUST_GDL_REGISTER 0x07 75 #define MOXA_MUST_GDL_MASK 0x7F 76 #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 77 78 #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */ 79 /* enhanced register bank select and enhanced mode setting register */ 80 /* This works only when LCR register equals to 0xBF */ 81 #define MOXA_MUST_EFR_REGISTER 0x02 82 #define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enhanced mode enable */ 83 /* enhanced register bank set 0, 1, 2 */ 84 #define MOXA_MUST_EFR_BANK0 0x00 85 #define MOXA_MUST_EFR_BANK1 0x40 86 #define MOXA_MUST_EFR_BANK2 0x80 87 #define MOXA_MUST_EFR_BANK3 0xC0 88 #define MOXA_MUST_EFR_BANK_MASK 0xC0 89 90 /* set XON1 value register, when LCR=0xBF and change to bank0 */ 91 #define MOXA_MUST_XON1_REGISTER 0x04 92 93 /* set XON2 value register, when LCR=0xBF and change to bank0 */ 94 #define MOXA_MUST_XON2_REGISTER 0x05 95 96 /* set XOFF1 value register, when LCR=0xBF and change to bank0 */ 97 #define MOXA_MUST_XOFF1_REGISTER 0x06 98 99 /* set XOFF2 value register, when LCR=0xBF and change to bank0 */ 100 #define MOXA_MUST_XOFF2_REGISTER 0x07 101 102 #define MOXA_MUST_RBRTL_REGISTER 0x04 103 #define MOXA_MUST_RBRTH_REGISTER 0x05 104 #define MOXA_MUST_RBRTI_REGISTER 0x06 105 #define MOXA_MUST_THRTL_REGISTER 0x07 106 #define MOXA_MUST_ENUM_REGISTER 0x04 107 #define MOXA_MUST_HWID_REGISTER 0x05 108 #define MOXA_MUST_ECR_REGISTER 0x06 109 #define MOXA_MUST_CSR_REGISTER 0x07 110 111 #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */ 112 #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */ 113 114 #define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */ 115 #define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */ 116 #define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */ 117 #define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */ 118 119 #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) 120 121 /* GDA interrupt pending */ 122 #define MOXA_MUST_IIR_GDA 0x1C 123 #define MOXA_MUST_IIR_RDA 0x04 124 #define MOXA_MUST_IIR_RTO 0x0C 125 #define MOXA_MUST_IIR_LSR 0x06 126 127 /* received Xon/Xoff or specical interrupt pending */ 128 #define MOXA_MUST_IIR_XSC 0x10 129 130 /* RTS/CTS change state interrupt pending */ 131 #define MOXA_MUST_IIR_RTSCTS 0x20 132 #define MOXA_MUST_IIR_MASK 0x3E 133 134 #define MOXA_MUST_MCR_XON_FLAG 0x40 135 #define MOXA_MUST_MCR_XON_ANY 0x80 136 #define MOXA_MUST_MCR_TX_XON 0x08 137 138 #define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */ 139 #define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */ 140 #define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */ 141 #define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */ 142 #define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */ 143 #define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */ 144 #define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */ 145 #define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */ 146 #define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */ 147 #define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */ 148 #define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */ 149 150 #define MXSERMAJOR 174 151 152 #define MXSER_BOARDS 4 /* Max. boards */ 153 #define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */ 154 #define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD) 155 #define MXSER_ISR_PASS_LIMIT 100 156 157 #define WAKEUP_CHARS 256 158 159 #define MXSER_BAUD_BASE 921600 160 #define MXSER_CUSTOM_DIVISOR (MXSER_BAUD_BASE * 16) 161 162 #define PCI_DEVICE_ID_POS104UL 0x1044 163 #define PCI_DEVICE_ID_CB108 0x1080 164 #define PCI_DEVICE_ID_CP102UF 0x1023 165 #define PCI_DEVICE_ID_CP112UL 0x1120 166 #define PCI_DEVICE_ID_CB114 0x1142 167 #define PCI_DEVICE_ID_CP114UL 0x1143 168 #define PCI_DEVICE_ID_CB134I 0x1341 169 #define PCI_DEVICE_ID_CP138U 0x1380 170 171 #define MXSER_NPORTS(ddata) ((ddata) & 0xffU) 172 #define MXSER_HIGHBAUD 0x0100 173 174 enum mxser_must_hwid { 175 MOXA_OTHER_UART = 0x00, 176 MOXA_MUST_MU150_HWID = 0x01, 177 MOXA_MUST_MU860_HWID = 0x02, 178 }; 179 180 static const struct { 181 u8 type; 182 u8 fifo_size; 183 u8 rx_high_water; 184 u8 rx_low_water; 185 speed_t max_baud; 186 } Gpci_uart_info[] = { 187 { MOXA_OTHER_UART, 16, 14, 1, 921600 }, 188 { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 }, 189 { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 } 190 }; 191 #define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info) 192 193 194 /* driver_data correspond to the lines in the structure above 195 see also ISA probe function before you change something */ 196 static const struct pci_device_id mxser_pcibrds[] = { 197 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 8 }, 198 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 }, 199 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 2 }, 200 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 4 }, 201 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 4 }, 202 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 2 | MXSER_HIGHBAUD }, 203 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 4 }, 204 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 8 }, 205 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 2 }, 206 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 4 }, 207 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 4 }, 208 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 8 }, /* RC7000 */ 209 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 8 }, 210 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 2 }, 211 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 2 }, 212 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 8 }, 213 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 8 }, 214 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 4 }, 215 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 8 }, 216 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 4 }, 217 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 4 }, 218 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 8 }, 219 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 4 }, 220 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 4 }, 221 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF), .driver_data = 2 }, 222 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP112UL), .driver_data = 2 }, 223 { } 224 }; 225 MODULE_DEVICE_TABLE(pci, mxser_pcibrds); 226 227 static int ttymajor = MXSERMAJOR; 228 229 /* Variables for insmod */ 230 231 MODULE_AUTHOR("Casper Yang"); 232 MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver"); 233 module_param(ttymajor, int, 0); 234 MODULE_LICENSE("GPL"); 235 236 struct mxser_board; 237 238 struct mxser_port { 239 struct tty_port port; 240 struct mxser_board *board; 241 242 unsigned long ioaddr; 243 unsigned long opmode_ioaddr; 244 245 u8 rx_high_water; 246 u8 rx_low_water; 247 int type; /* UART type */ 248 249 unsigned char x_char; /* xon/xoff character */ 250 u8 IER; /* Interrupt Enable Register */ 251 u8 MCR; /* Modem control register */ 252 u8 FCR; /* FIFO control register */ 253 254 bool ldisc_stop_rx; 255 256 struct async_icount icount; /* kernel counters for 4 input interrupts */ 257 unsigned int timeout; 258 259 u8 read_status_mask; 260 u8 ignore_status_mask; 261 u8 xmit_fifo_size; 262 unsigned int xmit_head; 263 unsigned int xmit_tail; 264 unsigned int xmit_cnt; 265 int closing; 266 267 spinlock_t slock; 268 }; 269 270 struct mxser_board { 271 unsigned int idx; 272 unsigned short nports; 273 int irq; 274 unsigned long vector; 275 276 enum mxser_must_hwid must_hwid; 277 speed_t max_baud; 278 279 struct mxser_port ports[]; 280 }; 281 282 static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS); 283 static struct tty_driver *mxvar_sdriver; 284 285 static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set, 286 bool restore_LCR) 287 { 288 u8 oldlcr, efr; 289 290 oldlcr = inb(baseio + UART_LCR); 291 outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR); 292 293 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 294 efr &= ~clear; 295 efr |= set; 296 297 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 298 299 if (restore_LCR) 300 outb(oldlcr, baseio + UART_LCR); 301 302 return oldlcr; 303 } 304 305 static u8 mxser_must_select_bank(unsigned long baseio, u8 bank) 306 { 307 return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank, 308 false); 309 } 310 311 static void mxser_set_must_xon1_value(unsigned long baseio, u8 value) 312 { 313 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); 314 outb(value, baseio + MOXA_MUST_XON1_REGISTER); 315 outb(oldlcr, baseio + UART_LCR); 316 } 317 318 static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value) 319 { 320 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); 321 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER); 322 outb(oldlcr, baseio + UART_LCR); 323 } 324 325 static void mxser_set_must_fifo_value(struct mxser_port *info) 326 { 327 u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1); 328 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER); 329 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER); 330 outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER); 331 outb(oldlcr, info->ioaddr + UART_LCR); 332 } 333 334 static void mxser_set_must_enum_value(unsigned long baseio, u8 value) 335 { 336 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); 337 outb(value, baseio + MOXA_MUST_ENUM_REGISTER); 338 outb(oldlcr, baseio + UART_LCR); 339 } 340 341 static u8 mxser_get_must_hardware_id(unsigned long baseio) 342 { 343 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); 344 u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER); 345 outb(oldlcr, baseio + UART_LCR); 346 347 return id; 348 } 349 350 static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set) 351 { 352 __mxser_must_set_EFR(baseio, clear, set, true); 353 } 354 355 static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable) 356 { 357 mxser_must_set_EFR(baseio, 358 enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE, 359 enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0); 360 } 361 362 static void mxser_must_no_sw_flow_control(unsigned long baseio) 363 { 364 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0); 365 } 366 367 static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable) 368 { 369 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK, 370 enable ? MOXA_MUST_EFR_SF_TX1 : 0); 371 } 372 373 static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable) 374 { 375 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK, 376 enable ? MOXA_MUST_EFR_SF_RX1 : 0); 377 } 378 379 static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io) 380 { 381 u8 oldmcr, hwid; 382 int i; 383 384 outb(0, io + UART_LCR); 385 mxser_must_set_enhance_mode(io, false); 386 oldmcr = inb(io + UART_MCR); 387 outb(0, io + UART_MCR); 388 mxser_set_must_xon1_value(io, 0x11); 389 if ((hwid = inb(io + UART_MCR)) != 0) { 390 outb(oldmcr, io + UART_MCR); 391 return MOXA_OTHER_UART; 392 } 393 394 hwid = mxser_get_must_hardware_id(io); 395 for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */ 396 if (hwid == Gpci_uart_info[i].type) 397 return hwid; 398 399 return MOXA_OTHER_UART; 400 } 401 402 static bool mxser_16550A_or_MUST(struct mxser_port *info) 403 { 404 return info->type == PORT_16550A || info->board->must_hwid; 405 } 406 407 static void mxser_process_txrx_fifo(struct mxser_port *info) 408 { 409 unsigned int i; 410 411 if (info->type == PORT_16450 || info->type == PORT_8250) { 412 info->rx_high_water = 1; 413 info->rx_low_water = 1; 414 info->xmit_fifo_size = 1; 415 return; 416 } 417 418 for (i = 0; i < UART_INFO_NUM; i++) 419 if (info->board->must_hwid == Gpci_uart_info[i].type) { 420 info->rx_low_water = Gpci_uart_info[i].rx_low_water; 421 info->rx_high_water = Gpci_uart_info[i].rx_high_water; 422 info->xmit_fifo_size = Gpci_uart_info[i].fifo_size; 423 break; 424 } 425 } 426 427 static void __mxser_start_tx(struct mxser_port *info) 428 { 429 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); 430 info->IER |= UART_IER_THRI; 431 outb(info->IER, info->ioaddr + UART_IER); 432 } 433 434 static void mxser_start_tx(struct mxser_port *info) 435 { 436 unsigned long flags; 437 438 spin_lock_irqsave(&info->slock, flags); 439 __mxser_start_tx(info); 440 spin_unlock_irqrestore(&info->slock, flags); 441 } 442 443 static void __mxser_stop_tx(struct mxser_port *info) 444 { 445 info->IER &= ~UART_IER_THRI; 446 outb(info->IER, info->ioaddr + UART_IER); 447 } 448 449 static int mxser_carrier_raised(struct tty_port *port) 450 { 451 struct mxser_port *mp = container_of(port, struct mxser_port, port); 452 return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0; 453 } 454 455 static void mxser_dtr_rts(struct tty_port *port, int on) 456 { 457 struct mxser_port *mp = container_of(port, struct mxser_port, port); 458 unsigned long flags; 459 u8 mcr; 460 461 spin_lock_irqsave(&mp->slock, flags); 462 mcr = inb(mp->ioaddr + UART_MCR); 463 if (on) 464 mcr |= UART_MCR_DTR | UART_MCR_RTS; 465 else 466 mcr &= ~(UART_MCR_DTR | UART_MCR_RTS); 467 outb(mcr, mp->ioaddr + UART_MCR); 468 spin_unlock_irqrestore(&mp->slock, flags); 469 } 470 471 static int mxser_set_baud(struct tty_struct *tty, speed_t newspd) 472 { 473 struct mxser_port *info = tty->driver_data; 474 unsigned int quot = 0, baud; 475 unsigned char cval; 476 u64 timeout; 477 478 if (newspd > info->board->max_baud) 479 return -1; 480 481 if (newspd == 134) { 482 quot = 2 * MXSER_BAUD_BASE / 269; 483 tty_encode_baud_rate(tty, 134, 134); 484 } else if (newspd) { 485 quot = MXSER_BAUD_BASE / newspd; 486 if (quot == 0) 487 quot = 1; 488 baud = MXSER_BAUD_BASE / quot; 489 tty_encode_baud_rate(tty, baud, baud); 490 } else { 491 quot = 0; 492 } 493 494 /* 495 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the 496 * u64 domain 497 */ 498 timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot; 499 do_div(timeout, MXSER_BAUD_BASE); 500 info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */ 501 502 if (quot) { 503 info->MCR |= UART_MCR_DTR; 504 outb(info->MCR, info->ioaddr + UART_MCR); 505 } else { 506 info->MCR &= ~UART_MCR_DTR; 507 outb(info->MCR, info->ioaddr + UART_MCR); 508 return 0; 509 } 510 511 cval = inb(info->ioaddr + UART_LCR); 512 513 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */ 514 515 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */ 516 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */ 517 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */ 518 519 #ifdef BOTHER 520 if (C_BAUD(tty) == BOTHER) { 521 quot = MXSER_BAUD_BASE % newspd; 522 quot *= 8; 523 if (quot % newspd > newspd / 2) { 524 quot /= newspd; 525 quot++; 526 } else 527 quot /= newspd; 528 529 mxser_set_must_enum_value(info->ioaddr, quot); 530 } else 531 #endif 532 mxser_set_must_enum_value(info->ioaddr, 0); 533 534 return 0; 535 } 536 537 static void mxser_handle_cts(struct tty_struct *tty, struct mxser_port *info, 538 u8 msr) 539 { 540 bool cts = msr & UART_MSR_CTS; 541 542 if (tty->hw_stopped) { 543 if (cts) { 544 tty->hw_stopped = 0; 545 546 if (!mxser_16550A_or_MUST(info)) 547 __mxser_start_tx(info); 548 tty_wakeup(tty); 549 } 550 return; 551 } else if (cts) 552 return; 553 554 tty->hw_stopped = 1; 555 if (!mxser_16550A_or_MUST(info)) 556 __mxser_stop_tx(info); 557 } 558 559 /* 560 * This routine is called to set the UART divisor registers to match 561 * the specified baud rate for a serial port. 562 */ 563 static void mxser_change_speed(struct tty_struct *tty, struct ktermios *old_termios) 564 { 565 struct mxser_port *info = tty->driver_data; 566 unsigned cflag, cval; 567 568 cflag = tty->termios.c_cflag; 569 570 if (mxser_set_baud(tty, tty_get_baud_rate(tty))) { 571 /* Use previous rate on a failure */ 572 if (old_termios) { 573 speed_t baud = tty_termios_baud_rate(old_termios); 574 tty_encode_baud_rate(tty, baud, baud); 575 } 576 } 577 578 /* byte size and parity */ 579 switch (cflag & CSIZE) { 580 default: 581 case CS5: 582 cval = UART_LCR_WLEN5; 583 break; 584 case CS6: 585 cval = UART_LCR_WLEN6; 586 break; 587 case CS7: 588 cval = UART_LCR_WLEN7; 589 break; 590 case CS8: 591 cval = UART_LCR_WLEN8; 592 break; 593 } 594 595 if (cflag & CSTOPB) 596 cval |= UART_LCR_STOP; 597 if (cflag & PARENB) 598 cval |= UART_LCR_PARITY; 599 if (!(cflag & PARODD)) 600 cval |= UART_LCR_EPAR; 601 if (cflag & CMSPAR) 602 cval |= UART_LCR_SPAR; 603 604 info->FCR = 0; 605 if (info->board->must_hwid) { 606 info->FCR |= UART_FCR_ENABLE_FIFO | 607 MOXA_MUST_FCR_GDA_MODE_ENABLE; 608 mxser_set_must_fifo_value(info); 609 } else if (info->type != PORT_8250 && info->type != PORT_16450) { 610 info->FCR |= UART_FCR_ENABLE_FIFO; 611 switch (info->rx_high_water) { 612 case 1: 613 info->FCR |= UART_FCR_TRIGGER_1; 614 break; 615 case 4: 616 info->FCR |= UART_FCR_TRIGGER_4; 617 break; 618 case 8: 619 info->FCR |= UART_FCR_TRIGGER_8; 620 break; 621 default: 622 info->FCR |= UART_FCR_TRIGGER_14; 623 break; 624 } 625 } 626 627 /* CTS flow control flag and modem status interrupts */ 628 info->IER &= ~UART_IER_MSI; 629 info->MCR &= ~UART_MCR_AFE; 630 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS); 631 if (cflag & CRTSCTS) { 632 info->IER |= UART_IER_MSI; 633 if (mxser_16550A_or_MUST(info)) { 634 info->MCR |= UART_MCR_AFE; 635 } else { 636 mxser_handle_cts(tty, info, 637 inb(info->ioaddr + UART_MSR)); 638 } 639 } 640 outb(info->MCR, info->ioaddr + UART_MCR); 641 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL); 642 if (~cflag & CLOCAL) 643 info->IER |= UART_IER_MSI; 644 outb(info->IER, info->ioaddr + UART_IER); 645 646 /* 647 * Set up parity check flag 648 */ 649 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 650 if (I_INPCK(tty)) 651 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 652 if (I_BRKINT(tty) || I_PARMRK(tty)) 653 info->read_status_mask |= UART_LSR_BI; 654 655 info->ignore_status_mask = 0; 656 657 if (I_IGNBRK(tty)) { 658 info->ignore_status_mask |= UART_LSR_BI; 659 info->read_status_mask |= UART_LSR_BI; 660 /* 661 * If we're ignore parity and break indicators, ignore 662 * overruns too. (For real raw support). 663 */ 664 if (I_IGNPAR(tty)) { 665 info->ignore_status_mask |= 666 UART_LSR_OE | 667 UART_LSR_PE | 668 UART_LSR_FE; 669 info->read_status_mask |= 670 UART_LSR_OE | 671 UART_LSR_PE | 672 UART_LSR_FE; 673 } 674 } 675 if (info->board->must_hwid) { 676 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty)); 677 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty)); 678 mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty)); 679 mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty)); 680 } 681 682 683 outb(info->FCR, info->ioaddr + UART_FCR); 684 outb(cval, info->ioaddr + UART_LCR); 685 } 686 687 static void mxser_check_modem_status(struct tty_struct *tty, 688 struct mxser_port *port, int status) 689 { 690 /* update input line counters */ 691 if (status & UART_MSR_TERI) 692 port->icount.rng++; 693 if (status & UART_MSR_DDSR) 694 port->icount.dsr++; 695 if (status & UART_MSR_DDCD) 696 port->icount.dcd++; 697 if (status & UART_MSR_DCTS) 698 port->icount.cts++; 699 wake_up_interruptible(&port->port.delta_msr_wait); 700 701 if (tty_port_check_carrier(&port->port) && (status & UART_MSR_DDCD)) { 702 if (status & UART_MSR_DCD) 703 wake_up_interruptible(&port->port.open_wait); 704 } 705 706 if (tty_port_cts_enabled(&port->port)) 707 mxser_handle_cts(tty, port, status); 708 } 709 710 static void mxser_disable_and_clear_FIFO(struct mxser_port *info) 711 { 712 u8 fcr = UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT; 713 714 if (info->board->must_hwid) 715 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; 716 717 outb(fcr, info->ioaddr + UART_FCR); 718 } 719 720 static int mxser_activate(struct tty_port *port, struct tty_struct *tty) 721 { 722 struct mxser_port *info = container_of(port, struct mxser_port, port); 723 unsigned long page; 724 unsigned long flags; 725 726 page = __get_free_page(GFP_KERNEL); 727 if (!page) 728 return -ENOMEM; 729 730 spin_lock_irqsave(&info->slock, flags); 731 732 if (!info->type) { 733 set_bit(TTY_IO_ERROR, &tty->flags); 734 free_page(page); 735 spin_unlock_irqrestore(&info->slock, flags); 736 return 0; 737 } 738 info->port.xmit_buf = (unsigned char *) page; 739 740 /* 741 * Clear the FIFO buffers and disable them 742 * (they will be reenabled in mxser_change_speed()) 743 */ 744 mxser_disable_and_clear_FIFO(info); 745 746 /* 747 * At this point there's no way the LSR could still be 0xFF; 748 * if it is, then bail out, because there's likely no UART 749 * here. 750 */ 751 if (inb(info->ioaddr + UART_LSR) == 0xff) { 752 spin_unlock_irqrestore(&info->slock, flags); 753 if (capable(CAP_SYS_ADMIN)) { 754 set_bit(TTY_IO_ERROR, &tty->flags); 755 return 0; 756 } else 757 return -ENODEV; 758 } 759 760 /* 761 * Clear the interrupt registers. 762 */ 763 (void) inb(info->ioaddr + UART_LSR); 764 (void) inb(info->ioaddr + UART_RX); 765 (void) inb(info->ioaddr + UART_IIR); 766 (void) inb(info->ioaddr + UART_MSR); 767 768 /* 769 * Now, initialize the UART 770 */ 771 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */ 772 info->MCR = UART_MCR_DTR | UART_MCR_RTS; 773 outb(info->MCR, info->ioaddr + UART_MCR); 774 775 /* 776 * Finally, enable interrupts 777 */ 778 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; 779 780 if (info->board->must_hwid) 781 info->IER |= MOXA_MUST_IER_EGDAI; 782 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */ 783 784 /* 785 * And clear the interrupt registers again for luck. 786 */ 787 (void) inb(info->ioaddr + UART_LSR); 788 (void) inb(info->ioaddr + UART_RX); 789 (void) inb(info->ioaddr + UART_IIR); 790 (void) inb(info->ioaddr + UART_MSR); 791 792 clear_bit(TTY_IO_ERROR, &tty->flags); 793 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; 794 795 /* 796 * and set the speed of the serial port 797 */ 798 mxser_change_speed(tty, NULL); 799 spin_unlock_irqrestore(&info->slock, flags); 800 801 return 0; 802 } 803 804 /* 805 * This routine will shutdown a serial port 806 */ 807 static void mxser_shutdown_port(struct tty_port *port) 808 { 809 struct mxser_port *info = container_of(port, struct mxser_port, port); 810 unsigned long flags; 811 812 spin_lock_irqsave(&info->slock, flags); 813 814 /* 815 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq 816 * here so the queue might never be waken up 817 */ 818 wake_up_interruptible(&info->port.delta_msr_wait); 819 820 /* 821 * Free the xmit buffer, if necessary 822 */ 823 if (info->port.xmit_buf) { 824 free_page((unsigned long) info->port.xmit_buf); 825 info->port.xmit_buf = NULL; 826 } 827 828 info->IER = 0; 829 outb(0x00, info->ioaddr + UART_IER); 830 831 /* clear Rx/Tx FIFO's */ 832 mxser_disable_and_clear_FIFO(info); 833 834 /* read data port to reset things */ 835 (void) inb(info->ioaddr + UART_RX); 836 837 838 if (info->board->must_hwid) 839 mxser_must_no_sw_flow_control(info->ioaddr); 840 841 spin_unlock_irqrestore(&info->slock, flags); 842 } 843 844 /* 845 * This routine is called whenever a serial port is opened. It 846 * enables interrupts for a serial port, linking in its async structure into 847 * the IRQ chain. It also performs the serial-specific 848 * initialization for the tty structure. 849 */ 850 static int mxser_open(struct tty_struct *tty, struct file *filp) 851 { 852 struct tty_port *tport = tty->port; 853 struct mxser_port *port = container_of(tport, struct mxser_port, port); 854 855 tty->driver_data = port; 856 857 return tty_port_open(tport, tty, filp); 858 } 859 860 static void mxser_flush_buffer(struct tty_struct *tty) 861 { 862 struct mxser_port *info = tty->driver_data; 863 unsigned long flags; 864 865 866 spin_lock_irqsave(&info->slock, flags); 867 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; 868 869 outb(info->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 870 info->ioaddr + UART_FCR); 871 872 spin_unlock_irqrestore(&info->slock, flags); 873 874 tty_wakeup(tty); 875 } 876 877 878 static void mxser_close_port(struct tty_port *port) 879 { 880 struct mxser_port *info = container_of(port, struct mxser_port, port); 881 unsigned long timeout; 882 /* 883 * At this point we stop accepting input. To do this, we 884 * disable the receive line status interrupts, and tell the 885 * interrupt driver to stop checking the data ready bit in the 886 * line status register. 887 */ 888 info->IER &= ~UART_IER_RLSI; 889 if (info->board->must_hwid) 890 info->IER &= ~MOXA_MUST_RECV_ISR; 891 892 outb(info->IER, info->ioaddr + UART_IER); 893 /* 894 * Before we drop DTR, make sure the UART transmitter 895 * has completely drained; this is especially 896 * important if there is a transmit FIFO! 897 */ 898 timeout = jiffies + HZ; 899 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) { 900 schedule_timeout_interruptible(5); 901 if (time_after(jiffies, timeout)) 902 break; 903 } 904 } 905 906 /* 907 * This routine is called when the serial port gets closed. First, we 908 * wait for the last remaining data to be sent. Then, we unlink its 909 * async structure from the interrupt chain if necessary, and we free 910 * that IRQ if nothing is left in the chain. 911 */ 912 static void mxser_close(struct tty_struct *tty, struct file *filp) 913 { 914 struct mxser_port *info = tty->driver_data; 915 struct tty_port *port = &info->port; 916 917 if (info == NULL) 918 return; 919 if (tty_port_close_start(port, tty, filp) == 0) 920 return; 921 info->closing = 1; 922 mutex_lock(&port->mutex); 923 mxser_close_port(port); 924 mxser_flush_buffer(tty); 925 if (tty_port_initialized(port) && C_HUPCL(tty)) 926 tty_port_lower_dtr_rts(port); 927 mxser_shutdown_port(port); 928 tty_port_set_initialized(port, 0); 929 mutex_unlock(&port->mutex); 930 info->closing = 0; 931 /* Right now the tty_port set is done outside of the close_end helper 932 as we don't yet have everyone using refcounts */ 933 tty_port_close_end(port, tty); 934 tty_port_tty_set(port, NULL); 935 } 936 937 static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count) 938 { 939 int c, total = 0; 940 struct mxser_port *info = tty->driver_data; 941 unsigned long flags; 942 943 if (!info->port.xmit_buf) 944 return 0; 945 946 while (1) { 947 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, 948 SERIAL_XMIT_SIZE - info->xmit_head)); 949 if (c <= 0) 950 break; 951 952 memcpy(info->port.xmit_buf + info->xmit_head, buf, c); 953 spin_lock_irqsave(&info->slock, flags); 954 info->xmit_head = (info->xmit_head + c) & 955 (SERIAL_XMIT_SIZE - 1); 956 info->xmit_cnt += c; 957 spin_unlock_irqrestore(&info->slock, flags); 958 959 buf += c; 960 count -= c; 961 total += c; 962 } 963 964 if (info->xmit_cnt && !tty->flow.stopped) 965 if (!tty->hw_stopped || mxser_16550A_or_MUST(info)) 966 mxser_start_tx(info); 967 968 return total; 969 } 970 971 static int mxser_put_char(struct tty_struct *tty, unsigned char ch) 972 { 973 struct mxser_port *info = tty->driver_data; 974 unsigned long flags; 975 976 if (!info->port.xmit_buf) 977 return 0; 978 979 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1) 980 return 0; 981 982 spin_lock_irqsave(&info->slock, flags); 983 info->port.xmit_buf[info->xmit_head++] = ch; 984 info->xmit_head &= SERIAL_XMIT_SIZE - 1; 985 info->xmit_cnt++; 986 spin_unlock_irqrestore(&info->slock, flags); 987 988 return 1; 989 } 990 991 992 static void mxser_flush_chars(struct tty_struct *tty) 993 { 994 struct mxser_port *info = tty->driver_data; 995 996 if (!info->xmit_cnt || tty->flow.stopped || !info->port.xmit_buf || 997 (tty->hw_stopped && !mxser_16550A_or_MUST(info))) 998 return; 999 1000 mxser_start_tx(info); 1001 } 1002 1003 static unsigned int mxser_write_room(struct tty_struct *tty) 1004 { 1005 struct mxser_port *info = tty->driver_data; 1006 int ret; 1007 1008 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1; 1009 return ret < 0 ? 0 : ret; 1010 } 1011 1012 static unsigned int mxser_chars_in_buffer(struct tty_struct *tty) 1013 { 1014 struct mxser_port *info = tty->driver_data; 1015 return info->xmit_cnt; 1016 } 1017 1018 /* 1019 * ------------------------------------------------------------ 1020 * friends of mxser_ioctl() 1021 * ------------------------------------------------------------ 1022 */ 1023 static int mxser_get_serial_info(struct tty_struct *tty, 1024 struct serial_struct *ss) 1025 { 1026 struct mxser_port *info = tty->driver_data; 1027 struct tty_port *port = &info->port; 1028 unsigned int closing_wait, close_delay; 1029 1030 mutex_lock(&port->mutex); 1031 1032 close_delay = jiffies_to_msecs(info->port.close_delay) / 10; 1033 closing_wait = info->port.closing_wait; 1034 if (closing_wait != ASYNC_CLOSING_WAIT_NONE) 1035 closing_wait = jiffies_to_msecs(closing_wait) / 10; 1036 1037 ss->type = info->type; 1038 ss->line = tty->index; 1039 ss->port = info->ioaddr; 1040 ss->irq = info->board->irq; 1041 ss->flags = info->port.flags; 1042 ss->baud_base = MXSER_BAUD_BASE; 1043 ss->close_delay = close_delay; 1044 ss->closing_wait = closing_wait; 1045 ss->custom_divisor = MXSER_CUSTOM_DIVISOR, 1046 mutex_unlock(&port->mutex); 1047 return 0; 1048 } 1049 1050 static int mxser_set_serial_info(struct tty_struct *tty, 1051 struct serial_struct *ss) 1052 { 1053 struct mxser_port *info = tty->driver_data; 1054 struct tty_port *port = &info->port; 1055 speed_t baud; 1056 unsigned long sl_flags; 1057 unsigned int old_speed, close_delay, closing_wait; 1058 int retval = 0; 1059 1060 if (tty_io_error(tty)) 1061 return -EIO; 1062 1063 mutex_lock(&port->mutex); 1064 1065 if (ss->irq != info->board->irq || 1066 ss->port != info->ioaddr) { 1067 mutex_unlock(&port->mutex); 1068 return -EINVAL; 1069 } 1070 1071 old_speed = port->flags & ASYNC_SPD_MASK; 1072 1073 close_delay = msecs_to_jiffies(ss->close_delay * 10); 1074 closing_wait = ss->closing_wait; 1075 if (closing_wait != ASYNC_CLOSING_WAIT_NONE) 1076 closing_wait = msecs_to_jiffies(closing_wait * 10); 1077 1078 if (!capable(CAP_SYS_ADMIN)) { 1079 if ((ss->baud_base != MXSER_BAUD_BASE) || 1080 (close_delay != port->close_delay) || 1081 (closing_wait != port->closing_wait) || 1082 ((ss->flags & ~ASYNC_USR_MASK) != (port->flags & ~ASYNC_USR_MASK))) { 1083 mutex_unlock(&port->mutex); 1084 return -EPERM; 1085 } 1086 port->flags = (port->flags & ~ASYNC_USR_MASK) | 1087 (ss->flags & ASYNC_USR_MASK); 1088 } else { 1089 /* 1090 * OK, past this point, all the error checking has been done. 1091 * At this point, we start making changes..... 1092 */ 1093 port->flags = ((port->flags & ~ASYNC_FLAGS) | 1094 (ss->flags & ASYNC_FLAGS)); 1095 port->close_delay = close_delay; 1096 port->closing_wait = closing_wait; 1097 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST && 1098 (ss->baud_base != MXSER_BAUD_BASE || 1099 ss->custom_divisor != 1100 MXSER_CUSTOM_DIVISOR)) { 1101 if (ss->custom_divisor == 0) { 1102 mutex_unlock(&port->mutex); 1103 return -EINVAL; 1104 } 1105 baud = ss->baud_base / ss->custom_divisor; 1106 tty_encode_baud_rate(tty, baud, baud); 1107 } 1108 1109 info->type = ss->type; 1110 1111 mxser_process_txrx_fifo(info); 1112 } 1113 1114 if (tty_port_initialized(port)) { 1115 if (old_speed != (port->flags & ASYNC_SPD_MASK)) { 1116 spin_lock_irqsave(&info->slock, sl_flags); 1117 mxser_change_speed(tty, NULL); 1118 spin_unlock_irqrestore(&info->slock, sl_flags); 1119 } 1120 } else { 1121 retval = mxser_activate(port, tty); 1122 if (retval == 0) 1123 tty_port_set_initialized(port, 1); 1124 } 1125 mutex_unlock(&port->mutex); 1126 return retval; 1127 } 1128 1129 /* 1130 * mxser_get_lsr_info - get line status register info 1131 * 1132 * Purpose: Let user call ioctl() to get info when the UART physically 1133 * is emptied. On bus types like RS485, the transmitter must 1134 * release the bus after transmitting. This must be done when 1135 * the transmit shift register is empty, not be done when the 1136 * transmit holding register is empty. This functionality 1137 * allows an RS485 driver to be written in user space. 1138 */ 1139 static int mxser_get_lsr_info(struct mxser_port *info, 1140 unsigned int __user *value) 1141 { 1142 unsigned char status; 1143 unsigned int result; 1144 unsigned long flags; 1145 1146 spin_lock_irqsave(&info->slock, flags); 1147 status = inb(info->ioaddr + UART_LSR); 1148 spin_unlock_irqrestore(&info->slock, flags); 1149 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0); 1150 return put_user(result, value); 1151 } 1152 1153 static int mxser_tiocmget(struct tty_struct *tty) 1154 { 1155 struct mxser_port *info = tty->driver_data; 1156 unsigned char control, status; 1157 unsigned long flags; 1158 1159 if (tty_io_error(tty)) 1160 return -EIO; 1161 1162 spin_lock_irqsave(&info->slock, flags); 1163 control = info->MCR; 1164 status = inb(info->ioaddr + UART_MSR); 1165 if (status & UART_MSR_ANY_DELTA) 1166 mxser_check_modem_status(tty, info, status); 1167 spin_unlock_irqrestore(&info->slock, flags); 1168 1169 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) | 1170 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) | 1171 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) | 1172 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) | 1173 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) | 1174 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0); 1175 } 1176 1177 static int mxser_tiocmset(struct tty_struct *tty, 1178 unsigned int set, unsigned int clear) 1179 { 1180 struct mxser_port *info = tty->driver_data; 1181 unsigned long flags; 1182 1183 if (tty_io_error(tty)) 1184 return -EIO; 1185 1186 spin_lock_irqsave(&info->slock, flags); 1187 1188 if (set & TIOCM_RTS) 1189 info->MCR |= UART_MCR_RTS; 1190 if (set & TIOCM_DTR) 1191 info->MCR |= UART_MCR_DTR; 1192 1193 if (clear & TIOCM_RTS) 1194 info->MCR &= ~UART_MCR_RTS; 1195 if (clear & TIOCM_DTR) 1196 info->MCR &= ~UART_MCR_DTR; 1197 1198 outb(info->MCR, info->ioaddr + UART_MCR); 1199 spin_unlock_irqrestore(&info->slock, flags); 1200 return 0; 1201 } 1202 1203 static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg, 1204 struct async_icount *cprev) 1205 { 1206 struct async_icount cnow; 1207 unsigned long flags; 1208 int ret; 1209 1210 spin_lock_irqsave(&info->slock, flags); 1211 cnow = info->icount; /* atomic copy */ 1212 spin_unlock_irqrestore(&info->slock, flags); 1213 1214 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) || 1215 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) || 1216 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) || 1217 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts)); 1218 1219 *cprev = cnow; 1220 1221 return ret; 1222 } 1223 1224 /* We should likely switch to TIOCGRS485/TIOCSRS485. */ 1225 static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set, 1226 int __user *u_opmode) 1227 { 1228 int opmode, p = index % 4; 1229 int shiftbit = p * 2; 1230 u8 val; 1231 1232 if (port->board->must_hwid != MOXA_MUST_MU860_HWID) 1233 return -EFAULT; 1234 1235 if (set) { 1236 if (get_user(opmode, u_opmode)) 1237 return -EFAULT; 1238 1239 if (opmode & ~OP_MODE_MASK) 1240 return -EINVAL; 1241 1242 spin_lock_irq(&port->slock); 1243 val = inb(port->opmode_ioaddr); 1244 val &= ~(OP_MODE_MASK << shiftbit); 1245 val |= (opmode << shiftbit); 1246 outb(val, port->opmode_ioaddr); 1247 spin_unlock_irq(&port->slock); 1248 1249 return 0; 1250 } 1251 1252 spin_lock_irq(&port->slock); 1253 opmode = inb(port->opmode_ioaddr) >> shiftbit; 1254 spin_unlock_irq(&port->slock); 1255 1256 return put_user(opmode & OP_MODE_MASK, u_opmode); 1257 } 1258 1259 static int mxser_ioctl(struct tty_struct *tty, 1260 unsigned int cmd, unsigned long arg) 1261 { 1262 struct mxser_port *info = tty->driver_data; 1263 struct async_icount cnow; 1264 unsigned long flags; 1265 void __user *argp = (void __user *)arg; 1266 1267 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) 1268 return mxser_ioctl_op_mode(info, tty->index, 1269 cmd == MOXA_SET_OP_MODE, argp); 1270 1271 if (cmd != TIOCMIWAIT && tty_io_error(tty)) 1272 return -EIO; 1273 1274 switch (cmd) { 1275 case TIOCSERGETLSR: /* Get line status register */ 1276 return mxser_get_lsr_info(info, argp); 1277 /* 1278 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change 1279 * - mask passed in arg for lines of interest 1280 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) 1281 * Caller should use TIOCGICOUNT to see which one it was 1282 */ 1283 case TIOCMIWAIT: 1284 spin_lock_irqsave(&info->slock, flags); 1285 cnow = info->icount; /* note the counters on entry */ 1286 spin_unlock_irqrestore(&info->slock, flags); 1287 1288 return wait_event_interruptible(info->port.delta_msr_wait, 1289 mxser_cflags_changed(info, arg, &cnow)); 1290 default: 1291 return -ENOIOCTLCMD; 1292 } 1293 return 0; 1294 } 1295 1296 /* 1297 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) 1298 * Return: write counters to the user passed counter struct 1299 * NB: both 1->0 and 0->1 transitions are counted except for 1300 * RI where only 0->1 is counted. 1301 */ 1302 1303 static int mxser_get_icount(struct tty_struct *tty, 1304 struct serial_icounter_struct *icount) 1305 1306 { 1307 struct mxser_port *info = tty->driver_data; 1308 struct async_icount cnow; 1309 unsigned long flags; 1310 1311 spin_lock_irqsave(&info->slock, flags); 1312 cnow = info->icount; 1313 spin_unlock_irqrestore(&info->slock, flags); 1314 1315 icount->frame = cnow.frame; 1316 icount->brk = cnow.brk; 1317 icount->overrun = cnow.overrun; 1318 icount->buf_overrun = cnow.buf_overrun; 1319 icount->parity = cnow.parity; 1320 icount->rx = cnow.rx; 1321 icount->tx = cnow.tx; 1322 icount->cts = cnow.cts; 1323 icount->dsr = cnow.dsr; 1324 icount->rng = cnow.rng; 1325 icount->dcd = cnow.dcd; 1326 return 0; 1327 } 1328 1329 static void mxser_stoprx(struct tty_struct *tty) 1330 { 1331 struct mxser_port *info = tty->driver_data; 1332 1333 info->ldisc_stop_rx = true; 1334 if (I_IXOFF(tty)) { 1335 if (info->board->must_hwid) { 1336 info->IER &= ~MOXA_MUST_RECV_ISR; 1337 outb(info->IER, info->ioaddr + UART_IER); 1338 } else { 1339 info->x_char = STOP_CHAR(tty); 1340 outb(0, info->ioaddr + UART_IER); 1341 info->IER |= UART_IER_THRI; 1342 outb(info->IER, info->ioaddr + UART_IER); 1343 } 1344 } 1345 1346 if (C_CRTSCTS(tty)) { 1347 info->MCR &= ~UART_MCR_RTS; 1348 outb(info->MCR, info->ioaddr + UART_MCR); 1349 } 1350 } 1351 1352 /* 1353 * This routine is called by the upper-layer tty layer to signal that 1354 * incoming characters should be throttled. 1355 */ 1356 static void mxser_throttle(struct tty_struct *tty) 1357 { 1358 mxser_stoprx(tty); 1359 } 1360 1361 static void mxser_unthrottle(struct tty_struct *tty) 1362 { 1363 struct mxser_port *info = tty->driver_data; 1364 1365 /* startrx */ 1366 info->ldisc_stop_rx = false; 1367 if (I_IXOFF(tty)) { 1368 if (info->x_char) 1369 info->x_char = 0; 1370 else { 1371 if (info->board->must_hwid) { 1372 info->IER |= MOXA_MUST_RECV_ISR; 1373 outb(info->IER, info->ioaddr + UART_IER); 1374 } else { 1375 info->x_char = START_CHAR(tty); 1376 outb(0, info->ioaddr + UART_IER); 1377 info->IER |= UART_IER_THRI; 1378 outb(info->IER, info->ioaddr + UART_IER); 1379 } 1380 } 1381 } 1382 1383 if (C_CRTSCTS(tty)) { 1384 info->MCR |= UART_MCR_RTS; 1385 outb(info->MCR, info->ioaddr + UART_MCR); 1386 } 1387 } 1388 1389 /* 1390 * mxser_stop() and mxser_start() 1391 * 1392 * This routines are called before setting or resetting tty->flow.stopped. 1393 * They enable or disable transmitter interrupts, as necessary. 1394 */ 1395 static void mxser_stop(struct tty_struct *tty) 1396 { 1397 struct mxser_port *info = tty->driver_data; 1398 unsigned long flags; 1399 1400 spin_lock_irqsave(&info->slock, flags); 1401 if (info->IER & UART_IER_THRI) 1402 __mxser_stop_tx(info); 1403 spin_unlock_irqrestore(&info->slock, flags); 1404 } 1405 1406 static void mxser_start(struct tty_struct *tty) 1407 { 1408 struct mxser_port *info = tty->driver_data; 1409 unsigned long flags; 1410 1411 spin_lock_irqsave(&info->slock, flags); 1412 if (info->xmit_cnt && info->port.xmit_buf) 1413 __mxser_start_tx(info); 1414 spin_unlock_irqrestore(&info->slock, flags); 1415 } 1416 1417 static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios) 1418 { 1419 struct mxser_port *info = tty->driver_data; 1420 unsigned long flags; 1421 1422 spin_lock_irqsave(&info->slock, flags); 1423 mxser_change_speed(tty, old_termios); 1424 spin_unlock_irqrestore(&info->slock, flags); 1425 1426 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) { 1427 tty->hw_stopped = 0; 1428 mxser_start(tty); 1429 } 1430 1431 /* Handle sw stopped */ 1432 if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) { 1433 tty->flow.stopped = 0; 1434 1435 if (info->board->must_hwid) { 1436 spin_lock_irqsave(&info->slock, flags); 1437 mxser_must_set_rx_sw_flow_control(info->ioaddr, false); 1438 spin_unlock_irqrestore(&info->slock, flags); 1439 } 1440 1441 mxser_start(tty); 1442 } 1443 } 1444 1445 /* 1446 * mxser_wait_until_sent() --- wait until the transmitter is empty 1447 */ 1448 static void mxser_wait_until_sent(struct tty_struct *tty, int timeout) 1449 { 1450 struct mxser_port *info = tty->driver_data; 1451 unsigned long orig_jiffies, char_time; 1452 unsigned long flags; 1453 int lsr; 1454 1455 if (info->type == PORT_UNKNOWN) 1456 return; 1457 1458 if (info->xmit_fifo_size == 0) 1459 return; /* Just in case.... */ 1460 1461 orig_jiffies = jiffies; 1462 /* 1463 * Set the check interval to be 1/5 of the estimated time to 1464 * send a single character, and make it at least 1. The check 1465 * interval should also be less than the timeout. 1466 * 1467 * Note: we have to use pretty tight timings here to satisfy 1468 * the NIST-PCTS. 1469 */ 1470 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size; 1471 char_time = char_time / 5; 1472 if (char_time == 0) 1473 char_time = 1; 1474 if (timeout && timeout < char_time) 1475 char_time = timeout; 1476 /* 1477 * If the transmitter hasn't cleared in twice the approximate 1478 * amount of time to send the entire FIFO, it probably won't 1479 * ever clear. This assumes the UART isn't doing flow 1480 * control, which is currently the case. Hence, if it ever 1481 * takes longer than info->timeout, this is probably due to a 1482 * UART bug of some kind. So, we clamp the timeout parameter at 1483 * 2*info->timeout. 1484 */ 1485 if (!timeout || timeout > 2 * info->timeout) 1486 timeout = 2 * info->timeout; 1487 1488 spin_lock_irqsave(&info->slock, flags); 1489 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) { 1490 spin_unlock_irqrestore(&info->slock, flags); 1491 schedule_timeout_interruptible(char_time); 1492 spin_lock_irqsave(&info->slock, flags); 1493 if (signal_pending(current)) 1494 break; 1495 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 1496 break; 1497 } 1498 spin_unlock_irqrestore(&info->slock, flags); 1499 set_current_state(TASK_RUNNING); 1500 } 1501 1502 /* 1503 * This routine is called by tty_hangup() when a hangup is signaled. 1504 */ 1505 static void mxser_hangup(struct tty_struct *tty) 1506 { 1507 struct mxser_port *info = tty->driver_data; 1508 1509 mxser_flush_buffer(tty); 1510 tty_port_hangup(&info->port); 1511 } 1512 1513 /* 1514 * mxser_rs_break() --- routine which turns the break handling on or off 1515 */ 1516 static int mxser_rs_break(struct tty_struct *tty, int break_state) 1517 { 1518 struct mxser_port *info = tty->driver_data; 1519 unsigned long flags; 1520 u8 lcr; 1521 1522 spin_lock_irqsave(&info->slock, flags); 1523 lcr = inb(info->ioaddr + UART_LCR); 1524 if (break_state == -1) 1525 lcr |= UART_LCR_SBC; 1526 else 1527 lcr &= ~UART_LCR_SBC; 1528 outb(lcr, info->ioaddr + UART_LCR); 1529 spin_unlock_irqrestore(&info->slock, flags); 1530 1531 return 0; 1532 } 1533 1534 static bool mxser_receive_chars_new(struct tty_struct *tty, 1535 struct mxser_port *port, u8 status) 1536 { 1537 enum mxser_must_hwid hwid = port->board->must_hwid; 1538 u8 gdl; 1539 1540 if (hwid == MOXA_OTHER_UART) 1541 return false; 1542 if (status & (UART_LSR_BRK_ERROR_BITS | MOXA_MUST_LSR_RERR)) 1543 return false; 1544 1545 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER); 1546 if (hwid == MOXA_MUST_MU150_HWID) 1547 gdl &= MOXA_MUST_GDL_MASK; 1548 1549 if (gdl >= tty->receive_room && !port->ldisc_stop_rx) 1550 mxser_stoprx(tty); 1551 1552 while (gdl--) { 1553 u8 ch = inb(port->ioaddr + UART_RX); 1554 tty_insert_flip_char(&port->port, ch, 0); 1555 } 1556 1557 return true; 1558 } 1559 1560 static u8 mxser_receive_chars_old(struct tty_struct *tty, 1561 struct mxser_port *port, u8 status) 1562 { 1563 enum mxser_must_hwid hwid = port->board->must_hwid; 1564 int recv_room = tty->receive_room; 1565 int ignored = 0; 1566 int max = 256; 1567 int cnt = 0; 1568 u8 ch; 1569 1570 do { 1571 if (max-- < 0) 1572 break; 1573 1574 ch = inb(port->ioaddr + UART_RX); 1575 if (hwid && (status & UART_LSR_OE)) 1576 outb(port->FCR | UART_FCR_CLEAR_RCVR, 1577 port->ioaddr + UART_FCR); 1578 status &= port->read_status_mask; 1579 if (status & port->ignore_status_mask) { 1580 if (++ignored > 100) 1581 break; 1582 } else { 1583 char flag = 0; 1584 if (status & UART_LSR_BRK_ERROR_BITS) { 1585 if (status & UART_LSR_BI) { 1586 flag = TTY_BREAK; 1587 port->icount.brk++; 1588 1589 if (port->port.flags & ASYNC_SAK) 1590 do_SAK(tty); 1591 } else if (status & UART_LSR_PE) { 1592 flag = TTY_PARITY; 1593 port->icount.parity++; 1594 } else if (status & UART_LSR_FE) { 1595 flag = TTY_FRAME; 1596 port->icount.frame++; 1597 } else if (status & UART_LSR_OE) { 1598 flag = TTY_OVERRUN; 1599 port->icount.overrun++; 1600 } 1601 } 1602 tty_insert_flip_char(&port->port, ch, flag); 1603 cnt++; 1604 if (cnt >= recv_room) { 1605 if (!port->ldisc_stop_rx) 1606 mxser_stoprx(tty); 1607 break; 1608 } 1609 1610 } 1611 1612 if (hwid) 1613 break; 1614 1615 status = inb(port->ioaddr + UART_LSR); 1616 } while (status & UART_LSR_DR); 1617 1618 return status; 1619 } 1620 1621 static u8 mxser_receive_chars(struct tty_struct *tty, 1622 struct mxser_port *port, u8 status) 1623 { 1624 if (tty->receive_room == 0 && !port->ldisc_stop_rx) 1625 mxser_stoprx(tty); 1626 1627 if (!mxser_receive_chars_new(tty, port, status)) 1628 status = mxser_receive_chars_old(tty, port, status); 1629 1630 tty_flip_buffer_push(&port->port); 1631 1632 return status; 1633 } 1634 1635 static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port) 1636 { 1637 int count, cnt; 1638 1639 if (port->x_char) { 1640 outb(port->x_char, port->ioaddr + UART_TX); 1641 port->x_char = 0; 1642 port->icount.tx++; 1643 return; 1644 } 1645 1646 if (port->port.xmit_buf == NULL) 1647 return; 1648 1649 if (!port->xmit_cnt || tty->flow.stopped || 1650 (tty->hw_stopped && !mxser_16550A_or_MUST(port))) { 1651 __mxser_stop_tx(port); 1652 return; 1653 } 1654 1655 cnt = port->xmit_cnt; 1656 count = port->xmit_fifo_size; 1657 do { 1658 outb(port->port.xmit_buf[port->xmit_tail++], 1659 port->ioaddr + UART_TX); 1660 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1); 1661 if (!--port->xmit_cnt) 1662 break; 1663 } while (--count > 0); 1664 1665 port->icount.tx += (cnt - port->xmit_cnt); 1666 1667 if (port->xmit_cnt < WAKEUP_CHARS) 1668 tty_wakeup(tty); 1669 1670 if (!port->xmit_cnt) 1671 __mxser_stop_tx(port); 1672 } 1673 1674 static bool mxser_port_isr(struct mxser_port *port) 1675 { 1676 struct tty_struct *tty; 1677 u8 iir, msr, status; 1678 bool error = false; 1679 1680 iir = inb(port->ioaddr + UART_IIR); 1681 if (iir & UART_IIR_NO_INT) 1682 return true; 1683 1684 iir &= MOXA_MUST_IIR_MASK; 1685 tty = tty_port_tty_get(&port->port); 1686 if (!tty || port->closing || !tty_port_initialized(&port->port)) { 1687 status = inb(port->ioaddr + UART_LSR); 1688 outb(port->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 1689 port->ioaddr + UART_FCR); 1690 inb(port->ioaddr + UART_MSR); 1691 1692 error = true; 1693 goto put_tty; 1694 } 1695 1696 status = inb(port->ioaddr + UART_LSR); 1697 1698 if (port->board->must_hwid) { 1699 if (iir == MOXA_MUST_IIR_GDA || 1700 iir == MOXA_MUST_IIR_RDA || 1701 iir == MOXA_MUST_IIR_RTO || 1702 iir == MOXA_MUST_IIR_LSR) 1703 status = mxser_receive_chars(tty, port, status); 1704 } else { 1705 status &= port->read_status_mask; 1706 if (status & UART_LSR_DR) 1707 status = mxser_receive_chars(tty, port, status); 1708 } 1709 1710 msr = inb(port->ioaddr + UART_MSR); 1711 if (msr & UART_MSR_ANY_DELTA) 1712 mxser_check_modem_status(tty, port, msr); 1713 1714 if (port->board->must_hwid) { 1715 if (iir == 0x02 && (status & UART_LSR_THRE)) 1716 mxser_transmit_chars(tty, port); 1717 } else { 1718 if (status & UART_LSR_THRE) 1719 mxser_transmit_chars(tty, port); 1720 } 1721 1722 put_tty: 1723 tty_kref_put(tty); 1724 1725 return error; 1726 } 1727 1728 /* 1729 * This is the serial driver's generic interrupt routine 1730 */ 1731 static irqreturn_t mxser_interrupt(int irq, void *dev_id) 1732 { 1733 struct mxser_board *brd = dev_id; 1734 struct mxser_port *port; 1735 unsigned int int_cnt, pass_counter = 0; 1736 unsigned int i, max = brd->nports; 1737 int handled = IRQ_NONE; 1738 u8 irqbits, bits, mask = BIT(max) - 1; 1739 1740 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) { 1741 irqbits = inb(brd->vector) & mask; 1742 if (irqbits == mask) 1743 break; 1744 1745 handled = IRQ_HANDLED; 1746 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) { 1747 if (irqbits == mask) 1748 break; 1749 if (bits & irqbits) 1750 continue; 1751 port = &brd->ports[i]; 1752 1753 int_cnt = 0; 1754 spin_lock(&port->slock); 1755 do { 1756 if (mxser_port_isr(port)) 1757 break; 1758 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT); 1759 spin_unlock(&port->slock); 1760 } 1761 } 1762 1763 return handled; 1764 } 1765 1766 static const struct tty_operations mxser_ops = { 1767 .open = mxser_open, 1768 .close = mxser_close, 1769 .write = mxser_write, 1770 .put_char = mxser_put_char, 1771 .flush_chars = mxser_flush_chars, 1772 .write_room = mxser_write_room, 1773 .chars_in_buffer = mxser_chars_in_buffer, 1774 .flush_buffer = mxser_flush_buffer, 1775 .ioctl = mxser_ioctl, 1776 .throttle = mxser_throttle, 1777 .unthrottle = mxser_unthrottle, 1778 .set_termios = mxser_set_termios, 1779 .stop = mxser_stop, 1780 .start = mxser_start, 1781 .hangup = mxser_hangup, 1782 .break_ctl = mxser_rs_break, 1783 .wait_until_sent = mxser_wait_until_sent, 1784 .tiocmget = mxser_tiocmget, 1785 .tiocmset = mxser_tiocmset, 1786 .set_serial = mxser_set_serial_info, 1787 .get_serial = mxser_get_serial_info, 1788 .get_icount = mxser_get_icount, 1789 }; 1790 1791 static const struct tty_port_operations mxser_port_ops = { 1792 .carrier_raised = mxser_carrier_raised, 1793 .dtr_rts = mxser_dtr_rts, 1794 .activate = mxser_activate, 1795 .shutdown = mxser_shutdown_port, 1796 }; 1797 1798 /* 1799 * The MOXA Smartio/Industio serial driver boot-time initialization code! 1800 */ 1801 1802 static void mxser_initbrd(struct mxser_board *brd, bool high_baud) 1803 { 1804 struct mxser_port *info; 1805 unsigned int i; 1806 bool is_mu860; 1807 1808 brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr); 1809 is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID; 1810 1811 for (i = 0; i < UART_INFO_NUM; i++) { 1812 if (Gpci_uart_info[i].type == brd->must_hwid) { 1813 brd->max_baud = Gpci_uart_info[i].max_baud; 1814 1815 /* exception....CP-102 */ 1816 if (high_baud) 1817 brd->max_baud = 921600; 1818 break; 1819 } 1820 } 1821 1822 if (is_mu860) { 1823 /* set to RS232 mode by default */ 1824 outb(0, brd->vector + 4); 1825 outb(0, brd->vector + 0x0c); 1826 } 1827 1828 for (i = 0; i < brd->nports; i++) { 1829 info = &brd->ports[i]; 1830 if (is_mu860) { 1831 if (i < 4) 1832 info->opmode_ioaddr = brd->vector + 4; 1833 else 1834 info->opmode_ioaddr = brd->vector + 0x0c; 1835 } 1836 tty_port_init(&info->port); 1837 info->port.ops = &mxser_port_ops; 1838 info->board = brd; 1839 info->ldisc_stop_rx = false; 1840 1841 /* Enhance mode enabled here */ 1842 if (brd->must_hwid != MOXA_OTHER_UART) 1843 mxser_must_set_enhance_mode(info->ioaddr, true); 1844 1845 info->type = PORT_16550A; 1846 1847 mxser_process_txrx_fifo(info); 1848 1849 info->port.close_delay = 5 * HZ / 10; 1850 info->port.closing_wait = 30 * HZ; 1851 spin_lock_init(&info->slock); 1852 1853 /* before set INT ISR, disable all int */ 1854 outb(inb(info->ioaddr + UART_IER) & 0xf0, 1855 info->ioaddr + UART_IER); 1856 } 1857 } 1858 1859 static int mxser_probe(struct pci_dev *pdev, 1860 const struct pci_device_id *ent) 1861 { 1862 struct mxser_board *brd; 1863 unsigned int i, base; 1864 unsigned long ioaddress; 1865 unsigned short nports = MXSER_NPORTS(ent->driver_data); 1866 struct device *tty_dev; 1867 int retval = -EINVAL; 1868 1869 i = find_first_zero_bit(mxser_boards, MXSER_BOARDS); 1870 if (i >= MXSER_BOARDS) { 1871 dev_err(&pdev->dev, "too many boards found (maximum %d), board " 1872 "not configured\n", MXSER_BOARDS); 1873 goto err; 1874 } 1875 1876 brd = devm_kzalloc(&pdev->dev, struct_size(brd, ports, nports), 1877 GFP_KERNEL); 1878 if (!brd) 1879 goto err; 1880 1881 brd->idx = i; 1882 __set_bit(brd->idx, mxser_boards); 1883 base = i * MXSER_PORTS_PER_BOARD; 1884 1885 retval = pcim_enable_device(pdev); 1886 if (retval) { 1887 dev_err(&pdev->dev, "PCI enable failed\n"); 1888 goto err_zero; 1889 } 1890 1891 /* io address */ 1892 ioaddress = pci_resource_start(pdev, 2); 1893 retval = pci_request_region(pdev, 2, "mxser(IO)"); 1894 if (retval) 1895 goto err_zero; 1896 1897 brd->nports = nports; 1898 for (i = 0; i < nports; i++) 1899 brd->ports[i].ioaddr = ioaddress + 8 * i; 1900 1901 /* vector */ 1902 ioaddress = pci_resource_start(pdev, 3); 1903 retval = pci_request_region(pdev, 3, "mxser(vector)"); 1904 if (retval) 1905 goto err_zero; 1906 brd->vector = ioaddress; 1907 1908 /* irq */ 1909 brd->irq = pdev->irq; 1910 1911 mxser_initbrd(brd, ent->driver_data & MXSER_HIGHBAUD); 1912 1913 retval = devm_request_irq(&pdev->dev, brd->irq, mxser_interrupt, 1914 IRQF_SHARED, "mxser", brd); 1915 if (retval) { 1916 dev_err(&pdev->dev, "request irq failed"); 1917 goto err_relbrd; 1918 } 1919 1920 for (i = 0; i < nports; i++) { 1921 tty_dev = tty_port_register_device(&brd->ports[i].port, 1922 mxvar_sdriver, base + i, &pdev->dev); 1923 if (IS_ERR(tty_dev)) { 1924 retval = PTR_ERR(tty_dev); 1925 for (; i > 0; i--) 1926 tty_unregister_device(mxvar_sdriver, 1927 base + i - 1); 1928 goto err_relbrd; 1929 } 1930 } 1931 1932 pci_set_drvdata(pdev, brd); 1933 1934 return 0; 1935 err_relbrd: 1936 for (i = 0; i < nports; i++) 1937 tty_port_destroy(&brd->ports[i].port); 1938 err_zero: 1939 __clear_bit(brd->idx, mxser_boards); 1940 err: 1941 return retval; 1942 } 1943 1944 static void mxser_remove(struct pci_dev *pdev) 1945 { 1946 struct mxser_board *brd = pci_get_drvdata(pdev); 1947 unsigned int i, base = brd->idx * MXSER_PORTS_PER_BOARD; 1948 1949 for (i = 0; i < brd->nports; i++) { 1950 tty_unregister_device(mxvar_sdriver, base + i); 1951 tty_port_destroy(&brd->ports[i].port); 1952 } 1953 1954 __clear_bit(brd->idx, mxser_boards); 1955 } 1956 1957 static struct pci_driver mxser_driver = { 1958 .name = "mxser", 1959 .id_table = mxser_pcibrds, 1960 .probe = mxser_probe, 1961 .remove = mxser_remove 1962 }; 1963 1964 static int __init mxser_module_init(void) 1965 { 1966 int retval; 1967 1968 mxvar_sdriver = tty_alloc_driver(MXSER_PORTS, TTY_DRIVER_REAL_RAW | 1969 TTY_DRIVER_DYNAMIC_DEV); 1970 if (IS_ERR(mxvar_sdriver)) 1971 return PTR_ERR(mxvar_sdriver); 1972 1973 /* Initialize the tty_driver structure */ 1974 mxvar_sdriver->name = "ttyMI"; 1975 mxvar_sdriver->major = ttymajor; 1976 mxvar_sdriver->minor_start = 0; 1977 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL; 1978 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL; 1979 mxvar_sdriver->init_termios = tty_std_termios; 1980 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL; 1981 tty_set_operations(mxvar_sdriver, &mxser_ops); 1982 1983 retval = tty_register_driver(mxvar_sdriver); 1984 if (retval) { 1985 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family " 1986 "tty driver !\n"); 1987 goto err_put; 1988 } 1989 1990 retval = pci_register_driver(&mxser_driver); 1991 if (retval) { 1992 printk(KERN_ERR "mxser: can't register pci driver\n"); 1993 goto err_unr; 1994 } 1995 1996 return 0; 1997 err_unr: 1998 tty_unregister_driver(mxvar_sdriver); 1999 err_put: 2000 tty_driver_kref_put(mxvar_sdriver); 2001 return retval; 2002 } 2003 2004 static void __exit mxser_module_exit(void) 2005 { 2006 pci_unregister_driver(&mxser_driver); 2007 tty_unregister_driver(mxvar_sdriver); 2008 tty_driver_kref_put(mxvar_sdriver); 2009 } 2010 2011 module_init(mxser_module_init); 2012 module_exit(mxser_module_exit); 2013