1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * mxser.c -- MOXA Smartio/Industio family multiport serial driver. 4 * 5 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com). 6 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com> 7 * 8 * This code is loosely based on the 1.8 moxa driver which is based on 9 * Linux serial driver, written by Linus Torvalds, Theodore T'so and 10 * others. 11 * 12 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox 13 * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on 14 * www.moxa.com. 15 * - Fixed x86_64 cleanness 16 */ 17 18 #include <linux/module.h> 19 #include <linux/errno.h> 20 #include <linux/signal.h> 21 #include <linux/sched.h> 22 #include <linux/timer.h> 23 #include <linux/interrupt.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/serial.h> 27 #include <linux/serial_reg.h> 28 #include <linux/major.h> 29 #include <linux/string.h> 30 #include <linux/fcntl.h> 31 #include <linux/ptrace.h> 32 #include <linux/ioport.h> 33 #include <linux/mm.h> 34 #include <linux/delay.h> 35 #include <linux/pci.h> 36 #include <linux/bitops.h> 37 #include <linux/slab.h> 38 #include <linux/ratelimit.h> 39 40 #include <asm/io.h> 41 #include <asm/irq.h> 42 #include <linux/uaccess.h> 43 44 /* 45 * Semi-public control interfaces 46 */ 47 48 /* 49 * MOXA ioctls 50 */ 51 52 #define MOXA 0x400 53 #define MOXA_SET_OP_MODE (MOXA + 66) 54 #define MOXA_GET_OP_MODE (MOXA + 67) 55 56 #define RS232_MODE 0 57 #define RS485_2WIRE_MODE 1 58 #define RS422_MODE 2 59 #define RS485_4WIRE_MODE 3 60 #define OP_MODE_MASK 3 61 62 /* --------------------------------------------------- */ 63 64 /* 65 * Follow just what Moxa Must chip defines. 66 * 67 * When LCR register (offset 0x03) is written the following value, the Must chip 68 * will enter enhanced mode. And a write to EFR (offset 0x02) bit 6,7 will 69 * change bank. 70 */ 71 #define MOXA_MUST_ENTER_ENHANCED 0xBF 72 73 /* when enhanced mode is enabled, access to general bank register */ 74 #define MOXA_MUST_GDL_REGISTER 0x07 75 #define MOXA_MUST_GDL_MASK 0x7F 76 #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 77 78 #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */ 79 /* enhanced register bank select and enhanced mode setting register */ 80 /* This works only when LCR register equals to 0xBF */ 81 #define MOXA_MUST_EFR_REGISTER 0x02 82 #define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enhanced mode enable */ 83 /* enhanced register bank set 0, 1, 2 */ 84 #define MOXA_MUST_EFR_BANK0 0x00 85 #define MOXA_MUST_EFR_BANK1 0x40 86 #define MOXA_MUST_EFR_BANK2 0x80 87 #define MOXA_MUST_EFR_BANK3 0xC0 88 #define MOXA_MUST_EFR_BANK_MASK 0xC0 89 90 /* set XON1 value register, when LCR=0xBF and change to bank0 */ 91 #define MOXA_MUST_XON1_REGISTER 0x04 92 93 /* set XON2 value register, when LCR=0xBF and change to bank0 */ 94 #define MOXA_MUST_XON2_REGISTER 0x05 95 96 /* set XOFF1 value register, when LCR=0xBF and change to bank0 */ 97 #define MOXA_MUST_XOFF1_REGISTER 0x06 98 99 /* set XOFF2 value register, when LCR=0xBF and change to bank0 */ 100 #define MOXA_MUST_XOFF2_REGISTER 0x07 101 102 #define MOXA_MUST_RBRTL_REGISTER 0x04 103 #define MOXA_MUST_RBRTH_REGISTER 0x05 104 #define MOXA_MUST_RBRTI_REGISTER 0x06 105 #define MOXA_MUST_THRTL_REGISTER 0x07 106 #define MOXA_MUST_ENUM_REGISTER 0x04 107 #define MOXA_MUST_HWID_REGISTER 0x05 108 #define MOXA_MUST_ECR_REGISTER 0x06 109 #define MOXA_MUST_CSR_REGISTER 0x07 110 111 #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */ 112 #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */ 113 114 #define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */ 115 #define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */ 116 #define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */ 117 #define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */ 118 119 #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) 120 121 /* GDA interrupt pending */ 122 #define MOXA_MUST_IIR_GDA 0x1C 123 #define MOXA_MUST_IIR_RDA 0x04 124 #define MOXA_MUST_IIR_RTO 0x0C 125 #define MOXA_MUST_IIR_LSR 0x06 126 127 /* received Xon/Xoff or specical interrupt pending */ 128 #define MOXA_MUST_IIR_XSC 0x10 129 130 /* RTS/CTS change state interrupt pending */ 131 #define MOXA_MUST_IIR_RTSCTS 0x20 132 #define MOXA_MUST_IIR_MASK 0x3E 133 134 #define MOXA_MUST_MCR_XON_FLAG 0x40 135 #define MOXA_MUST_MCR_XON_ANY 0x80 136 #define MOXA_MUST_MCR_TX_XON 0x08 137 138 #define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */ 139 #define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */ 140 #define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */ 141 #define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */ 142 #define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */ 143 #define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */ 144 #define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */ 145 #define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */ 146 #define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */ 147 #define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */ 148 #define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */ 149 150 #define MXSERMAJOR 174 151 152 #define MXSER_BOARDS 4 /* Max. boards */ 153 #define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */ 154 #define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD) 155 #define MXSER_ISR_PASS_LIMIT 100 156 157 #define WAKEUP_CHARS 256 158 159 #define MXSER_BAUD_BASE 921600 160 #define MXSER_CUSTOM_DIVISOR (MXSER_BAUD_BASE * 16) 161 162 #define PCI_DEVICE_ID_MOXA_RC7000 0x0001 163 #define PCI_DEVICE_ID_MOXA_CP102 0x1020 164 #define PCI_DEVICE_ID_MOXA_CP102UL 0x1021 165 #define PCI_DEVICE_ID_MOXA_CP102U 0x1022 166 #define PCI_DEVICE_ID_MOXA_CP102UF 0x1023 167 #define PCI_DEVICE_ID_MOXA_C104 0x1040 168 #define PCI_DEVICE_ID_MOXA_CP104U 0x1041 169 #define PCI_DEVICE_ID_MOXA_CP104JU 0x1042 170 #define PCI_DEVICE_ID_MOXA_CP104EL 0x1043 171 #define PCI_DEVICE_ID_MOXA_POS104UL 0x1044 172 #define PCI_DEVICE_ID_MOXA_CB108 0x1080 173 #define PCI_DEVICE_ID_MOXA_CP112UL 0x1120 174 #define PCI_DEVICE_ID_MOXA_CT114 0x1140 175 #define PCI_DEVICE_ID_MOXA_CP114 0x1141 176 #define PCI_DEVICE_ID_MOXA_CB114 0x1142 177 #define PCI_DEVICE_ID_MOXA_CP114UL 0x1143 178 #define PCI_DEVICE_ID_MOXA_CP118U 0x1180 179 #define PCI_DEVICE_ID_MOXA_CP118EL 0x1181 180 #define PCI_DEVICE_ID_MOXA_CP132 0x1320 181 #define PCI_DEVICE_ID_MOXA_CP132U 0x1321 182 #define PCI_DEVICE_ID_MOXA_CP134U 0x1340 183 #define PCI_DEVICE_ID_MOXA_CB134I 0x1341 184 #define PCI_DEVICE_ID_MOXA_CP138U 0x1380 185 #define PCI_DEVICE_ID_MOXA_C168 0x1680 186 #define PCI_DEVICE_ID_MOXA_CP168U 0x1681 187 #define PCI_DEVICE_ID_MOXA_CP168EL 0x1682 188 189 #define MXSER_NPORTS(ddata) ((ddata) & 0xffU) 190 #define MXSER_HIGHBAUD 0x0100 191 192 enum mxser_must_hwid { 193 MOXA_OTHER_UART = 0x00, 194 MOXA_MUST_MU150_HWID = 0x01, 195 MOXA_MUST_MU860_HWID = 0x02, 196 }; 197 198 static const struct { 199 u8 type; 200 u8 fifo_size; 201 u8 rx_high_water; 202 u8 rx_low_water; 203 speed_t max_baud; 204 } Gpci_uart_info[] = { 205 { MOXA_OTHER_UART, 16, 14, 1, 921600 }, 206 { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 }, 207 { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 } 208 }; 209 #define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info) 210 211 212 /* driver_data correspond to the lines in the structure above 213 see also ISA probe function before you change something */ 214 static const struct pci_device_id mxser_pcibrds[] = { 215 { PCI_DEVICE_DATA(MOXA, C168, 8) }, 216 { PCI_DEVICE_DATA(MOXA, C104, 4) }, 217 { PCI_DEVICE_DATA(MOXA, CP132, 2) }, 218 { PCI_DEVICE_DATA(MOXA, CP114, 4) }, 219 { PCI_DEVICE_DATA(MOXA, CT114, 4) }, 220 { PCI_DEVICE_DATA(MOXA, CP102, 2 | MXSER_HIGHBAUD) }, 221 { PCI_DEVICE_DATA(MOXA, CP104U, 4) }, 222 { PCI_DEVICE_DATA(MOXA, CP168U, 8) }, 223 { PCI_DEVICE_DATA(MOXA, CP132U, 2) }, 224 { PCI_DEVICE_DATA(MOXA, CP134U, 4) }, 225 { PCI_DEVICE_DATA(MOXA, CP104JU, 4) }, 226 { PCI_DEVICE_DATA(MOXA, RC7000, 8) }, /* RC7000 */ 227 { PCI_DEVICE_DATA(MOXA, CP118U, 8) }, 228 { PCI_DEVICE_DATA(MOXA, CP102UL, 2) }, 229 { PCI_DEVICE_DATA(MOXA, CP102U, 2) }, 230 { PCI_DEVICE_DATA(MOXA, CP118EL, 8) }, 231 { PCI_DEVICE_DATA(MOXA, CP168EL, 8) }, 232 { PCI_DEVICE_DATA(MOXA, CP104EL, 4) }, 233 { PCI_DEVICE_DATA(MOXA, CB108, 8) }, 234 { PCI_DEVICE_DATA(MOXA, CB114, 4) }, 235 { PCI_DEVICE_DATA(MOXA, CB134I, 4) }, 236 { PCI_DEVICE_DATA(MOXA, CP138U, 8) }, 237 { PCI_DEVICE_DATA(MOXA, POS104UL, 4) }, 238 { PCI_DEVICE_DATA(MOXA, CP114UL, 4) }, 239 { PCI_DEVICE_DATA(MOXA, CP102UF, 2) }, 240 { PCI_DEVICE_DATA(MOXA, CP112UL, 2) }, 241 { } 242 }; 243 MODULE_DEVICE_TABLE(pci, mxser_pcibrds); 244 245 static int ttymajor = MXSERMAJOR; 246 247 /* Variables for insmod */ 248 249 MODULE_AUTHOR("Casper Yang"); 250 MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver"); 251 module_param(ttymajor, int, 0); 252 MODULE_LICENSE("GPL"); 253 254 struct mxser_board; 255 256 struct mxser_port { 257 struct tty_port port; 258 struct mxser_board *board; 259 260 unsigned long ioaddr; 261 unsigned long opmode_ioaddr; 262 263 u8 rx_high_water; 264 u8 rx_low_water; 265 int type; /* UART type */ 266 267 unsigned char x_char; /* xon/xoff character */ 268 u8 IER; /* Interrupt Enable Register */ 269 u8 MCR; /* Modem control register */ 270 u8 FCR; /* FIFO control register */ 271 272 struct async_icount icount; /* kernel counters for 4 input interrupts */ 273 unsigned int timeout; 274 275 u8 read_status_mask; 276 u8 ignore_status_mask; 277 u8 xmit_fifo_size; 278 unsigned int xmit_head; 279 unsigned int xmit_tail; 280 unsigned int xmit_cnt; 281 282 spinlock_t slock; 283 }; 284 285 struct mxser_board { 286 unsigned int idx; 287 unsigned short nports; 288 int irq; 289 unsigned long vector; 290 291 enum mxser_must_hwid must_hwid; 292 speed_t max_baud; 293 294 struct mxser_port ports[]; 295 }; 296 297 static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS); 298 static struct tty_driver *mxvar_sdriver; 299 300 static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set, 301 bool restore_LCR) 302 { 303 u8 oldlcr, efr; 304 305 oldlcr = inb(baseio + UART_LCR); 306 outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR); 307 308 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 309 efr &= ~clear; 310 efr |= set; 311 312 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 313 314 if (restore_LCR) 315 outb(oldlcr, baseio + UART_LCR); 316 317 return oldlcr; 318 } 319 320 static u8 mxser_must_select_bank(unsigned long baseio, u8 bank) 321 { 322 return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank, 323 false); 324 } 325 326 static void mxser_set_must_xon1_value(unsigned long baseio, u8 value) 327 { 328 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); 329 outb(value, baseio + MOXA_MUST_XON1_REGISTER); 330 outb(oldlcr, baseio + UART_LCR); 331 } 332 333 static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value) 334 { 335 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); 336 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER); 337 outb(oldlcr, baseio + UART_LCR); 338 } 339 340 static void mxser_set_must_fifo_value(struct mxser_port *info) 341 { 342 u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1); 343 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER); 344 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER); 345 outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER); 346 outb(oldlcr, info->ioaddr + UART_LCR); 347 } 348 349 static void mxser_set_must_enum_value(unsigned long baseio, u8 value) 350 { 351 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); 352 outb(value, baseio + MOXA_MUST_ENUM_REGISTER); 353 outb(oldlcr, baseio + UART_LCR); 354 } 355 356 static u8 mxser_get_must_hardware_id(unsigned long baseio) 357 { 358 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); 359 u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER); 360 outb(oldlcr, baseio + UART_LCR); 361 362 return id; 363 } 364 365 static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set) 366 { 367 __mxser_must_set_EFR(baseio, clear, set, true); 368 } 369 370 static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable) 371 { 372 mxser_must_set_EFR(baseio, 373 enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE, 374 enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0); 375 } 376 377 static void mxser_must_no_sw_flow_control(unsigned long baseio) 378 { 379 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0); 380 } 381 382 static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable) 383 { 384 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK, 385 enable ? MOXA_MUST_EFR_SF_TX1 : 0); 386 } 387 388 static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable) 389 { 390 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK, 391 enable ? MOXA_MUST_EFR_SF_RX1 : 0); 392 } 393 394 static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io) 395 { 396 u8 oldmcr, hwid; 397 int i; 398 399 outb(0, io + UART_LCR); 400 mxser_must_set_enhance_mode(io, false); 401 oldmcr = inb(io + UART_MCR); 402 outb(0, io + UART_MCR); 403 mxser_set_must_xon1_value(io, 0x11); 404 if ((hwid = inb(io + UART_MCR)) != 0) { 405 outb(oldmcr, io + UART_MCR); 406 return MOXA_OTHER_UART; 407 } 408 409 hwid = mxser_get_must_hardware_id(io); 410 for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */ 411 if (hwid == Gpci_uart_info[i].type) 412 return hwid; 413 414 return MOXA_OTHER_UART; 415 } 416 417 static bool mxser_16550A_or_MUST(struct mxser_port *info) 418 { 419 return info->type == PORT_16550A || info->board->must_hwid; 420 } 421 422 static void mxser_process_txrx_fifo(struct mxser_port *info) 423 { 424 unsigned int i; 425 426 if (info->type == PORT_16450 || info->type == PORT_8250) { 427 info->rx_high_water = 1; 428 info->rx_low_water = 1; 429 info->xmit_fifo_size = 1; 430 return; 431 } 432 433 for (i = 0; i < UART_INFO_NUM; i++) 434 if (info->board->must_hwid == Gpci_uart_info[i].type) { 435 info->rx_low_water = Gpci_uart_info[i].rx_low_water; 436 info->rx_high_water = Gpci_uart_info[i].rx_high_water; 437 info->xmit_fifo_size = Gpci_uart_info[i].fifo_size; 438 break; 439 } 440 } 441 442 static void __mxser_start_tx(struct mxser_port *info) 443 { 444 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); 445 info->IER |= UART_IER_THRI; 446 outb(info->IER, info->ioaddr + UART_IER); 447 } 448 449 static void mxser_start_tx(struct mxser_port *info) 450 { 451 unsigned long flags; 452 453 spin_lock_irqsave(&info->slock, flags); 454 __mxser_start_tx(info); 455 spin_unlock_irqrestore(&info->slock, flags); 456 } 457 458 static void __mxser_stop_tx(struct mxser_port *info) 459 { 460 info->IER &= ~UART_IER_THRI; 461 outb(info->IER, info->ioaddr + UART_IER); 462 } 463 464 static int mxser_carrier_raised(struct tty_port *port) 465 { 466 struct mxser_port *mp = container_of(port, struct mxser_port, port); 467 return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0; 468 } 469 470 static void mxser_dtr_rts(struct tty_port *port, int on) 471 { 472 struct mxser_port *mp = container_of(port, struct mxser_port, port); 473 unsigned long flags; 474 u8 mcr; 475 476 spin_lock_irqsave(&mp->slock, flags); 477 mcr = inb(mp->ioaddr + UART_MCR); 478 if (on) 479 mcr |= UART_MCR_DTR | UART_MCR_RTS; 480 else 481 mcr &= ~(UART_MCR_DTR | UART_MCR_RTS); 482 outb(mcr, mp->ioaddr + UART_MCR); 483 spin_unlock_irqrestore(&mp->slock, flags); 484 } 485 486 static int mxser_set_baud(struct tty_struct *tty, speed_t newspd) 487 { 488 struct mxser_port *info = tty->driver_data; 489 unsigned int quot = 0, baud; 490 unsigned char cval; 491 u64 timeout; 492 493 if (newspd > info->board->max_baud) 494 return -1; 495 496 if (newspd == 134) { 497 quot = 2 * MXSER_BAUD_BASE / 269; 498 tty_encode_baud_rate(tty, 134, 134); 499 } else if (newspd) { 500 quot = MXSER_BAUD_BASE / newspd; 501 if (quot == 0) 502 quot = 1; 503 baud = MXSER_BAUD_BASE / quot; 504 tty_encode_baud_rate(tty, baud, baud); 505 } else { 506 quot = 0; 507 } 508 509 /* 510 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the 511 * u64 domain 512 */ 513 timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot; 514 do_div(timeout, MXSER_BAUD_BASE); 515 info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */ 516 517 if (quot) { 518 info->MCR |= UART_MCR_DTR; 519 outb(info->MCR, info->ioaddr + UART_MCR); 520 } else { 521 info->MCR &= ~UART_MCR_DTR; 522 outb(info->MCR, info->ioaddr + UART_MCR); 523 return 0; 524 } 525 526 cval = inb(info->ioaddr + UART_LCR); 527 528 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */ 529 530 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */ 531 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */ 532 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */ 533 534 #ifdef BOTHER 535 if (C_BAUD(tty) == BOTHER) { 536 quot = MXSER_BAUD_BASE % newspd; 537 quot *= 8; 538 if (quot % newspd > newspd / 2) { 539 quot /= newspd; 540 quot++; 541 } else 542 quot /= newspd; 543 544 mxser_set_must_enum_value(info->ioaddr, quot); 545 } else 546 #endif 547 mxser_set_must_enum_value(info->ioaddr, 0); 548 549 return 0; 550 } 551 552 static void mxser_handle_cts(struct tty_struct *tty, struct mxser_port *info, 553 u8 msr) 554 { 555 bool cts = msr & UART_MSR_CTS; 556 557 if (tty->hw_stopped) { 558 if (cts) { 559 tty->hw_stopped = 0; 560 561 if (!mxser_16550A_or_MUST(info)) 562 __mxser_start_tx(info); 563 tty_wakeup(tty); 564 } 565 return; 566 } else if (cts) 567 return; 568 569 tty->hw_stopped = 1; 570 if (!mxser_16550A_or_MUST(info)) 571 __mxser_stop_tx(info); 572 } 573 574 /* 575 * This routine is called to set the UART divisor registers to match 576 * the specified baud rate for a serial port. 577 */ 578 static void mxser_change_speed(struct tty_struct *tty, struct ktermios *old_termios) 579 { 580 struct mxser_port *info = tty->driver_data; 581 unsigned cflag, cval; 582 583 cflag = tty->termios.c_cflag; 584 585 if (mxser_set_baud(tty, tty_get_baud_rate(tty))) { 586 /* Use previous rate on a failure */ 587 if (old_termios) { 588 speed_t baud = tty_termios_baud_rate(old_termios); 589 tty_encode_baud_rate(tty, baud, baud); 590 } 591 } 592 593 /* byte size and parity */ 594 switch (cflag & CSIZE) { 595 default: 596 case CS5: 597 cval = UART_LCR_WLEN5; 598 break; 599 case CS6: 600 cval = UART_LCR_WLEN6; 601 break; 602 case CS7: 603 cval = UART_LCR_WLEN7; 604 break; 605 case CS8: 606 cval = UART_LCR_WLEN8; 607 break; 608 } 609 610 if (cflag & CSTOPB) 611 cval |= UART_LCR_STOP; 612 if (cflag & PARENB) 613 cval |= UART_LCR_PARITY; 614 if (!(cflag & PARODD)) 615 cval |= UART_LCR_EPAR; 616 if (cflag & CMSPAR) 617 cval |= UART_LCR_SPAR; 618 619 info->FCR = 0; 620 if (info->board->must_hwid) { 621 info->FCR |= UART_FCR_ENABLE_FIFO | 622 MOXA_MUST_FCR_GDA_MODE_ENABLE; 623 mxser_set_must_fifo_value(info); 624 } else if (info->type != PORT_8250 && info->type != PORT_16450) { 625 info->FCR |= UART_FCR_ENABLE_FIFO; 626 switch (info->rx_high_water) { 627 case 1: 628 info->FCR |= UART_FCR_TRIGGER_1; 629 break; 630 case 4: 631 info->FCR |= UART_FCR_TRIGGER_4; 632 break; 633 case 8: 634 info->FCR |= UART_FCR_TRIGGER_8; 635 break; 636 default: 637 info->FCR |= UART_FCR_TRIGGER_14; 638 break; 639 } 640 } 641 642 /* CTS flow control flag and modem status interrupts */ 643 info->IER &= ~UART_IER_MSI; 644 info->MCR &= ~UART_MCR_AFE; 645 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS); 646 if (cflag & CRTSCTS) { 647 info->IER |= UART_IER_MSI; 648 if (mxser_16550A_or_MUST(info)) { 649 info->MCR |= UART_MCR_AFE; 650 } else { 651 mxser_handle_cts(tty, info, 652 inb(info->ioaddr + UART_MSR)); 653 } 654 } 655 outb(info->MCR, info->ioaddr + UART_MCR); 656 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL); 657 if (~cflag & CLOCAL) 658 info->IER |= UART_IER_MSI; 659 outb(info->IER, info->ioaddr + UART_IER); 660 661 /* 662 * Set up parity check flag 663 */ 664 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 665 if (I_INPCK(tty)) 666 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 667 if (I_BRKINT(tty) || I_PARMRK(tty)) 668 info->read_status_mask |= UART_LSR_BI; 669 670 info->ignore_status_mask = 0; 671 672 if (I_IGNBRK(tty)) { 673 info->ignore_status_mask |= UART_LSR_BI; 674 info->read_status_mask |= UART_LSR_BI; 675 /* 676 * If we're ignore parity and break indicators, ignore 677 * overruns too. (For real raw support). 678 */ 679 if (I_IGNPAR(tty)) { 680 info->ignore_status_mask |= 681 UART_LSR_OE | 682 UART_LSR_PE | 683 UART_LSR_FE; 684 info->read_status_mask |= 685 UART_LSR_OE | 686 UART_LSR_PE | 687 UART_LSR_FE; 688 } 689 } 690 if (info->board->must_hwid) { 691 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty)); 692 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty)); 693 mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty)); 694 mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty)); 695 } 696 697 698 outb(info->FCR, info->ioaddr + UART_FCR); 699 outb(cval, info->ioaddr + UART_LCR); 700 } 701 702 static u8 mxser_check_modem_status(struct tty_struct *tty, 703 struct mxser_port *port) 704 { 705 u8 msr = inb(port->ioaddr + UART_MSR); 706 707 if (!(msr & UART_MSR_ANY_DELTA)) 708 return msr; 709 710 /* update input line counters */ 711 if (msr & UART_MSR_TERI) 712 port->icount.rng++; 713 if (msr & UART_MSR_DDSR) 714 port->icount.dsr++; 715 if (msr & UART_MSR_DDCD) 716 port->icount.dcd++; 717 if (msr & UART_MSR_DCTS) 718 port->icount.cts++; 719 wake_up_interruptible(&port->port.delta_msr_wait); 720 721 if (tty_port_check_carrier(&port->port) && (msr & UART_MSR_DDCD)) { 722 if (msr & UART_MSR_DCD) 723 wake_up_interruptible(&port->port.open_wait); 724 } 725 726 if (tty_port_cts_enabled(&port->port)) 727 mxser_handle_cts(tty, port, msr); 728 729 return msr; 730 } 731 732 static void mxser_disable_and_clear_FIFO(struct mxser_port *info) 733 { 734 u8 fcr = UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT; 735 736 if (info->board->must_hwid) 737 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; 738 739 outb(fcr, info->ioaddr + UART_FCR); 740 } 741 742 static int mxser_activate(struct tty_port *port, struct tty_struct *tty) 743 { 744 struct mxser_port *info = container_of(port, struct mxser_port, port); 745 unsigned long page; 746 unsigned long flags; 747 748 page = __get_free_page(GFP_KERNEL); 749 if (!page) 750 return -ENOMEM; 751 752 spin_lock_irqsave(&info->slock, flags); 753 754 if (!info->type) { 755 set_bit(TTY_IO_ERROR, &tty->flags); 756 free_page(page); 757 spin_unlock_irqrestore(&info->slock, flags); 758 return 0; 759 } 760 info->port.xmit_buf = (unsigned char *) page; 761 762 /* 763 * Clear the FIFO buffers and disable them 764 * (they will be reenabled in mxser_change_speed()) 765 */ 766 mxser_disable_and_clear_FIFO(info); 767 768 /* 769 * At this point there's no way the LSR could still be 0xFF; 770 * if it is, then bail out, because there's likely no UART 771 * here. 772 */ 773 if (inb(info->ioaddr + UART_LSR) == 0xff) { 774 spin_unlock_irqrestore(&info->slock, flags); 775 if (capable(CAP_SYS_ADMIN)) { 776 set_bit(TTY_IO_ERROR, &tty->flags); 777 return 0; 778 } else 779 return -ENODEV; 780 } 781 782 /* 783 * Clear the interrupt registers. 784 */ 785 (void) inb(info->ioaddr + UART_LSR); 786 (void) inb(info->ioaddr + UART_RX); 787 (void) inb(info->ioaddr + UART_IIR); 788 (void) inb(info->ioaddr + UART_MSR); 789 790 /* 791 * Now, initialize the UART 792 */ 793 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */ 794 info->MCR = UART_MCR_DTR | UART_MCR_RTS; 795 outb(info->MCR, info->ioaddr + UART_MCR); 796 797 /* 798 * Finally, enable interrupts 799 */ 800 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; 801 802 if (info->board->must_hwid) 803 info->IER |= MOXA_MUST_IER_EGDAI; 804 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */ 805 806 /* 807 * And clear the interrupt registers again for luck. 808 */ 809 (void) inb(info->ioaddr + UART_LSR); 810 (void) inb(info->ioaddr + UART_RX); 811 (void) inb(info->ioaddr + UART_IIR); 812 (void) inb(info->ioaddr + UART_MSR); 813 814 clear_bit(TTY_IO_ERROR, &tty->flags); 815 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; 816 817 /* 818 * and set the speed of the serial port 819 */ 820 mxser_change_speed(tty, NULL); 821 spin_unlock_irqrestore(&info->slock, flags); 822 823 return 0; 824 } 825 826 /* 827 * To stop accepting input, we disable the receive line status interrupts, and 828 * tell the interrupt driver to stop checking the data ready bit in the line 829 * status register. 830 */ 831 static void mxser_stop_rx(struct mxser_port *info) 832 { 833 info->IER &= ~UART_IER_RLSI; 834 if (info->board->must_hwid) 835 info->IER &= ~MOXA_MUST_RECV_ISR; 836 837 outb(info->IER, info->ioaddr + UART_IER); 838 } 839 840 /* 841 * This routine will shutdown a serial port 842 */ 843 static void mxser_shutdown_port(struct tty_port *port) 844 { 845 struct mxser_port *info = container_of(port, struct mxser_port, port); 846 unsigned long flags; 847 848 spin_lock_irqsave(&info->slock, flags); 849 850 mxser_stop_rx(info); 851 852 /* 853 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq 854 * here so the queue might never be waken up 855 */ 856 wake_up_interruptible(&info->port.delta_msr_wait); 857 858 /* 859 * Free the xmit buffer, if necessary 860 */ 861 if (info->port.xmit_buf) { 862 free_page((unsigned long) info->port.xmit_buf); 863 info->port.xmit_buf = NULL; 864 } 865 866 info->IER = 0; 867 outb(0x00, info->ioaddr + UART_IER); 868 869 /* clear Rx/Tx FIFO's */ 870 mxser_disable_and_clear_FIFO(info); 871 872 /* read data port to reset things */ 873 (void) inb(info->ioaddr + UART_RX); 874 875 876 if (info->board->must_hwid) 877 mxser_must_no_sw_flow_control(info->ioaddr); 878 879 spin_unlock_irqrestore(&info->slock, flags); 880 } 881 882 /* 883 * This routine is called whenever a serial port is opened. It 884 * enables interrupts for a serial port, linking in its async structure into 885 * the IRQ chain. It also performs the serial-specific 886 * initialization for the tty structure. 887 */ 888 static int mxser_open(struct tty_struct *tty, struct file *filp) 889 { 890 struct tty_port *tport = tty->port; 891 struct mxser_port *port = container_of(tport, struct mxser_port, port); 892 893 tty->driver_data = port; 894 895 return tty_port_open(tport, tty, filp); 896 } 897 898 static void mxser_flush_buffer(struct tty_struct *tty) 899 { 900 struct mxser_port *info = tty->driver_data; 901 unsigned long flags; 902 903 904 spin_lock_irqsave(&info->slock, flags); 905 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; 906 907 outb(info->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 908 info->ioaddr + UART_FCR); 909 910 spin_unlock_irqrestore(&info->slock, flags); 911 912 tty_wakeup(tty); 913 } 914 915 static void mxser_close(struct tty_struct *tty, struct file *filp) 916 { 917 tty_port_close(tty->port, tty, filp); 918 } 919 920 static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count) 921 { 922 int c, total = 0; 923 struct mxser_port *info = tty->driver_data; 924 unsigned long flags; 925 926 while (1) { 927 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, 928 SERIAL_XMIT_SIZE - info->xmit_head)); 929 if (c <= 0) 930 break; 931 932 memcpy(info->port.xmit_buf + info->xmit_head, buf, c); 933 spin_lock_irqsave(&info->slock, flags); 934 info->xmit_head = (info->xmit_head + c) & 935 (SERIAL_XMIT_SIZE - 1); 936 info->xmit_cnt += c; 937 spin_unlock_irqrestore(&info->slock, flags); 938 939 buf += c; 940 count -= c; 941 total += c; 942 } 943 944 if (info->xmit_cnt && !tty->flow.stopped) 945 if (!tty->hw_stopped || mxser_16550A_or_MUST(info)) 946 mxser_start_tx(info); 947 948 return total; 949 } 950 951 static int mxser_put_char(struct tty_struct *tty, unsigned char ch) 952 { 953 struct mxser_port *info = tty->driver_data; 954 unsigned long flags; 955 956 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1) 957 return 0; 958 959 spin_lock_irqsave(&info->slock, flags); 960 info->port.xmit_buf[info->xmit_head++] = ch; 961 info->xmit_head &= SERIAL_XMIT_SIZE - 1; 962 info->xmit_cnt++; 963 spin_unlock_irqrestore(&info->slock, flags); 964 965 return 1; 966 } 967 968 969 static void mxser_flush_chars(struct tty_struct *tty) 970 { 971 struct mxser_port *info = tty->driver_data; 972 973 if (!info->xmit_cnt || tty->flow.stopped || 974 (tty->hw_stopped && !mxser_16550A_or_MUST(info))) 975 return; 976 977 mxser_start_tx(info); 978 } 979 980 static unsigned int mxser_write_room(struct tty_struct *tty) 981 { 982 struct mxser_port *info = tty->driver_data; 983 int ret; 984 985 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1; 986 return ret < 0 ? 0 : ret; 987 } 988 989 static unsigned int mxser_chars_in_buffer(struct tty_struct *tty) 990 { 991 struct mxser_port *info = tty->driver_data; 992 return info->xmit_cnt; 993 } 994 995 /* 996 * ------------------------------------------------------------ 997 * friends of mxser_ioctl() 998 * ------------------------------------------------------------ 999 */ 1000 static int mxser_get_serial_info(struct tty_struct *tty, 1001 struct serial_struct *ss) 1002 { 1003 struct mxser_port *info = tty->driver_data; 1004 struct tty_port *port = &info->port; 1005 unsigned int closing_wait, close_delay; 1006 1007 mutex_lock(&port->mutex); 1008 1009 close_delay = jiffies_to_msecs(info->port.close_delay) / 10; 1010 closing_wait = info->port.closing_wait; 1011 if (closing_wait != ASYNC_CLOSING_WAIT_NONE) 1012 closing_wait = jiffies_to_msecs(closing_wait) / 10; 1013 1014 ss->type = info->type; 1015 ss->line = tty->index; 1016 ss->port = info->ioaddr; 1017 ss->irq = info->board->irq; 1018 ss->flags = info->port.flags; 1019 ss->baud_base = MXSER_BAUD_BASE; 1020 ss->close_delay = close_delay; 1021 ss->closing_wait = closing_wait; 1022 ss->custom_divisor = MXSER_CUSTOM_DIVISOR, 1023 mutex_unlock(&port->mutex); 1024 return 0; 1025 } 1026 1027 static int mxser_set_serial_info(struct tty_struct *tty, 1028 struct serial_struct *ss) 1029 { 1030 struct mxser_port *info = tty->driver_data; 1031 struct tty_port *port = &info->port; 1032 speed_t baud; 1033 unsigned long sl_flags; 1034 unsigned int old_speed, close_delay, closing_wait; 1035 int retval = 0; 1036 1037 if (tty_io_error(tty)) 1038 return -EIO; 1039 1040 mutex_lock(&port->mutex); 1041 1042 if (ss->irq != info->board->irq || 1043 ss->port != info->ioaddr) { 1044 mutex_unlock(&port->mutex); 1045 return -EINVAL; 1046 } 1047 1048 old_speed = port->flags & ASYNC_SPD_MASK; 1049 1050 close_delay = msecs_to_jiffies(ss->close_delay * 10); 1051 closing_wait = ss->closing_wait; 1052 if (closing_wait != ASYNC_CLOSING_WAIT_NONE) 1053 closing_wait = msecs_to_jiffies(closing_wait * 10); 1054 1055 if (!capable(CAP_SYS_ADMIN)) { 1056 if ((ss->baud_base != MXSER_BAUD_BASE) || 1057 (close_delay != port->close_delay) || 1058 (closing_wait != port->closing_wait) || 1059 ((ss->flags & ~ASYNC_USR_MASK) != (port->flags & ~ASYNC_USR_MASK))) { 1060 mutex_unlock(&port->mutex); 1061 return -EPERM; 1062 } 1063 port->flags = (port->flags & ~ASYNC_USR_MASK) | 1064 (ss->flags & ASYNC_USR_MASK); 1065 } else { 1066 /* 1067 * OK, past this point, all the error checking has been done. 1068 * At this point, we start making changes..... 1069 */ 1070 port->flags = ((port->flags & ~ASYNC_FLAGS) | 1071 (ss->flags & ASYNC_FLAGS)); 1072 port->close_delay = close_delay; 1073 port->closing_wait = closing_wait; 1074 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST && 1075 (ss->baud_base != MXSER_BAUD_BASE || 1076 ss->custom_divisor != 1077 MXSER_CUSTOM_DIVISOR)) { 1078 if (ss->custom_divisor == 0) { 1079 mutex_unlock(&port->mutex); 1080 return -EINVAL; 1081 } 1082 baud = ss->baud_base / ss->custom_divisor; 1083 tty_encode_baud_rate(tty, baud, baud); 1084 } 1085 1086 info->type = ss->type; 1087 1088 mxser_process_txrx_fifo(info); 1089 } 1090 1091 if (tty_port_initialized(port)) { 1092 if (old_speed != (port->flags & ASYNC_SPD_MASK)) { 1093 spin_lock_irqsave(&info->slock, sl_flags); 1094 mxser_change_speed(tty, NULL); 1095 spin_unlock_irqrestore(&info->slock, sl_flags); 1096 } 1097 } else { 1098 retval = mxser_activate(port, tty); 1099 if (retval == 0) 1100 tty_port_set_initialized(port, 1); 1101 } 1102 mutex_unlock(&port->mutex); 1103 return retval; 1104 } 1105 1106 /* 1107 * mxser_get_lsr_info - get line status register info 1108 * 1109 * Purpose: Let user call ioctl() to get info when the UART physically 1110 * is emptied. On bus types like RS485, the transmitter must 1111 * release the bus after transmitting. This must be done when 1112 * the transmit shift register is empty, not be done when the 1113 * transmit holding register is empty. This functionality 1114 * allows an RS485 driver to be written in user space. 1115 */ 1116 static int mxser_get_lsr_info(struct mxser_port *info, 1117 unsigned int __user *value) 1118 { 1119 unsigned char status; 1120 unsigned int result; 1121 unsigned long flags; 1122 1123 spin_lock_irqsave(&info->slock, flags); 1124 status = inb(info->ioaddr + UART_LSR); 1125 spin_unlock_irqrestore(&info->slock, flags); 1126 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0); 1127 return put_user(result, value); 1128 } 1129 1130 static int mxser_tiocmget(struct tty_struct *tty) 1131 { 1132 struct mxser_port *info = tty->driver_data; 1133 unsigned char control; 1134 unsigned long flags; 1135 u8 msr; 1136 1137 if (tty_io_error(tty)) 1138 return -EIO; 1139 1140 spin_lock_irqsave(&info->slock, flags); 1141 control = info->MCR; 1142 msr = mxser_check_modem_status(tty, info); 1143 spin_unlock_irqrestore(&info->slock, flags); 1144 1145 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) | 1146 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) | 1147 ((msr & UART_MSR_DCD) ? TIOCM_CAR : 0) | 1148 ((msr & UART_MSR_RI) ? TIOCM_RNG : 0) | 1149 ((msr & UART_MSR_DSR) ? TIOCM_DSR : 0) | 1150 ((msr & UART_MSR_CTS) ? TIOCM_CTS : 0); 1151 } 1152 1153 static int mxser_tiocmset(struct tty_struct *tty, 1154 unsigned int set, unsigned int clear) 1155 { 1156 struct mxser_port *info = tty->driver_data; 1157 unsigned long flags; 1158 1159 if (tty_io_error(tty)) 1160 return -EIO; 1161 1162 spin_lock_irqsave(&info->slock, flags); 1163 1164 if (set & TIOCM_RTS) 1165 info->MCR |= UART_MCR_RTS; 1166 if (set & TIOCM_DTR) 1167 info->MCR |= UART_MCR_DTR; 1168 1169 if (clear & TIOCM_RTS) 1170 info->MCR &= ~UART_MCR_RTS; 1171 if (clear & TIOCM_DTR) 1172 info->MCR &= ~UART_MCR_DTR; 1173 1174 outb(info->MCR, info->ioaddr + UART_MCR); 1175 spin_unlock_irqrestore(&info->slock, flags); 1176 return 0; 1177 } 1178 1179 static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg, 1180 struct async_icount *cprev) 1181 { 1182 struct async_icount cnow; 1183 unsigned long flags; 1184 int ret; 1185 1186 spin_lock_irqsave(&info->slock, flags); 1187 cnow = info->icount; /* atomic copy */ 1188 spin_unlock_irqrestore(&info->slock, flags); 1189 1190 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) || 1191 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) || 1192 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) || 1193 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts)); 1194 1195 *cprev = cnow; 1196 1197 return ret; 1198 } 1199 1200 /* We should likely switch to TIOCGRS485/TIOCSRS485. */ 1201 static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set, 1202 int __user *u_opmode) 1203 { 1204 int opmode, p = index % 4; 1205 int shiftbit = p * 2; 1206 u8 val; 1207 1208 if (port->board->must_hwid != MOXA_MUST_MU860_HWID) 1209 return -EFAULT; 1210 1211 if (set) { 1212 if (get_user(opmode, u_opmode)) 1213 return -EFAULT; 1214 1215 if (opmode & ~OP_MODE_MASK) 1216 return -EINVAL; 1217 1218 spin_lock_irq(&port->slock); 1219 val = inb(port->opmode_ioaddr); 1220 val &= ~(OP_MODE_MASK << shiftbit); 1221 val |= (opmode << shiftbit); 1222 outb(val, port->opmode_ioaddr); 1223 spin_unlock_irq(&port->slock); 1224 1225 return 0; 1226 } 1227 1228 spin_lock_irq(&port->slock); 1229 opmode = inb(port->opmode_ioaddr) >> shiftbit; 1230 spin_unlock_irq(&port->slock); 1231 1232 return put_user(opmode & OP_MODE_MASK, u_opmode); 1233 } 1234 1235 static int mxser_ioctl(struct tty_struct *tty, 1236 unsigned int cmd, unsigned long arg) 1237 { 1238 struct mxser_port *info = tty->driver_data; 1239 struct async_icount cnow; 1240 unsigned long flags; 1241 void __user *argp = (void __user *)arg; 1242 1243 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) 1244 return mxser_ioctl_op_mode(info, tty->index, 1245 cmd == MOXA_SET_OP_MODE, argp); 1246 1247 if (cmd != TIOCMIWAIT && tty_io_error(tty)) 1248 return -EIO; 1249 1250 switch (cmd) { 1251 case TIOCSERGETLSR: /* Get line status register */ 1252 return mxser_get_lsr_info(info, argp); 1253 /* 1254 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change 1255 * - mask passed in arg for lines of interest 1256 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) 1257 * Caller should use TIOCGICOUNT to see which one it was 1258 */ 1259 case TIOCMIWAIT: 1260 spin_lock_irqsave(&info->slock, flags); 1261 cnow = info->icount; /* note the counters on entry */ 1262 spin_unlock_irqrestore(&info->slock, flags); 1263 1264 return wait_event_interruptible(info->port.delta_msr_wait, 1265 mxser_cflags_changed(info, arg, &cnow)); 1266 default: 1267 return -ENOIOCTLCMD; 1268 } 1269 return 0; 1270 } 1271 1272 /* 1273 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) 1274 * Return: write counters to the user passed counter struct 1275 * NB: both 1->0 and 0->1 transitions are counted except for 1276 * RI where only 0->1 is counted. 1277 */ 1278 1279 static int mxser_get_icount(struct tty_struct *tty, 1280 struct serial_icounter_struct *icount) 1281 1282 { 1283 struct mxser_port *info = tty->driver_data; 1284 struct async_icount cnow; 1285 unsigned long flags; 1286 1287 spin_lock_irqsave(&info->slock, flags); 1288 cnow = info->icount; 1289 spin_unlock_irqrestore(&info->slock, flags); 1290 1291 icount->frame = cnow.frame; 1292 icount->brk = cnow.brk; 1293 icount->overrun = cnow.overrun; 1294 icount->buf_overrun = cnow.buf_overrun; 1295 icount->parity = cnow.parity; 1296 icount->rx = cnow.rx; 1297 icount->tx = cnow.tx; 1298 icount->cts = cnow.cts; 1299 icount->dsr = cnow.dsr; 1300 icount->rng = cnow.rng; 1301 icount->dcd = cnow.dcd; 1302 return 0; 1303 } 1304 1305 /* 1306 * This routine is called by the upper-layer tty layer to signal that 1307 * incoming characters should be throttled. 1308 */ 1309 static void mxser_throttle(struct tty_struct *tty) 1310 { 1311 struct mxser_port *info = tty->driver_data; 1312 1313 if (I_IXOFF(tty)) { 1314 if (info->board->must_hwid) { 1315 info->IER &= ~MOXA_MUST_RECV_ISR; 1316 outb(info->IER, info->ioaddr + UART_IER); 1317 } else { 1318 info->x_char = STOP_CHAR(tty); 1319 outb(0, info->ioaddr + UART_IER); 1320 info->IER |= UART_IER_THRI; 1321 outb(info->IER, info->ioaddr + UART_IER); 1322 } 1323 } 1324 1325 if (C_CRTSCTS(tty)) { 1326 info->MCR &= ~UART_MCR_RTS; 1327 outb(info->MCR, info->ioaddr + UART_MCR); 1328 } 1329 } 1330 1331 static void mxser_unthrottle(struct tty_struct *tty) 1332 { 1333 struct mxser_port *info = tty->driver_data; 1334 1335 /* startrx */ 1336 if (I_IXOFF(tty)) { 1337 if (info->x_char) 1338 info->x_char = 0; 1339 else { 1340 if (info->board->must_hwid) { 1341 info->IER |= MOXA_MUST_RECV_ISR; 1342 outb(info->IER, info->ioaddr + UART_IER); 1343 } else { 1344 info->x_char = START_CHAR(tty); 1345 outb(0, info->ioaddr + UART_IER); 1346 info->IER |= UART_IER_THRI; 1347 outb(info->IER, info->ioaddr + UART_IER); 1348 } 1349 } 1350 } 1351 1352 if (C_CRTSCTS(tty)) { 1353 info->MCR |= UART_MCR_RTS; 1354 outb(info->MCR, info->ioaddr + UART_MCR); 1355 } 1356 } 1357 1358 /* 1359 * mxser_stop() and mxser_start() 1360 * 1361 * This routines are called before setting or resetting tty->flow.stopped. 1362 * They enable or disable transmitter interrupts, as necessary. 1363 */ 1364 static void mxser_stop(struct tty_struct *tty) 1365 { 1366 struct mxser_port *info = tty->driver_data; 1367 unsigned long flags; 1368 1369 spin_lock_irqsave(&info->slock, flags); 1370 if (info->IER & UART_IER_THRI) 1371 __mxser_stop_tx(info); 1372 spin_unlock_irqrestore(&info->slock, flags); 1373 } 1374 1375 static void mxser_start(struct tty_struct *tty) 1376 { 1377 struct mxser_port *info = tty->driver_data; 1378 unsigned long flags; 1379 1380 spin_lock_irqsave(&info->slock, flags); 1381 if (info->xmit_cnt) 1382 __mxser_start_tx(info); 1383 spin_unlock_irqrestore(&info->slock, flags); 1384 } 1385 1386 static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios) 1387 { 1388 struct mxser_port *info = tty->driver_data; 1389 unsigned long flags; 1390 1391 spin_lock_irqsave(&info->slock, flags); 1392 mxser_change_speed(tty, old_termios); 1393 spin_unlock_irqrestore(&info->slock, flags); 1394 1395 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) { 1396 tty->hw_stopped = 0; 1397 mxser_start(tty); 1398 } 1399 1400 /* Handle sw stopped */ 1401 if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) { 1402 tty->flow.stopped = 0; 1403 1404 if (info->board->must_hwid) { 1405 spin_lock_irqsave(&info->slock, flags); 1406 mxser_must_set_rx_sw_flow_control(info->ioaddr, false); 1407 spin_unlock_irqrestore(&info->slock, flags); 1408 } 1409 1410 mxser_start(tty); 1411 } 1412 } 1413 1414 static bool mxser_tx_empty(struct mxser_port *info) 1415 { 1416 unsigned long flags; 1417 u8 lsr; 1418 1419 spin_lock_irqsave(&info->slock, flags); 1420 lsr = inb(info->ioaddr + UART_LSR); 1421 spin_unlock_irqrestore(&info->slock, flags); 1422 1423 return !(lsr & UART_LSR_TEMT); 1424 } 1425 1426 /* 1427 * mxser_wait_until_sent() --- wait until the transmitter is empty 1428 */ 1429 static void mxser_wait_until_sent(struct tty_struct *tty, int timeout) 1430 { 1431 struct mxser_port *info = tty->driver_data; 1432 unsigned long expire, char_time; 1433 1434 if (info->type == PORT_UNKNOWN) 1435 return; 1436 1437 if (info->xmit_fifo_size == 0) 1438 return; /* Just in case.... */ 1439 1440 /* 1441 * Set the check interval to be 1/5 of the estimated time to 1442 * send a single character, and make it at least 1. The check 1443 * interval should also be less than the timeout. 1444 * 1445 * Note: we have to use pretty tight timings here to satisfy 1446 * the NIST-PCTS. 1447 */ 1448 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size; 1449 char_time = char_time / 5; 1450 if (char_time == 0) 1451 char_time = 1; 1452 if (timeout && timeout < char_time) 1453 char_time = timeout; 1454 1455 char_time = jiffies_to_msecs(char_time); 1456 1457 /* 1458 * If the transmitter hasn't cleared in twice the approximate 1459 * amount of time to send the entire FIFO, it probably won't 1460 * ever clear. This assumes the UART isn't doing flow 1461 * control, which is currently the case. Hence, if it ever 1462 * takes longer than info->timeout, this is probably due to a 1463 * UART bug of some kind. So, we clamp the timeout parameter at 1464 * 2*info->timeout. 1465 */ 1466 if (!timeout || timeout > 2 * info->timeout) 1467 timeout = 2 * info->timeout; 1468 1469 expire = jiffies + timeout; 1470 1471 while (mxser_tx_empty(info)) { 1472 msleep_interruptible(char_time); 1473 if (signal_pending(current)) 1474 break; 1475 if (time_after(jiffies, expire)) 1476 break; 1477 } 1478 } 1479 1480 /* 1481 * This routine is called by tty_hangup() when a hangup is signaled. 1482 */ 1483 static void mxser_hangup(struct tty_struct *tty) 1484 { 1485 struct mxser_port *info = tty->driver_data; 1486 1487 mxser_flush_buffer(tty); 1488 tty_port_hangup(&info->port); 1489 } 1490 1491 /* 1492 * mxser_rs_break() --- routine which turns the break handling on or off 1493 */ 1494 static int mxser_rs_break(struct tty_struct *tty, int break_state) 1495 { 1496 struct mxser_port *info = tty->driver_data; 1497 unsigned long flags; 1498 u8 lcr; 1499 1500 spin_lock_irqsave(&info->slock, flags); 1501 lcr = inb(info->ioaddr + UART_LCR); 1502 if (break_state == -1) 1503 lcr |= UART_LCR_SBC; 1504 else 1505 lcr &= ~UART_LCR_SBC; 1506 outb(lcr, info->ioaddr + UART_LCR); 1507 spin_unlock_irqrestore(&info->slock, flags); 1508 1509 return 0; 1510 } 1511 1512 static bool mxser_receive_chars_new(struct mxser_port *port, u8 status) 1513 { 1514 enum mxser_must_hwid hwid = port->board->must_hwid; 1515 u8 gdl; 1516 1517 if (hwid == MOXA_OTHER_UART) 1518 return false; 1519 if (status & (UART_LSR_BRK_ERROR_BITS | MOXA_MUST_LSR_RERR)) 1520 return false; 1521 1522 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER); 1523 if (hwid == MOXA_MUST_MU150_HWID) 1524 gdl &= MOXA_MUST_GDL_MASK; 1525 1526 while (gdl--) { 1527 u8 ch = inb(port->ioaddr + UART_RX); 1528 if (!tty_insert_flip_char(&port->port, ch, 0)) 1529 port->icount.buf_overrun++; 1530 } 1531 1532 return true; 1533 } 1534 1535 static u8 mxser_receive_chars_old(struct tty_struct *tty, 1536 struct mxser_port *port, u8 status) 1537 { 1538 enum mxser_must_hwid hwid = port->board->must_hwid; 1539 int ignored = 0; 1540 int max = 256; 1541 u8 ch; 1542 1543 do { 1544 if (max-- < 0) 1545 break; 1546 1547 ch = inb(port->ioaddr + UART_RX); 1548 if (hwid && (status & UART_LSR_OE)) 1549 outb(port->FCR | UART_FCR_CLEAR_RCVR, 1550 port->ioaddr + UART_FCR); 1551 status &= port->read_status_mask; 1552 if (status & port->ignore_status_mask) { 1553 if (++ignored > 100) 1554 break; 1555 } else { 1556 char flag = 0; 1557 if (status & UART_LSR_BRK_ERROR_BITS) { 1558 if (status & UART_LSR_BI) { 1559 flag = TTY_BREAK; 1560 port->icount.brk++; 1561 1562 if (port->port.flags & ASYNC_SAK) 1563 do_SAK(tty); 1564 } else if (status & UART_LSR_PE) { 1565 flag = TTY_PARITY; 1566 port->icount.parity++; 1567 } else if (status & UART_LSR_FE) { 1568 flag = TTY_FRAME; 1569 port->icount.frame++; 1570 } else if (status & UART_LSR_OE) { 1571 flag = TTY_OVERRUN; 1572 port->icount.overrun++; 1573 } 1574 } 1575 if (!tty_insert_flip_char(&port->port, ch, flag)) { 1576 port->icount.buf_overrun++; 1577 break; 1578 } 1579 } 1580 1581 if (hwid) 1582 break; 1583 1584 status = inb(port->ioaddr + UART_LSR); 1585 } while (status & UART_LSR_DR); 1586 1587 return status; 1588 } 1589 1590 static u8 mxser_receive_chars(struct tty_struct *tty, 1591 struct mxser_port *port, u8 status) 1592 { 1593 if (!mxser_receive_chars_new(port, status)) 1594 status = mxser_receive_chars_old(tty, port, status); 1595 1596 tty_flip_buffer_push(&port->port); 1597 1598 return status; 1599 } 1600 1601 static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port) 1602 { 1603 int count; 1604 1605 if (port->x_char) { 1606 outb(port->x_char, port->ioaddr + UART_TX); 1607 port->x_char = 0; 1608 port->icount.tx++; 1609 return; 1610 } 1611 1612 if (!port->xmit_cnt || tty->flow.stopped || 1613 (tty->hw_stopped && !mxser_16550A_or_MUST(port))) { 1614 __mxser_stop_tx(port); 1615 return; 1616 } 1617 1618 count = port->xmit_fifo_size; 1619 do { 1620 outb(port->port.xmit_buf[port->xmit_tail++], 1621 port->ioaddr + UART_TX); 1622 port->xmit_tail &= SERIAL_XMIT_SIZE - 1; 1623 port->icount.tx++; 1624 if (!--port->xmit_cnt) 1625 break; 1626 } while (--count > 0); 1627 1628 if (port->xmit_cnt < WAKEUP_CHARS) 1629 tty_wakeup(tty); 1630 1631 if (!port->xmit_cnt) 1632 __mxser_stop_tx(port); 1633 } 1634 1635 static bool mxser_port_isr(struct mxser_port *port) 1636 { 1637 struct tty_struct *tty; 1638 u8 iir, status; 1639 bool error = false; 1640 1641 iir = inb(port->ioaddr + UART_IIR); 1642 if (iir & UART_IIR_NO_INT) 1643 return true; 1644 1645 iir &= MOXA_MUST_IIR_MASK; 1646 tty = tty_port_tty_get(&port->port); 1647 if (!tty) { 1648 status = inb(port->ioaddr + UART_LSR); 1649 outb(port->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 1650 port->ioaddr + UART_FCR); 1651 inb(port->ioaddr + UART_MSR); 1652 1653 error = true; 1654 goto put_tty; 1655 } 1656 1657 status = inb(port->ioaddr + UART_LSR); 1658 1659 if (port->board->must_hwid) { 1660 if (iir == MOXA_MUST_IIR_GDA || 1661 iir == MOXA_MUST_IIR_RDA || 1662 iir == MOXA_MUST_IIR_RTO || 1663 iir == MOXA_MUST_IIR_LSR) 1664 status = mxser_receive_chars(tty, port, status); 1665 } else { 1666 status &= port->read_status_mask; 1667 if (status & UART_LSR_DR) 1668 status = mxser_receive_chars(tty, port, status); 1669 } 1670 1671 mxser_check_modem_status(tty, port); 1672 1673 if (port->board->must_hwid) { 1674 if (iir == 0x02 && (status & UART_LSR_THRE)) 1675 mxser_transmit_chars(tty, port); 1676 } else { 1677 if (status & UART_LSR_THRE) 1678 mxser_transmit_chars(tty, port); 1679 } 1680 1681 put_tty: 1682 tty_kref_put(tty); 1683 1684 return error; 1685 } 1686 1687 /* 1688 * This is the serial driver's generic interrupt routine 1689 */ 1690 static irqreturn_t mxser_interrupt(int irq, void *dev_id) 1691 { 1692 struct mxser_board *brd = dev_id; 1693 struct mxser_port *port; 1694 unsigned int int_cnt, pass_counter = 0; 1695 unsigned int i, max = brd->nports; 1696 int handled = IRQ_NONE; 1697 u8 irqbits, bits, mask = BIT(max) - 1; 1698 1699 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) { 1700 irqbits = inb(brd->vector) & mask; 1701 if (irqbits == mask) 1702 break; 1703 1704 handled = IRQ_HANDLED; 1705 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) { 1706 if (irqbits == mask) 1707 break; 1708 if (bits & irqbits) 1709 continue; 1710 port = &brd->ports[i]; 1711 1712 int_cnt = 0; 1713 spin_lock(&port->slock); 1714 do { 1715 if (mxser_port_isr(port)) 1716 break; 1717 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT); 1718 spin_unlock(&port->slock); 1719 } 1720 } 1721 1722 return handled; 1723 } 1724 1725 static const struct tty_operations mxser_ops = { 1726 .open = mxser_open, 1727 .close = mxser_close, 1728 .write = mxser_write, 1729 .put_char = mxser_put_char, 1730 .flush_chars = mxser_flush_chars, 1731 .write_room = mxser_write_room, 1732 .chars_in_buffer = mxser_chars_in_buffer, 1733 .flush_buffer = mxser_flush_buffer, 1734 .ioctl = mxser_ioctl, 1735 .throttle = mxser_throttle, 1736 .unthrottle = mxser_unthrottle, 1737 .set_termios = mxser_set_termios, 1738 .stop = mxser_stop, 1739 .start = mxser_start, 1740 .hangup = mxser_hangup, 1741 .break_ctl = mxser_rs_break, 1742 .wait_until_sent = mxser_wait_until_sent, 1743 .tiocmget = mxser_tiocmget, 1744 .tiocmset = mxser_tiocmset, 1745 .set_serial = mxser_set_serial_info, 1746 .get_serial = mxser_get_serial_info, 1747 .get_icount = mxser_get_icount, 1748 }; 1749 1750 static const struct tty_port_operations mxser_port_ops = { 1751 .carrier_raised = mxser_carrier_raised, 1752 .dtr_rts = mxser_dtr_rts, 1753 .activate = mxser_activate, 1754 .shutdown = mxser_shutdown_port, 1755 }; 1756 1757 /* 1758 * The MOXA Smartio/Industio serial driver boot-time initialization code! 1759 */ 1760 1761 static void mxser_initbrd(struct mxser_board *brd, bool high_baud) 1762 { 1763 struct mxser_port *info; 1764 unsigned int i; 1765 bool is_mu860; 1766 1767 brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr); 1768 is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID; 1769 1770 for (i = 0; i < UART_INFO_NUM; i++) { 1771 if (Gpci_uart_info[i].type == brd->must_hwid) { 1772 brd->max_baud = Gpci_uart_info[i].max_baud; 1773 1774 /* exception....CP-102 */ 1775 if (high_baud) 1776 brd->max_baud = 921600; 1777 break; 1778 } 1779 } 1780 1781 if (is_mu860) { 1782 /* set to RS232 mode by default */ 1783 outb(0, brd->vector + 4); 1784 outb(0, brd->vector + 0x0c); 1785 } 1786 1787 for (i = 0; i < brd->nports; i++) { 1788 info = &brd->ports[i]; 1789 if (is_mu860) { 1790 if (i < 4) 1791 info->opmode_ioaddr = brd->vector + 4; 1792 else 1793 info->opmode_ioaddr = brd->vector + 0x0c; 1794 } 1795 tty_port_init(&info->port); 1796 info->port.ops = &mxser_port_ops; 1797 info->board = brd; 1798 1799 /* Enhance mode enabled here */ 1800 if (brd->must_hwid != MOXA_OTHER_UART) 1801 mxser_must_set_enhance_mode(info->ioaddr, true); 1802 1803 info->type = PORT_16550A; 1804 1805 mxser_process_txrx_fifo(info); 1806 1807 info->port.close_delay = 5 * HZ / 10; 1808 info->port.closing_wait = 30 * HZ; 1809 spin_lock_init(&info->slock); 1810 1811 /* before set INT ISR, disable all int */ 1812 outb(inb(info->ioaddr + UART_IER) & 0xf0, 1813 info->ioaddr + UART_IER); 1814 } 1815 } 1816 1817 static int mxser_probe(struct pci_dev *pdev, 1818 const struct pci_device_id *ent) 1819 { 1820 struct mxser_board *brd; 1821 unsigned int i, base; 1822 unsigned long ioaddress; 1823 unsigned short nports = MXSER_NPORTS(ent->driver_data); 1824 struct device *tty_dev; 1825 int retval = -EINVAL; 1826 1827 i = find_first_zero_bit(mxser_boards, MXSER_BOARDS); 1828 if (i >= MXSER_BOARDS) { 1829 dev_err(&pdev->dev, "too many boards found (maximum %d), board " 1830 "not configured\n", MXSER_BOARDS); 1831 goto err; 1832 } 1833 1834 brd = devm_kzalloc(&pdev->dev, struct_size(brd, ports, nports), 1835 GFP_KERNEL); 1836 if (!brd) 1837 goto err; 1838 1839 brd->idx = i; 1840 __set_bit(brd->idx, mxser_boards); 1841 base = i * MXSER_PORTS_PER_BOARD; 1842 1843 retval = pcim_enable_device(pdev); 1844 if (retval) { 1845 dev_err(&pdev->dev, "PCI enable failed\n"); 1846 goto err_zero; 1847 } 1848 1849 /* io address */ 1850 ioaddress = pci_resource_start(pdev, 2); 1851 retval = pci_request_region(pdev, 2, "mxser(IO)"); 1852 if (retval) 1853 goto err_zero; 1854 1855 brd->nports = nports; 1856 for (i = 0; i < nports; i++) 1857 brd->ports[i].ioaddr = ioaddress + 8 * i; 1858 1859 /* vector */ 1860 ioaddress = pci_resource_start(pdev, 3); 1861 retval = pci_request_region(pdev, 3, "mxser(vector)"); 1862 if (retval) 1863 goto err_zero; 1864 brd->vector = ioaddress; 1865 1866 /* irq */ 1867 brd->irq = pdev->irq; 1868 1869 mxser_initbrd(brd, ent->driver_data & MXSER_HIGHBAUD); 1870 1871 retval = devm_request_irq(&pdev->dev, brd->irq, mxser_interrupt, 1872 IRQF_SHARED, "mxser", brd); 1873 if (retval) { 1874 dev_err(&pdev->dev, "request irq failed"); 1875 goto err_relbrd; 1876 } 1877 1878 for (i = 0; i < nports; i++) { 1879 tty_dev = tty_port_register_device(&brd->ports[i].port, 1880 mxvar_sdriver, base + i, &pdev->dev); 1881 if (IS_ERR(tty_dev)) { 1882 retval = PTR_ERR(tty_dev); 1883 for (; i > 0; i--) 1884 tty_unregister_device(mxvar_sdriver, 1885 base + i - 1); 1886 goto err_relbrd; 1887 } 1888 } 1889 1890 pci_set_drvdata(pdev, brd); 1891 1892 return 0; 1893 err_relbrd: 1894 for (i = 0; i < nports; i++) 1895 tty_port_destroy(&brd->ports[i].port); 1896 err_zero: 1897 __clear_bit(brd->idx, mxser_boards); 1898 err: 1899 return retval; 1900 } 1901 1902 static void mxser_remove(struct pci_dev *pdev) 1903 { 1904 struct mxser_board *brd = pci_get_drvdata(pdev); 1905 unsigned int i, base = brd->idx * MXSER_PORTS_PER_BOARD; 1906 1907 for (i = 0; i < brd->nports; i++) { 1908 tty_unregister_device(mxvar_sdriver, base + i); 1909 tty_port_destroy(&brd->ports[i].port); 1910 } 1911 1912 __clear_bit(brd->idx, mxser_boards); 1913 } 1914 1915 static struct pci_driver mxser_driver = { 1916 .name = "mxser", 1917 .id_table = mxser_pcibrds, 1918 .probe = mxser_probe, 1919 .remove = mxser_remove 1920 }; 1921 1922 static int __init mxser_module_init(void) 1923 { 1924 int retval; 1925 1926 mxvar_sdriver = tty_alloc_driver(MXSER_PORTS, TTY_DRIVER_REAL_RAW | 1927 TTY_DRIVER_DYNAMIC_DEV); 1928 if (IS_ERR(mxvar_sdriver)) 1929 return PTR_ERR(mxvar_sdriver); 1930 1931 /* Initialize the tty_driver structure */ 1932 mxvar_sdriver->name = "ttyMI"; 1933 mxvar_sdriver->major = ttymajor; 1934 mxvar_sdriver->minor_start = 0; 1935 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL; 1936 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL; 1937 mxvar_sdriver->init_termios = tty_std_termios; 1938 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL; 1939 tty_set_operations(mxvar_sdriver, &mxser_ops); 1940 1941 retval = tty_register_driver(mxvar_sdriver); 1942 if (retval) { 1943 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family " 1944 "tty driver !\n"); 1945 goto err_put; 1946 } 1947 1948 retval = pci_register_driver(&mxser_driver); 1949 if (retval) { 1950 printk(KERN_ERR "mxser: can't register pci driver\n"); 1951 goto err_unr; 1952 } 1953 1954 return 0; 1955 err_unr: 1956 tty_unregister_driver(mxvar_sdriver); 1957 err_put: 1958 tty_driver_kref_put(mxvar_sdriver); 1959 return retval; 1960 } 1961 1962 static void __exit mxser_module_exit(void) 1963 { 1964 pci_unregister_driver(&mxser_driver); 1965 tty_unregister_driver(mxvar_sdriver); 1966 tty_driver_kref_put(mxvar_sdriver); 1967 } 1968 1969 module_init(mxser_module_init); 1970 module_exit(mxser_module_exit); 1971