1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * mxser.c -- MOXA Smartio/Industio family multiport serial driver. 4 * 5 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com). 6 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com> 7 * 8 * This code is loosely based on the 1.8 moxa driver which is based on 9 * Linux serial driver, written by Linus Torvalds, Theodore T'so and 10 * others. 11 * 12 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox 13 * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on 14 * www.moxa.com. 15 * - Fixed x86_64 cleanness 16 */ 17 18 #include <linux/module.h> 19 #include <linux/errno.h> 20 #include <linux/signal.h> 21 #include <linux/sched.h> 22 #include <linux/timer.h> 23 #include <linux/interrupt.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/serial.h> 27 #include <linux/serial_reg.h> 28 #include <linux/major.h> 29 #include <linux/string.h> 30 #include <linux/fcntl.h> 31 #include <linux/ptrace.h> 32 #include <linux/ioport.h> 33 #include <linux/mm.h> 34 #include <linux/delay.h> 35 #include <linux/pci.h> 36 #include <linux/bitops.h> 37 #include <linux/slab.h> 38 #include <linux/ratelimit.h> 39 40 #include <asm/io.h> 41 #include <asm/irq.h> 42 #include <linux/uaccess.h> 43 44 /* 45 * Semi-public control interfaces 46 */ 47 48 /* 49 * MOXA ioctls 50 */ 51 52 #define MOXA 0x400 53 #define MOXA_SET_OP_MODE (MOXA + 66) 54 #define MOXA_GET_OP_MODE (MOXA + 67) 55 56 #define RS232_MODE 0 57 #define RS485_2WIRE_MODE 1 58 #define RS422_MODE 2 59 #define RS485_4WIRE_MODE 3 60 #define OP_MODE_MASK 3 61 62 /* --------------------------------------------------- */ 63 64 /* 65 * Follow just what Moxa Must chip defines. 66 * 67 * When LCR register (offset 0x03) is written the following value, the Must chip 68 * will enter enhanced mode. And a write to EFR (offset 0x02) bit 6,7 will 69 * change bank. 70 */ 71 #define MOXA_MUST_ENTER_ENHANCED 0xBF 72 73 /* when enhanced mode is enabled, access to general bank register */ 74 #define MOXA_MUST_GDL_REGISTER 0x07 75 #define MOXA_MUST_GDL_MASK 0x7F 76 #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 77 78 #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */ 79 /* enhanced register bank select and enhanced mode setting register */ 80 /* This works only when LCR register equals to 0xBF */ 81 #define MOXA_MUST_EFR_REGISTER 0x02 82 #define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enhanced mode enable */ 83 /* enhanced register bank set 0, 1, 2 */ 84 #define MOXA_MUST_EFR_BANK0 0x00 85 #define MOXA_MUST_EFR_BANK1 0x40 86 #define MOXA_MUST_EFR_BANK2 0x80 87 #define MOXA_MUST_EFR_BANK3 0xC0 88 #define MOXA_MUST_EFR_BANK_MASK 0xC0 89 90 /* set XON1 value register, when LCR=0xBF and change to bank0 */ 91 #define MOXA_MUST_XON1_REGISTER 0x04 92 93 /* set XON2 value register, when LCR=0xBF and change to bank0 */ 94 #define MOXA_MUST_XON2_REGISTER 0x05 95 96 /* set XOFF1 value register, when LCR=0xBF and change to bank0 */ 97 #define MOXA_MUST_XOFF1_REGISTER 0x06 98 99 /* set XOFF2 value register, when LCR=0xBF and change to bank0 */ 100 #define MOXA_MUST_XOFF2_REGISTER 0x07 101 102 #define MOXA_MUST_RBRTL_REGISTER 0x04 103 #define MOXA_MUST_RBRTH_REGISTER 0x05 104 #define MOXA_MUST_RBRTI_REGISTER 0x06 105 #define MOXA_MUST_THRTL_REGISTER 0x07 106 #define MOXA_MUST_ENUM_REGISTER 0x04 107 #define MOXA_MUST_HWID_REGISTER 0x05 108 #define MOXA_MUST_ECR_REGISTER 0x06 109 #define MOXA_MUST_CSR_REGISTER 0x07 110 111 #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */ 112 #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */ 113 114 #define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */ 115 #define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */ 116 #define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */ 117 #define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */ 118 119 #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) 120 121 /* GDA interrupt pending */ 122 #define MOXA_MUST_IIR_GDA 0x1C 123 #define MOXA_MUST_IIR_RDA 0x04 124 #define MOXA_MUST_IIR_RTO 0x0C 125 #define MOXA_MUST_IIR_LSR 0x06 126 127 /* received Xon/Xoff or specical interrupt pending */ 128 #define MOXA_MUST_IIR_XSC 0x10 129 130 /* RTS/CTS change state interrupt pending */ 131 #define MOXA_MUST_IIR_RTSCTS 0x20 132 #define MOXA_MUST_IIR_MASK 0x3E 133 134 #define MOXA_MUST_MCR_XON_FLAG 0x40 135 #define MOXA_MUST_MCR_XON_ANY 0x80 136 #define MOXA_MUST_MCR_TX_XON 0x08 137 138 #define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */ 139 #define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */ 140 #define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */ 141 #define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */ 142 #define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */ 143 #define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */ 144 #define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */ 145 #define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */ 146 #define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */ 147 #define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */ 148 #define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */ 149 150 #define MXSERMAJOR 174 151 152 #define MXSER_BOARDS 4 /* Max. boards */ 153 #define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */ 154 #define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD) 155 #define MXSER_ISR_PASS_LIMIT 100 156 157 #define WAKEUP_CHARS 256 158 159 #define MXSER_BAUD_BASE 921600 160 #define MXSER_CUSTOM_DIVISOR (MXSER_BAUD_BASE * 16) 161 162 #define PCI_DEVICE_ID_POS104UL 0x1044 163 #define PCI_DEVICE_ID_CB108 0x1080 164 #define PCI_DEVICE_ID_CP102UF 0x1023 165 #define PCI_DEVICE_ID_CP112UL 0x1120 166 #define PCI_DEVICE_ID_CB114 0x1142 167 #define PCI_DEVICE_ID_CP114UL 0x1143 168 #define PCI_DEVICE_ID_CB134I 0x1341 169 #define PCI_DEVICE_ID_CP138U 0x1380 170 171 #define MXSER_NPORTS(ddata) ((ddata) & 0xffU) 172 #define MXSER_HIGHBAUD 0x0100 173 174 enum mxser_must_hwid { 175 MOXA_OTHER_UART = 0x00, 176 MOXA_MUST_MU150_HWID = 0x01, 177 MOXA_MUST_MU860_HWID = 0x02, 178 }; 179 180 static const struct { 181 u8 type; 182 u8 fifo_size; 183 u8 rx_high_water; 184 u8 rx_low_water; 185 speed_t max_baud; 186 } Gpci_uart_info[] = { 187 { MOXA_OTHER_UART, 16, 14, 1, 921600 }, 188 { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 }, 189 { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 } 190 }; 191 #define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info) 192 193 194 /* driver_data correspond to the lines in the structure above 195 see also ISA probe function before you change something */ 196 static const struct pci_device_id mxser_pcibrds[] = { 197 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C168), .driver_data = 8 }, 198 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_C104), .driver_data = 4 }, 199 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132), .driver_data = 2 }, 200 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP114), .driver_data = 4 }, 201 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CT114), .driver_data = 4 }, 202 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102), .driver_data = 2 | MXSER_HIGHBAUD }, 203 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104U), .driver_data = 4 }, 204 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168U), .driver_data = 8 }, 205 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP132U), .driver_data = 2 }, 206 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP134U), .driver_data = 4 }, 207 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104JU),.driver_data = 4 }, 208 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_RC7000), .driver_data = 8 }, /* RC7000 */ 209 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118U), .driver_data = 8 }, 210 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102UL),.driver_data = 2 }, 211 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP102U), .driver_data = 2 }, 212 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP118EL),.driver_data = 8 }, 213 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP168EL),.driver_data = 8 }, 214 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_MOXA_CP104EL),.driver_data = 4 }, 215 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB108), .driver_data = 8 }, 216 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB114), .driver_data = 4 }, 217 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CB134I), .driver_data = 4 }, 218 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP138U), .driver_data = 8 }, 219 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_POS104UL), .driver_data = 4 }, 220 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP114UL), .driver_data = 4 }, 221 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP102UF), .driver_data = 2 }, 222 { PCI_VDEVICE(MOXA, PCI_DEVICE_ID_CP112UL), .driver_data = 2 }, 223 { } 224 }; 225 MODULE_DEVICE_TABLE(pci, mxser_pcibrds); 226 227 static int ttymajor = MXSERMAJOR; 228 229 /* Variables for insmod */ 230 231 MODULE_AUTHOR("Casper Yang"); 232 MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver"); 233 module_param(ttymajor, int, 0); 234 MODULE_LICENSE("GPL"); 235 236 struct mxser_board; 237 238 struct mxser_port { 239 struct tty_port port; 240 struct mxser_board *board; 241 242 unsigned long ioaddr; 243 unsigned long opmode_ioaddr; 244 245 u8 rx_high_water; 246 u8 rx_low_water; 247 int type; /* UART type */ 248 249 unsigned char x_char; /* xon/xoff character */ 250 u8 IER; /* Interrupt Enable Register */ 251 u8 MCR; /* Modem control register */ 252 253 unsigned char ldisc_stop_rx; 254 255 struct async_icount icount; /* kernel counters for 4 input interrupts */ 256 unsigned int timeout; 257 258 u8 read_status_mask; 259 u8 ignore_status_mask; 260 u8 xmit_fifo_size; 261 unsigned int xmit_head; 262 unsigned int xmit_tail; 263 unsigned int xmit_cnt; 264 int closing; 265 266 spinlock_t slock; 267 }; 268 269 struct mxser_board { 270 unsigned int idx; 271 unsigned short nports; 272 int irq; 273 unsigned long vector; 274 275 enum mxser_must_hwid must_hwid; 276 speed_t max_baud; 277 278 struct mxser_port ports[]; 279 }; 280 281 static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS); 282 static struct tty_driver *mxvar_sdriver; 283 284 static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set, 285 bool restore_LCR) 286 { 287 u8 oldlcr, efr; 288 289 oldlcr = inb(baseio + UART_LCR); 290 outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR); 291 292 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 293 efr &= ~clear; 294 efr |= set; 295 296 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 297 298 if (restore_LCR) 299 outb(oldlcr, baseio + UART_LCR); 300 301 return oldlcr; 302 } 303 304 static u8 mxser_must_select_bank(unsigned long baseio, u8 bank) 305 { 306 return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank, 307 false); 308 } 309 310 static void mxser_set_must_xon1_value(unsigned long baseio, u8 value) 311 { 312 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); 313 outb(value, baseio + MOXA_MUST_XON1_REGISTER); 314 outb(oldlcr, baseio + UART_LCR); 315 } 316 317 static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value) 318 { 319 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); 320 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER); 321 outb(oldlcr, baseio + UART_LCR); 322 } 323 324 static void mxser_set_must_fifo_value(struct mxser_port *info) 325 { 326 u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1); 327 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER); 328 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER); 329 outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER); 330 outb(oldlcr, info->ioaddr + UART_LCR); 331 } 332 333 static void mxser_set_must_enum_value(unsigned long baseio, u8 value) 334 { 335 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); 336 outb(value, baseio + MOXA_MUST_ENUM_REGISTER); 337 outb(oldlcr, baseio + UART_LCR); 338 } 339 340 static u8 mxser_get_must_hardware_id(unsigned long baseio) 341 { 342 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); 343 u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER); 344 outb(oldlcr, baseio + UART_LCR); 345 346 return id; 347 } 348 349 static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set) 350 { 351 __mxser_must_set_EFR(baseio, clear, set, true); 352 } 353 354 static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable) 355 { 356 mxser_must_set_EFR(baseio, 357 enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE, 358 enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0); 359 } 360 361 static void mxser_must_no_sw_flow_control(unsigned long baseio) 362 { 363 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0); 364 } 365 366 static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable) 367 { 368 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK, 369 enable ? MOXA_MUST_EFR_SF_TX1 : 0); 370 } 371 372 static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable) 373 { 374 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK, 375 enable ? MOXA_MUST_EFR_SF_RX1 : 0); 376 } 377 378 static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io) 379 { 380 u8 oldmcr, hwid; 381 int i; 382 383 outb(0, io + UART_LCR); 384 mxser_must_set_enhance_mode(io, false); 385 oldmcr = inb(io + UART_MCR); 386 outb(0, io + UART_MCR); 387 mxser_set_must_xon1_value(io, 0x11); 388 if ((hwid = inb(io + UART_MCR)) != 0) { 389 outb(oldmcr, io + UART_MCR); 390 return MOXA_OTHER_UART; 391 } 392 393 hwid = mxser_get_must_hardware_id(io); 394 for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */ 395 if (hwid == Gpci_uart_info[i].type) 396 return hwid; 397 398 return MOXA_OTHER_UART; 399 } 400 401 static bool mxser_16550A_or_MUST(struct mxser_port *info) 402 { 403 return info->type == PORT_16550A || info->board->must_hwid; 404 } 405 406 static void mxser_process_txrx_fifo(struct mxser_port *info) 407 { 408 unsigned int i; 409 410 if (info->type == PORT_16450 || info->type == PORT_8250) { 411 info->rx_high_water = 1; 412 info->rx_low_water = 1; 413 info->xmit_fifo_size = 1; 414 return; 415 } 416 417 for (i = 0; i < UART_INFO_NUM; i++) 418 if (info->board->must_hwid == Gpci_uart_info[i].type) { 419 info->rx_low_water = Gpci_uart_info[i].rx_low_water; 420 info->rx_high_water = Gpci_uart_info[i].rx_high_water; 421 info->xmit_fifo_size = Gpci_uart_info[i].fifo_size; 422 break; 423 } 424 } 425 426 static void __mxser_start_tx(struct mxser_port *info) 427 { 428 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); 429 info->IER |= UART_IER_THRI; 430 outb(info->IER, info->ioaddr + UART_IER); 431 } 432 433 static void mxser_start_tx(struct mxser_port *info) 434 { 435 unsigned long flags; 436 437 spin_lock_irqsave(&info->slock, flags); 438 __mxser_start_tx(info); 439 spin_unlock_irqrestore(&info->slock, flags); 440 } 441 442 static void __mxser_stop_tx(struct mxser_port *info) 443 { 444 info->IER &= ~UART_IER_THRI; 445 outb(info->IER, info->ioaddr + UART_IER); 446 } 447 448 static int mxser_carrier_raised(struct tty_port *port) 449 { 450 struct mxser_port *mp = container_of(port, struct mxser_port, port); 451 return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0; 452 } 453 454 static void mxser_dtr_rts(struct tty_port *port, int on) 455 { 456 struct mxser_port *mp = container_of(port, struct mxser_port, port); 457 unsigned long flags; 458 u8 mcr; 459 460 spin_lock_irqsave(&mp->slock, flags); 461 mcr = inb(mp->ioaddr + UART_MCR); 462 if (on) 463 mcr |= UART_MCR_DTR | UART_MCR_RTS; 464 else 465 mcr &= ~(UART_MCR_DTR | UART_MCR_RTS); 466 outb(mcr, mp->ioaddr + UART_MCR); 467 spin_unlock_irqrestore(&mp->slock, flags); 468 } 469 470 static int mxser_set_baud(struct tty_struct *tty, speed_t newspd) 471 { 472 struct mxser_port *info = tty->driver_data; 473 unsigned int quot = 0, baud; 474 unsigned char cval; 475 u64 timeout; 476 477 if (newspd > info->board->max_baud) 478 return -1; 479 480 if (newspd == 134) { 481 quot = 2 * MXSER_BAUD_BASE / 269; 482 tty_encode_baud_rate(tty, 134, 134); 483 } else if (newspd) { 484 quot = MXSER_BAUD_BASE / newspd; 485 if (quot == 0) 486 quot = 1; 487 baud = MXSER_BAUD_BASE / quot; 488 tty_encode_baud_rate(tty, baud, baud); 489 } else { 490 quot = 0; 491 } 492 493 /* 494 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the 495 * u64 domain 496 */ 497 timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot; 498 do_div(timeout, MXSER_BAUD_BASE); 499 info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */ 500 501 if (quot) { 502 info->MCR |= UART_MCR_DTR; 503 outb(info->MCR, info->ioaddr + UART_MCR); 504 } else { 505 info->MCR &= ~UART_MCR_DTR; 506 outb(info->MCR, info->ioaddr + UART_MCR); 507 return 0; 508 } 509 510 cval = inb(info->ioaddr + UART_LCR); 511 512 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */ 513 514 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */ 515 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */ 516 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */ 517 518 #ifdef BOTHER 519 if (C_BAUD(tty) == BOTHER) { 520 quot = MXSER_BAUD_BASE % newspd; 521 quot *= 8; 522 if (quot % newspd > newspd / 2) { 523 quot /= newspd; 524 quot++; 525 } else 526 quot /= newspd; 527 528 mxser_set_must_enum_value(info->ioaddr, quot); 529 } else 530 #endif 531 mxser_set_must_enum_value(info->ioaddr, 0); 532 533 return 0; 534 } 535 536 static void mxser_handle_cts(struct tty_struct *tty, struct mxser_port *info, 537 u8 msr) 538 { 539 bool cts = msr & UART_MSR_CTS; 540 541 if (tty->hw_stopped) { 542 if (cts) { 543 tty->hw_stopped = 0; 544 545 if (!mxser_16550A_or_MUST(info)) 546 __mxser_start_tx(info); 547 tty_wakeup(tty); 548 } 549 return; 550 } else if (cts) 551 return; 552 553 tty->hw_stopped = 1; 554 if (!mxser_16550A_or_MUST(info)) 555 __mxser_stop_tx(info); 556 } 557 558 /* 559 * This routine is called to set the UART divisor registers to match 560 * the specified baud rate for a serial port. 561 */ 562 static void mxser_change_speed(struct tty_struct *tty) 563 { 564 struct mxser_port *info = tty->driver_data; 565 unsigned cflag, cval, fcr; 566 567 cflag = tty->termios.c_cflag; 568 569 mxser_set_baud(tty, tty_get_baud_rate(tty)); 570 571 /* byte size and parity */ 572 switch (cflag & CSIZE) { 573 default: 574 case CS5: 575 cval = UART_LCR_WLEN5; 576 break; 577 case CS6: 578 cval = UART_LCR_WLEN6; 579 break; 580 case CS7: 581 cval = UART_LCR_WLEN7; 582 break; 583 case CS8: 584 cval = UART_LCR_WLEN8; 585 break; 586 } 587 588 if (cflag & CSTOPB) 589 cval |= UART_LCR_STOP; 590 if (cflag & PARENB) 591 cval |= UART_LCR_PARITY; 592 if (!(cflag & PARODD)) 593 cval |= UART_LCR_EPAR; 594 if (cflag & CMSPAR) 595 cval |= UART_LCR_SPAR; 596 597 if ((info->type == PORT_8250) || (info->type == PORT_16450)) { 598 if (info->board->must_hwid) { 599 fcr = UART_FCR_ENABLE_FIFO; 600 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; 601 mxser_set_must_fifo_value(info); 602 } else 603 fcr = 0; 604 } else { 605 fcr = UART_FCR_ENABLE_FIFO; 606 if (info->board->must_hwid) { 607 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; 608 mxser_set_must_fifo_value(info); 609 } else { 610 switch (info->rx_high_water) { 611 case 1: 612 fcr |= UART_FCR_TRIGGER_1; 613 break; 614 case 4: 615 fcr |= UART_FCR_TRIGGER_4; 616 break; 617 case 8: 618 fcr |= UART_FCR_TRIGGER_8; 619 break; 620 default: 621 fcr |= UART_FCR_TRIGGER_14; 622 break; 623 } 624 } 625 } 626 627 /* CTS flow control flag and modem status interrupts */ 628 info->IER &= ~UART_IER_MSI; 629 info->MCR &= ~UART_MCR_AFE; 630 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS); 631 if (cflag & CRTSCTS) { 632 info->IER |= UART_IER_MSI; 633 if (mxser_16550A_or_MUST(info)) { 634 info->MCR |= UART_MCR_AFE; 635 } else { 636 mxser_handle_cts(tty, info, 637 inb(info->ioaddr + UART_MSR)); 638 } 639 } 640 outb(info->MCR, info->ioaddr + UART_MCR); 641 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL); 642 if (~cflag & CLOCAL) 643 info->IER |= UART_IER_MSI; 644 outb(info->IER, info->ioaddr + UART_IER); 645 646 /* 647 * Set up parity check flag 648 */ 649 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 650 if (I_INPCK(tty)) 651 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 652 if (I_BRKINT(tty) || I_PARMRK(tty)) 653 info->read_status_mask |= UART_LSR_BI; 654 655 info->ignore_status_mask = 0; 656 657 if (I_IGNBRK(tty)) { 658 info->ignore_status_mask |= UART_LSR_BI; 659 info->read_status_mask |= UART_LSR_BI; 660 /* 661 * If we're ignore parity and break indicators, ignore 662 * overruns too. (For real raw support). 663 */ 664 if (I_IGNPAR(tty)) { 665 info->ignore_status_mask |= 666 UART_LSR_OE | 667 UART_LSR_PE | 668 UART_LSR_FE; 669 info->read_status_mask |= 670 UART_LSR_OE | 671 UART_LSR_PE | 672 UART_LSR_FE; 673 } 674 } 675 if (info->board->must_hwid) { 676 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty)); 677 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty)); 678 mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty)); 679 mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty)); 680 } 681 682 683 outb(fcr, info->ioaddr + UART_FCR); /* set fcr */ 684 outb(cval, info->ioaddr + UART_LCR); 685 } 686 687 static void mxser_check_modem_status(struct tty_struct *tty, 688 struct mxser_port *port, int status) 689 { 690 /* update input line counters */ 691 if (status & UART_MSR_TERI) 692 port->icount.rng++; 693 if (status & UART_MSR_DDSR) 694 port->icount.dsr++; 695 if (status & UART_MSR_DDCD) 696 port->icount.dcd++; 697 if (status & UART_MSR_DCTS) 698 port->icount.cts++; 699 wake_up_interruptible(&port->port.delta_msr_wait); 700 701 if (tty_port_check_carrier(&port->port) && (status & UART_MSR_DDCD)) { 702 if (status & UART_MSR_DCD) 703 wake_up_interruptible(&port->port.open_wait); 704 } 705 706 if (tty_port_cts_enabled(&port->port)) 707 mxser_handle_cts(tty, port, status); 708 } 709 710 static int mxser_activate(struct tty_port *port, struct tty_struct *tty) 711 { 712 struct mxser_port *info = container_of(port, struct mxser_port, port); 713 unsigned long page; 714 unsigned long flags; 715 716 page = __get_free_page(GFP_KERNEL); 717 if (!page) 718 return -ENOMEM; 719 720 spin_lock_irqsave(&info->slock, flags); 721 722 if (!info->type) { 723 set_bit(TTY_IO_ERROR, &tty->flags); 724 free_page(page); 725 spin_unlock_irqrestore(&info->slock, flags); 726 return 0; 727 } 728 info->port.xmit_buf = (unsigned char *) page; 729 730 /* 731 * Clear the FIFO buffers and disable them 732 * (they will be reenabled in mxser_change_speed()) 733 */ 734 if (info->board->must_hwid) 735 outb((UART_FCR_CLEAR_RCVR | 736 UART_FCR_CLEAR_XMIT | 737 MOXA_MUST_FCR_GDA_MODE_ENABLE), info->ioaddr + UART_FCR); 738 else 739 outb((UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), 740 info->ioaddr + UART_FCR); 741 742 /* 743 * At this point there's no way the LSR could still be 0xFF; 744 * if it is, then bail out, because there's likely no UART 745 * here. 746 */ 747 if (inb(info->ioaddr + UART_LSR) == 0xff) { 748 spin_unlock_irqrestore(&info->slock, flags); 749 if (capable(CAP_SYS_ADMIN)) { 750 set_bit(TTY_IO_ERROR, &tty->flags); 751 return 0; 752 } else 753 return -ENODEV; 754 } 755 756 /* 757 * Clear the interrupt registers. 758 */ 759 (void) inb(info->ioaddr + UART_LSR); 760 (void) inb(info->ioaddr + UART_RX); 761 (void) inb(info->ioaddr + UART_IIR); 762 (void) inb(info->ioaddr + UART_MSR); 763 764 /* 765 * Now, initialize the UART 766 */ 767 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */ 768 info->MCR = UART_MCR_DTR | UART_MCR_RTS; 769 outb(info->MCR, info->ioaddr + UART_MCR); 770 771 /* 772 * Finally, enable interrupts 773 */ 774 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; 775 776 if (info->board->must_hwid) 777 info->IER |= MOXA_MUST_IER_EGDAI; 778 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */ 779 780 /* 781 * And clear the interrupt registers again for luck. 782 */ 783 (void) inb(info->ioaddr + UART_LSR); 784 (void) inb(info->ioaddr + UART_RX); 785 (void) inb(info->ioaddr + UART_IIR); 786 (void) inb(info->ioaddr + UART_MSR); 787 788 clear_bit(TTY_IO_ERROR, &tty->flags); 789 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; 790 791 /* 792 * and set the speed of the serial port 793 */ 794 mxser_change_speed(tty); 795 spin_unlock_irqrestore(&info->slock, flags); 796 797 return 0; 798 } 799 800 /* 801 * This routine will shutdown a serial port 802 */ 803 static void mxser_shutdown_port(struct tty_port *port) 804 { 805 struct mxser_port *info = container_of(port, struct mxser_port, port); 806 unsigned long flags; 807 808 spin_lock_irqsave(&info->slock, flags); 809 810 /* 811 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq 812 * here so the queue might never be waken up 813 */ 814 wake_up_interruptible(&info->port.delta_msr_wait); 815 816 /* 817 * Free the xmit buffer, if necessary 818 */ 819 if (info->port.xmit_buf) { 820 free_page((unsigned long) info->port.xmit_buf); 821 info->port.xmit_buf = NULL; 822 } 823 824 info->IER = 0; 825 outb(0x00, info->ioaddr + UART_IER); 826 827 /* clear Rx/Tx FIFO's */ 828 if (info->board->must_hwid) 829 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT | 830 MOXA_MUST_FCR_GDA_MODE_ENABLE, 831 info->ioaddr + UART_FCR); 832 else 833 outb(UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 834 info->ioaddr + UART_FCR); 835 836 /* read data port to reset things */ 837 (void) inb(info->ioaddr + UART_RX); 838 839 840 if (info->board->must_hwid) 841 mxser_must_no_sw_flow_control(info->ioaddr); 842 843 spin_unlock_irqrestore(&info->slock, flags); 844 } 845 846 /* 847 * This routine is called whenever a serial port is opened. It 848 * enables interrupts for a serial port, linking in its async structure into 849 * the IRQ chain. It also performs the serial-specific 850 * initialization for the tty structure. 851 */ 852 static int mxser_open(struct tty_struct *tty, struct file *filp) 853 { 854 struct tty_port *tport = tty->port; 855 struct mxser_port *port = container_of(tport, struct mxser_port, port); 856 857 tty->driver_data = port; 858 859 return tty_port_open(tport, tty, filp); 860 } 861 862 static void mxser_flush_buffer(struct tty_struct *tty) 863 { 864 struct mxser_port *info = tty->driver_data; 865 char fcr; 866 unsigned long flags; 867 868 869 spin_lock_irqsave(&info->slock, flags); 870 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0; 871 872 fcr = inb(info->ioaddr + UART_FCR); 873 outb((fcr | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT), 874 info->ioaddr + UART_FCR); 875 outb(fcr, info->ioaddr + UART_FCR); 876 877 spin_unlock_irqrestore(&info->slock, flags); 878 879 tty_wakeup(tty); 880 } 881 882 883 static void mxser_close_port(struct tty_port *port) 884 { 885 struct mxser_port *info = container_of(port, struct mxser_port, port); 886 unsigned long timeout; 887 /* 888 * At this point we stop accepting input. To do this, we 889 * disable the receive line status interrupts, and tell the 890 * interrupt driver to stop checking the data ready bit in the 891 * line status register. 892 */ 893 info->IER &= ~UART_IER_RLSI; 894 if (info->board->must_hwid) 895 info->IER &= ~MOXA_MUST_RECV_ISR; 896 897 outb(info->IER, info->ioaddr + UART_IER); 898 /* 899 * Before we drop DTR, make sure the UART transmitter 900 * has completely drained; this is especially 901 * important if there is a transmit FIFO! 902 */ 903 timeout = jiffies + HZ; 904 while (!(inb(info->ioaddr + UART_LSR) & UART_LSR_TEMT)) { 905 schedule_timeout_interruptible(5); 906 if (time_after(jiffies, timeout)) 907 break; 908 } 909 } 910 911 /* 912 * This routine is called when the serial port gets closed. First, we 913 * wait for the last remaining data to be sent. Then, we unlink its 914 * async structure from the interrupt chain if necessary, and we free 915 * that IRQ if nothing is left in the chain. 916 */ 917 static void mxser_close(struct tty_struct *tty, struct file *filp) 918 { 919 struct mxser_port *info = tty->driver_data; 920 struct tty_port *port = &info->port; 921 922 if (info == NULL) 923 return; 924 if (tty_port_close_start(port, tty, filp) == 0) 925 return; 926 info->closing = 1; 927 mutex_lock(&port->mutex); 928 mxser_close_port(port); 929 mxser_flush_buffer(tty); 930 if (tty_port_initialized(port) && C_HUPCL(tty)) 931 tty_port_lower_dtr_rts(port); 932 mxser_shutdown_port(port); 933 tty_port_set_initialized(port, 0); 934 mutex_unlock(&port->mutex); 935 info->closing = 0; 936 /* Right now the tty_port set is done outside of the close_end helper 937 as we don't yet have everyone using refcounts */ 938 tty_port_close_end(port, tty); 939 tty_port_tty_set(port, NULL); 940 } 941 942 static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count) 943 { 944 int c, total = 0; 945 struct mxser_port *info = tty->driver_data; 946 unsigned long flags; 947 948 if (!info->port.xmit_buf) 949 return 0; 950 951 while (1) { 952 c = min_t(int, count, min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1, 953 SERIAL_XMIT_SIZE - info->xmit_head)); 954 if (c <= 0) 955 break; 956 957 memcpy(info->port.xmit_buf + info->xmit_head, buf, c); 958 spin_lock_irqsave(&info->slock, flags); 959 info->xmit_head = (info->xmit_head + c) & 960 (SERIAL_XMIT_SIZE - 1); 961 info->xmit_cnt += c; 962 spin_unlock_irqrestore(&info->slock, flags); 963 964 buf += c; 965 count -= c; 966 total += c; 967 } 968 969 if (info->xmit_cnt && !tty->flow.stopped) 970 if (!tty->hw_stopped || mxser_16550A_or_MUST(info)) 971 mxser_start_tx(info); 972 973 return total; 974 } 975 976 static int mxser_put_char(struct tty_struct *tty, unsigned char ch) 977 { 978 struct mxser_port *info = tty->driver_data; 979 unsigned long flags; 980 981 if (!info->port.xmit_buf) 982 return 0; 983 984 if (info->xmit_cnt >= SERIAL_XMIT_SIZE - 1) 985 return 0; 986 987 spin_lock_irqsave(&info->slock, flags); 988 info->port.xmit_buf[info->xmit_head++] = ch; 989 info->xmit_head &= SERIAL_XMIT_SIZE - 1; 990 info->xmit_cnt++; 991 spin_unlock_irqrestore(&info->slock, flags); 992 993 return 1; 994 } 995 996 997 static void mxser_flush_chars(struct tty_struct *tty) 998 { 999 struct mxser_port *info = tty->driver_data; 1000 1001 if (!info->xmit_cnt || tty->flow.stopped || !info->port.xmit_buf || 1002 (tty->hw_stopped && !mxser_16550A_or_MUST(info))) 1003 return; 1004 1005 mxser_start_tx(info); 1006 } 1007 1008 static unsigned int mxser_write_room(struct tty_struct *tty) 1009 { 1010 struct mxser_port *info = tty->driver_data; 1011 int ret; 1012 1013 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1; 1014 return ret < 0 ? 0 : ret; 1015 } 1016 1017 static unsigned int mxser_chars_in_buffer(struct tty_struct *tty) 1018 { 1019 struct mxser_port *info = tty->driver_data; 1020 return info->xmit_cnt; 1021 } 1022 1023 /* 1024 * ------------------------------------------------------------ 1025 * friends of mxser_ioctl() 1026 * ------------------------------------------------------------ 1027 */ 1028 static int mxser_get_serial_info(struct tty_struct *tty, 1029 struct serial_struct *ss) 1030 { 1031 struct mxser_port *info = tty->driver_data; 1032 struct tty_port *port = &info->port; 1033 unsigned int closing_wait, close_delay; 1034 1035 mutex_lock(&port->mutex); 1036 1037 close_delay = jiffies_to_msecs(info->port.close_delay) / 10; 1038 closing_wait = info->port.closing_wait; 1039 if (closing_wait != ASYNC_CLOSING_WAIT_NONE) 1040 closing_wait = jiffies_to_msecs(closing_wait) / 10; 1041 1042 ss->type = info->type; 1043 ss->line = tty->index; 1044 ss->port = info->ioaddr; 1045 ss->irq = info->board->irq; 1046 ss->flags = info->port.flags; 1047 ss->baud_base = MXSER_BAUD_BASE; 1048 ss->close_delay = close_delay; 1049 ss->closing_wait = closing_wait; 1050 ss->custom_divisor = MXSER_CUSTOM_DIVISOR, 1051 mutex_unlock(&port->mutex); 1052 return 0; 1053 } 1054 1055 static int mxser_set_serial_info(struct tty_struct *tty, 1056 struct serial_struct *ss) 1057 { 1058 struct mxser_port *info = tty->driver_data; 1059 struct tty_port *port = &info->port; 1060 speed_t baud; 1061 unsigned long sl_flags; 1062 unsigned int old_speed, close_delay, closing_wait; 1063 int retval = 0; 1064 1065 if (tty_io_error(tty)) 1066 return -EIO; 1067 1068 mutex_lock(&port->mutex); 1069 1070 if (ss->irq != info->board->irq || 1071 ss->port != info->ioaddr) { 1072 mutex_unlock(&port->mutex); 1073 return -EINVAL; 1074 } 1075 1076 old_speed = port->flags & ASYNC_SPD_MASK; 1077 1078 close_delay = msecs_to_jiffies(ss->close_delay * 10); 1079 closing_wait = ss->closing_wait; 1080 if (closing_wait != ASYNC_CLOSING_WAIT_NONE) 1081 closing_wait = msecs_to_jiffies(closing_wait * 10); 1082 1083 if (!capable(CAP_SYS_ADMIN)) { 1084 if ((ss->baud_base != MXSER_BAUD_BASE) || 1085 (close_delay != port->close_delay) || 1086 (closing_wait != port->closing_wait) || 1087 ((ss->flags & ~ASYNC_USR_MASK) != (port->flags & ~ASYNC_USR_MASK))) { 1088 mutex_unlock(&port->mutex); 1089 return -EPERM; 1090 } 1091 port->flags = (port->flags & ~ASYNC_USR_MASK) | 1092 (ss->flags & ASYNC_USR_MASK); 1093 } else { 1094 /* 1095 * OK, past this point, all the error checking has been done. 1096 * At this point, we start making changes..... 1097 */ 1098 port->flags = ((port->flags & ~ASYNC_FLAGS) | 1099 (ss->flags & ASYNC_FLAGS)); 1100 port->close_delay = close_delay; 1101 port->closing_wait = closing_wait; 1102 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST && 1103 (ss->baud_base != MXSER_BAUD_BASE || 1104 ss->custom_divisor != 1105 MXSER_CUSTOM_DIVISOR)) { 1106 if (ss->custom_divisor == 0) { 1107 mutex_unlock(&port->mutex); 1108 return -EINVAL; 1109 } 1110 baud = ss->baud_base / ss->custom_divisor; 1111 tty_encode_baud_rate(tty, baud, baud); 1112 } 1113 1114 info->type = ss->type; 1115 1116 mxser_process_txrx_fifo(info); 1117 } 1118 1119 if (tty_port_initialized(port)) { 1120 if (old_speed != (port->flags & ASYNC_SPD_MASK)) { 1121 spin_lock_irqsave(&info->slock, sl_flags); 1122 mxser_change_speed(tty); 1123 spin_unlock_irqrestore(&info->slock, sl_flags); 1124 } 1125 } else { 1126 retval = mxser_activate(port, tty); 1127 if (retval == 0) 1128 tty_port_set_initialized(port, 1); 1129 } 1130 mutex_unlock(&port->mutex); 1131 return retval; 1132 } 1133 1134 /* 1135 * mxser_get_lsr_info - get line status register info 1136 * 1137 * Purpose: Let user call ioctl() to get info when the UART physically 1138 * is emptied. On bus types like RS485, the transmitter must 1139 * release the bus after transmitting. This must be done when 1140 * the transmit shift register is empty, not be done when the 1141 * transmit holding register is empty. This functionality 1142 * allows an RS485 driver to be written in user space. 1143 */ 1144 static int mxser_get_lsr_info(struct mxser_port *info, 1145 unsigned int __user *value) 1146 { 1147 unsigned char status; 1148 unsigned int result; 1149 unsigned long flags; 1150 1151 spin_lock_irqsave(&info->slock, flags); 1152 status = inb(info->ioaddr + UART_LSR); 1153 spin_unlock_irqrestore(&info->slock, flags); 1154 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0); 1155 return put_user(result, value); 1156 } 1157 1158 static int mxser_tiocmget(struct tty_struct *tty) 1159 { 1160 struct mxser_port *info = tty->driver_data; 1161 unsigned char control, status; 1162 unsigned long flags; 1163 1164 if (tty_io_error(tty)) 1165 return -EIO; 1166 1167 spin_lock_irqsave(&info->slock, flags); 1168 control = info->MCR; 1169 status = inb(info->ioaddr + UART_MSR); 1170 if (status & UART_MSR_ANY_DELTA) 1171 mxser_check_modem_status(tty, info, status); 1172 spin_unlock_irqrestore(&info->slock, flags); 1173 1174 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) | 1175 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) | 1176 ((status & UART_MSR_DCD) ? TIOCM_CAR : 0) | 1177 ((status & UART_MSR_RI) ? TIOCM_RNG : 0) | 1178 ((status & UART_MSR_DSR) ? TIOCM_DSR : 0) | 1179 ((status & UART_MSR_CTS) ? TIOCM_CTS : 0); 1180 } 1181 1182 static int mxser_tiocmset(struct tty_struct *tty, 1183 unsigned int set, unsigned int clear) 1184 { 1185 struct mxser_port *info = tty->driver_data; 1186 unsigned long flags; 1187 1188 if (tty_io_error(tty)) 1189 return -EIO; 1190 1191 spin_lock_irqsave(&info->slock, flags); 1192 1193 if (set & TIOCM_RTS) 1194 info->MCR |= UART_MCR_RTS; 1195 if (set & TIOCM_DTR) 1196 info->MCR |= UART_MCR_DTR; 1197 1198 if (clear & TIOCM_RTS) 1199 info->MCR &= ~UART_MCR_RTS; 1200 if (clear & TIOCM_DTR) 1201 info->MCR &= ~UART_MCR_DTR; 1202 1203 outb(info->MCR, info->ioaddr + UART_MCR); 1204 spin_unlock_irqrestore(&info->slock, flags); 1205 return 0; 1206 } 1207 1208 static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg, 1209 struct async_icount *cprev) 1210 { 1211 struct async_icount cnow; 1212 unsigned long flags; 1213 int ret; 1214 1215 spin_lock_irqsave(&info->slock, flags); 1216 cnow = info->icount; /* atomic copy */ 1217 spin_unlock_irqrestore(&info->slock, flags); 1218 1219 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) || 1220 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) || 1221 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) || 1222 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts)); 1223 1224 *cprev = cnow; 1225 1226 return ret; 1227 } 1228 1229 /* We should likely switch to TIOCGRS485/TIOCSRS485. */ 1230 static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set, 1231 int __user *u_opmode) 1232 { 1233 int opmode, p = index % 4; 1234 int shiftbit = p * 2; 1235 u8 val; 1236 1237 if (port->board->must_hwid != MOXA_MUST_MU860_HWID) 1238 return -EFAULT; 1239 1240 if (set) { 1241 if (get_user(opmode, u_opmode)) 1242 return -EFAULT; 1243 1244 if (opmode & ~OP_MODE_MASK) 1245 return -EINVAL; 1246 1247 spin_lock_irq(&port->slock); 1248 val = inb(port->opmode_ioaddr); 1249 val &= ~(OP_MODE_MASK << shiftbit); 1250 val |= (opmode << shiftbit); 1251 outb(val, port->opmode_ioaddr); 1252 spin_unlock_irq(&port->slock); 1253 1254 return 0; 1255 } 1256 1257 spin_lock_irq(&port->slock); 1258 opmode = inb(port->opmode_ioaddr) >> shiftbit; 1259 spin_unlock_irq(&port->slock); 1260 1261 return put_user(opmode & OP_MODE_MASK, u_opmode); 1262 } 1263 1264 static int mxser_ioctl(struct tty_struct *tty, 1265 unsigned int cmd, unsigned long arg) 1266 { 1267 struct mxser_port *info = tty->driver_data; 1268 struct async_icount cnow; 1269 unsigned long flags; 1270 void __user *argp = (void __user *)arg; 1271 1272 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) 1273 return mxser_ioctl_op_mode(info, tty->index, 1274 cmd == MOXA_SET_OP_MODE, argp); 1275 1276 if (cmd != TIOCMIWAIT && tty_io_error(tty)) 1277 return -EIO; 1278 1279 switch (cmd) { 1280 case TIOCSERGETLSR: /* Get line status register */ 1281 return mxser_get_lsr_info(info, argp); 1282 /* 1283 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change 1284 * - mask passed in arg for lines of interest 1285 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) 1286 * Caller should use TIOCGICOUNT to see which one it was 1287 */ 1288 case TIOCMIWAIT: 1289 spin_lock_irqsave(&info->slock, flags); 1290 cnow = info->icount; /* note the counters on entry */ 1291 spin_unlock_irqrestore(&info->slock, flags); 1292 1293 return wait_event_interruptible(info->port.delta_msr_wait, 1294 mxser_cflags_changed(info, arg, &cnow)); 1295 default: 1296 return -ENOIOCTLCMD; 1297 } 1298 return 0; 1299 } 1300 1301 /* 1302 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) 1303 * Return: write counters to the user passed counter struct 1304 * NB: both 1->0 and 0->1 transitions are counted except for 1305 * RI where only 0->1 is counted. 1306 */ 1307 1308 static int mxser_get_icount(struct tty_struct *tty, 1309 struct serial_icounter_struct *icount) 1310 1311 { 1312 struct mxser_port *info = tty->driver_data; 1313 struct async_icount cnow; 1314 unsigned long flags; 1315 1316 spin_lock_irqsave(&info->slock, flags); 1317 cnow = info->icount; 1318 spin_unlock_irqrestore(&info->slock, flags); 1319 1320 icount->frame = cnow.frame; 1321 icount->brk = cnow.brk; 1322 icount->overrun = cnow.overrun; 1323 icount->buf_overrun = cnow.buf_overrun; 1324 icount->parity = cnow.parity; 1325 icount->rx = cnow.rx; 1326 icount->tx = cnow.tx; 1327 icount->cts = cnow.cts; 1328 icount->dsr = cnow.dsr; 1329 icount->rng = cnow.rng; 1330 icount->dcd = cnow.dcd; 1331 return 0; 1332 } 1333 1334 static void mxser_stoprx(struct tty_struct *tty) 1335 { 1336 struct mxser_port *info = tty->driver_data; 1337 1338 info->ldisc_stop_rx = 1; 1339 if (I_IXOFF(tty)) { 1340 if (info->board->must_hwid) { 1341 info->IER &= ~MOXA_MUST_RECV_ISR; 1342 outb(info->IER, info->ioaddr + UART_IER); 1343 } else { 1344 info->x_char = STOP_CHAR(tty); 1345 outb(0, info->ioaddr + UART_IER); 1346 info->IER |= UART_IER_THRI; 1347 outb(info->IER, info->ioaddr + UART_IER); 1348 } 1349 } 1350 1351 if (C_CRTSCTS(tty)) { 1352 info->MCR &= ~UART_MCR_RTS; 1353 outb(info->MCR, info->ioaddr + UART_MCR); 1354 } 1355 } 1356 1357 /* 1358 * This routine is called by the upper-layer tty layer to signal that 1359 * incoming characters should be throttled. 1360 */ 1361 static void mxser_throttle(struct tty_struct *tty) 1362 { 1363 mxser_stoprx(tty); 1364 } 1365 1366 static void mxser_unthrottle(struct tty_struct *tty) 1367 { 1368 struct mxser_port *info = tty->driver_data; 1369 1370 /* startrx */ 1371 info->ldisc_stop_rx = 0; 1372 if (I_IXOFF(tty)) { 1373 if (info->x_char) 1374 info->x_char = 0; 1375 else { 1376 if (info->board->must_hwid) { 1377 info->IER |= MOXA_MUST_RECV_ISR; 1378 outb(info->IER, info->ioaddr + UART_IER); 1379 } else { 1380 info->x_char = START_CHAR(tty); 1381 outb(0, info->ioaddr + UART_IER); 1382 info->IER |= UART_IER_THRI; 1383 outb(info->IER, info->ioaddr + UART_IER); 1384 } 1385 } 1386 } 1387 1388 if (C_CRTSCTS(tty)) { 1389 info->MCR |= UART_MCR_RTS; 1390 outb(info->MCR, info->ioaddr + UART_MCR); 1391 } 1392 } 1393 1394 /* 1395 * mxser_stop() and mxser_start() 1396 * 1397 * This routines are called before setting or resetting tty->flow.stopped. 1398 * They enable or disable transmitter interrupts, as necessary. 1399 */ 1400 static void mxser_stop(struct tty_struct *tty) 1401 { 1402 struct mxser_port *info = tty->driver_data; 1403 unsigned long flags; 1404 1405 spin_lock_irqsave(&info->slock, flags); 1406 if (info->IER & UART_IER_THRI) 1407 __mxser_stop_tx(info); 1408 spin_unlock_irqrestore(&info->slock, flags); 1409 } 1410 1411 static void mxser_start(struct tty_struct *tty) 1412 { 1413 struct mxser_port *info = tty->driver_data; 1414 unsigned long flags; 1415 1416 spin_lock_irqsave(&info->slock, flags); 1417 if (info->xmit_cnt && info->port.xmit_buf) 1418 __mxser_start_tx(info); 1419 spin_unlock_irqrestore(&info->slock, flags); 1420 } 1421 1422 static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios) 1423 { 1424 struct mxser_port *info = tty->driver_data; 1425 unsigned long flags; 1426 1427 spin_lock_irqsave(&info->slock, flags); 1428 mxser_change_speed(tty); 1429 spin_unlock_irqrestore(&info->slock, flags); 1430 1431 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) { 1432 tty->hw_stopped = 0; 1433 mxser_start(tty); 1434 } 1435 1436 /* Handle sw stopped */ 1437 if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) { 1438 tty->flow.stopped = 0; 1439 1440 if (info->board->must_hwid) { 1441 spin_lock_irqsave(&info->slock, flags); 1442 mxser_must_set_rx_sw_flow_control(info->ioaddr, false); 1443 spin_unlock_irqrestore(&info->slock, flags); 1444 } 1445 1446 mxser_start(tty); 1447 } 1448 } 1449 1450 /* 1451 * mxser_wait_until_sent() --- wait until the transmitter is empty 1452 */ 1453 static void mxser_wait_until_sent(struct tty_struct *tty, int timeout) 1454 { 1455 struct mxser_port *info = tty->driver_data; 1456 unsigned long orig_jiffies, char_time; 1457 unsigned long flags; 1458 int lsr; 1459 1460 if (info->type == PORT_UNKNOWN) 1461 return; 1462 1463 if (info->xmit_fifo_size == 0) 1464 return; /* Just in case.... */ 1465 1466 orig_jiffies = jiffies; 1467 /* 1468 * Set the check interval to be 1/5 of the estimated time to 1469 * send a single character, and make it at least 1. The check 1470 * interval should also be less than the timeout. 1471 * 1472 * Note: we have to use pretty tight timings here to satisfy 1473 * the NIST-PCTS. 1474 */ 1475 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size; 1476 char_time = char_time / 5; 1477 if (char_time == 0) 1478 char_time = 1; 1479 if (timeout && timeout < char_time) 1480 char_time = timeout; 1481 /* 1482 * If the transmitter hasn't cleared in twice the approximate 1483 * amount of time to send the entire FIFO, it probably won't 1484 * ever clear. This assumes the UART isn't doing flow 1485 * control, which is currently the case. Hence, if it ever 1486 * takes longer than info->timeout, this is probably due to a 1487 * UART bug of some kind. So, we clamp the timeout parameter at 1488 * 2*info->timeout. 1489 */ 1490 if (!timeout || timeout > 2 * info->timeout) 1491 timeout = 2 * info->timeout; 1492 1493 spin_lock_irqsave(&info->slock, flags); 1494 while (!((lsr = inb(info->ioaddr + UART_LSR)) & UART_LSR_TEMT)) { 1495 spin_unlock_irqrestore(&info->slock, flags); 1496 schedule_timeout_interruptible(char_time); 1497 spin_lock_irqsave(&info->slock, flags); 1498 if (signal_pending(current)) 1499 break; 1500 if (timeout && time_after(jiffies, orig_jiffies + timeout)) 1501 break; 1502 } 1503 spin_unlock_irqrestore(&info->slock, flags); 1504 set_current_state(TASK_RUNNING); 1505 } 1506 1507 /* 1508 * This routine is called by tty_hangup() when a hangup is signaled. 1509 */ 1510 static void mxser_hangup(struct tty_struct *tty) 1511 { 1512 struct mxser_port *info = tty->driver_data; 1513 1514 mxser_flush_buffer(tty); 1515 tty_port_hangup(&info->port); 1516 } 1517 1518 /* 1519 * mxser_rs_break() --- routine which turns the break handling on or off 1520 */ 1521 static int mxser_rs_break(struct tty_struct *tty, int break_state) 1522 { 1523 struct mxser_port *info = tty->driver_data; 1524 unsigned long flags; 1525 u8 lcr; 1526 1527 spin_lock_irqsave(&info->slock, flags); 1528 lcr = inb(info->ioaddr + UART_LCR); 1529 if (break_state == -1) 1530 lcr |= UART_LCR_SBC; 1531 else 1532 lcr &= ~UART_LCR_SBC; 1533 outb(lcr, info->ioaddr + UART_LCR); 1534 spin_unlock_irqrestore(&info->slock, flags); 1535 1536 return 0; 1537 } 1538 1539 static bool mxser_receive_chars_new(struct tty_struct *tty, 1540 struct mxser_port *port, u8 status) 1541 { 1542 enum mxser_must_hwid hwid = port->board->must_hwid; 1543 u8 gdl; 1544 1545 if (hwid == MOXA_OTHER_UART) 1546 return false; 1547 if (status & UART_LSR_BRK_ERROR_BITS) 1548 return false; 1549 if (hwid == MOXA_MUST_MU860_HWID && (status & MOXA_MUST_LSR_RERR)) 1550 return false; 1551 if (status & MOXA_MUST_LSR_RERR) 1552 return false; 1553 1554 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER); 1555 if (hwid == MOXA_MUST_MU150_HWID) 1556 gdl &= MOXA_MUST_GDL_MASK; 1557 1558 if (gdl >= tty->receive_room && !port->ldisc_stop_rx) 1559 mxser_stoprx(tty); 1560 1561 while (gdl--) { 1562 u8 ch = inb(port->ioaddr + UART_RX); 1563 tty_insert_flip_char(&port->port, ch, 0); 1564 } 1565 1566 return true; 1567 } 1568 1569 static u8 mxser_receive_chars_old(struct tty_struct *tty, 1570 struct mxser_port *port, u8 status) 1571 { 1572 enum mxser_must_hwid hwid = port->board->must_hwid; 1573 int recv_room = tty->receive_room; 1574 int ignored = 0; 1575 int max = 256; 1576 int cnt = 0; 1577 u8 ch; 1578 1579 do { 1580 if (max-- < 0) 1581 break; 1582 1583 ch = inb(port->ioaddr + UART_RX); 1584 if (hwid && (status & UART_LSR_OE)) 1585 outb(UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | 1586 MOXA_MUST_FCR_GDA_MODE_ENABLE, 1587 port->ioaddr + UART_FCR); 1588 status &= port->read_status_mask; 1589 if (status & port->ignore_status_mask) { 1590 if (++ignored > 100) 1591 break; 1592 } else { 1593 char flag = 0; 1594 if (status & UART_LSR_BRK_ERROR_BITS) { 1595 if (status & UART_LSR_BI) { 1596 flag = TTY_BREAK; 1597 port->icount.brk++; 1598 1599 if (port->port.flags & ASYNC_SAK) 1600 do_SAK(tty); 1601 } else if (status & UART_LSR_PE) { 1602 flag = TTY_PARITY; 1603 port->icount.parity++; 1604 } else if (status & UART_LSR_FE) { 1605 flag = TTY_FRAME; 1606 port->icount.frame++; 1607 } else if (status & UART_LSR_OE) { 1608 flag = TTY_OVERRUN; 1609 port->icount.overrun++; 1610 } 1611 } 1612 tty_insert_flip_char(&port->port, ch, flag); 1613 cnt++; 1614 if (cnt >= recv_room) { 1615 if (!port->ldisc_stop_rx) 1616 mxser_stoprx(tty); 1617 break; 1618 } 1619 1620 } 1621 1622 if (hwid) 1623 break; 1624 1625 status = inb(port->ioaddr + UART_LSR); 1626 } while (status & UART_LSR_DR); 1627 1628 return status; 1629 } 1630 1631 static u8 mxser_receive_chars(struct tty_struct *tty, 1632 struct mxser_port *port, u8 status) 1633 { 1634 if (tty->receive_room == 0 && !port->ldisc_stop_rx) 1635 mxser_stoprx(tty); 1636 1637 if (!mxser_receive_chars_new(tty, port, status)) 1638 status = mxser_receive_chars_old(tty, port, status); 1639 1640 tty_flip_buffer_push(&port->port); 1641 1642 return status; 1643 } 1644 1645 static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port) 1646 { 1647 int count, cnt; 1648 1649 if (port->x_char) { 1650 outb(port->x_char, port->ioaddr + UART_TX); 1651 port->x_char = 0; 1652 port->icount.tx++; 1653 return; 1654 } 1655 1656 if (port->port.xmit_buf == NULL) 1657 return; 1658 1659 if (!port->xmit_cnt || tty->flow.stopped || 1660 (tty->hw_stopped && !mxser_16550A_or_MUST(port))) { 1661 __mxser_stop_tx(port); 1662 return; 1663 } 1664 1665 cnt = port->xmit_cnt; 1666 count = port->xmit_fifo_size; 1667 do { 1668 outb(port->port.xmit_buf[port->xmit_tail++], 1669 port->ioaddr + UART_TX); 1670 port->xmit_tail = port->xmit_tail & (SERIAL_XMIT_SIZE - 1); 1671 if (!--port->xmit_cnt) 1672 break; 1673 } while (--count > 0); 1674 1675 port->icount.tx += (cnt - port->xmit_cnt); 1676 1677 if (port->xmit_cnt < WAKEUP_CHARS) 1678 tty_wakeup(tty); 1679 1680 if (!port->xmit_cnt) 1681 __mxser_stop_tx(port); 1682 } 1683 1684 static bool mxser_port_isr(struct mxser_port *port) 1685 { 1686 struct tty_struct *tty; 1687 u8 iir, msr, status; 1688 bool error = false; 1689 1690 iir = inb(port->ioaddr + UART_IIR); 1691 if (iir & UART_IIR_NO_INT) 1692 return true; 1693 1694 iir &= MOXA_MUST_IIR_MASK; 1695 tty = tty_port_tty_get(&port->port); 1696 if (!tty || port->closing || !tty_port_initialized(&port->port)) { 1697 status = inb(port->ioaddr + UART_LSR); 1698 outb(MOXA_MUST_FCR_GDA_MODE_ENABLE | UART_FCR_ENABLE_FIFO | 1699 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 1700 port->ioaddr + UART_FCR); 1701 inb(port->ioaddr + UART_MSR); 1702 1703 error = true; 1704 goto put_tty; 1705 } 1706 1707 status = inb(port->ioaddr + UART_LSR); 1708 1709 if (port->board->must_hwid) { 1710 if (iir == MOXA_MUST_IIR_GDA || 1711 iir == MOXA_MUST_IIR_RDA || 1712 iir == MOXA_MUST_IIR_RTO || 1713 iir == MOXA_MUST_IIR_LSR) 1714 status = mxser_receive_chars(tty, port, status); 1715 } else { 1716 status &= port->read_status_mask; 1717 if (status & UART_LSR_DR) 1718 status = mxser_receive_chars(tty, port, status); 1719 } 1720 1721 msr = inb(port->ioaddr + UART_MSR); 1722 if (msr & UART_MSR_ANY_DELTA) 1723 mxser_check_modem_status(tty, port, msr); 1724 1725 if (port->board->must_hwid) { 1726 if (iir == 0x02 && (status & UART_LSR_THRE)) 1727 mxser_transmit_chars(tty, port); 1728 } else { 1729 if (status & UART_LSR_THRE) 1730 mxser_transmit_chars(tty, port); 1731 } 1732 1733 put_tty: 1734 tty_kref_put(tty); 1735 1736 return error; 1737 } 1738 1739 /* 1740 * This is the serial driver's generic interrupt routine 1741 */ 1742 static irqreturn_t mxser_interrupt(int irq, void *dev_id) 1743 { 1744 struct mxser_board *brd = dev_id; 1745 struct mxser_port *port; 1746 unsigned int int_cnt, pass_counter = 0; 1747 unsigned int i, max = brd->nports; 1748 int handled = IRQ_NONE; 1749 u8 irqbits, bits, mask = BIT(max) - 1; 1750 1751 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) { 1752 irqbits = inb(brd->vector) & mask; 1753 if (irqbits == mask) 1754 break; 1755 1756 handled = IRQ_HANDLED; 1757 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) { 1758 if (irqbits == mask) 1759 break; 1760 if (bits & irqbits) 1761 continue; 1762 port = &brd->ports[i]; 1763 1764 int_cnt = 0; 1765 spin_lock(&port->slock); 1766 do { 1767 if (mxser_port_isr(port)) 1768 break; 1769 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT); 1770 spin_unlock(&port->slock); 1771 } 1772 } 1773 1774 return handled; 1775 } 1776 1777 static const struct tty_operations mxser_ops = { 1778 .open = mxser_open, 1779 .close = mxser_close, 1780 .write = mxser_write, 1781 .put_char = mxser_put_char, 1782 .flush_chars = mxser_flush_chars, 1783 .write_room = mxser_write_room, 1784 .chars_in_buffer = mxser_chars_in_buffer, 1785 .flush_buffer = mxser_flush_buffer, 1786 .ioctl = mxser_ioctl, 1787 .throttle = mxser_throttle, 1788 .unthrottle = mxser_unthrottle, 1789 .set_termios = mxser_set_termios, 1790 .stop = mxser_stop, 1791 .start = mxser_start, 1792 .hangup = mxser_hangup, 1793 .break_ctl = mxser_rs_break, 1794 .wait_until_sent = mxser_wait_until_sent, 1795 .tiocmget = mxser_tiocmget, 1796 .tiocmset = mxser_tiocmset, 1797 .set_serial = mxser_set_serial_info, 1798 .get_serial = mxser_get_serial_info, 1799 .get_icount = mxser_get_icount, 1800 }; 1801 1802 static const struct tty_port_operations mxser_port_ops = { 1803 .carrier_raised = mxser_carrier_raised, 1804 .dtr_rts = mxser_dtr_rts, 1805 .activate = mxser_activate, 1806 .shutdown = mxser_shutdown_port, 1807 }; 1808 1809 /* 1810 * The MOXA Smartio/Industio serial driver boot-time initialization code! 1811 */ 1812 1813 static void mxser_initbrd(struct mxser_board *brd, bool high_baud) 1814 { 1815 struct mxser_port *info; 1816 unsigned int i; 1817 bool is_mu860; 1818 1819 brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr); 1820 is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID; 1821 1822 for (i = 0; i < UART_INFO_NUM; i++) { 1823 if (Gpci_uart_info[i].type == brd->must_hwid) { 1824 brd->max_baud = Gpci_uart_info[i].max_baud; 1825 1826 /* exception....CP-102 */ 1827 if (high_baud) 1828 brd->max_baud = 921600; 1829 break; 1830 } 1831 } 1832 1833 if (is_mu860) { 1834 /* set to RS232 mode by default */ 1835 outb(0, brd->vector + 4); 1836 outb(0, brd->vector + 0x0c); 1837 } 1838 1839 for (i = 0; i < brd->nports; i++) { 1840 info = &brd->ports[i]; 1841 if (is_mu860) { 1842 if (i < 4) 1843 info->opmode_ioaddr = brd->vector + 4; 1844 else 1845 info->opmode_ioaddr = brd->vector + 0x0c; 1846 } 1847 tty_port_init(&info->port); 1848 info->port.ops = &mxser_port_ops; 1849 info->board = brd; 1850 info->ldisc_stop_rx = 0; 1851 1852 /* Enhance mode enabled here */ 1853 if (brd->must_hwid != MOXA_OTHER_UART) 1854 mxser_must_set_enhance_mode(info->ioaddr, true); 1855 1856 info->type = PORT_16550A; 1857 1858 mxser_process_txrx_fifo(info); 1859 1860 info->port.close_delay = 5 * HZ / 10; 1861 info->port.closing_wait = 30 * HZ; 1862 spin_lock_init(&info->slock); 1863 1864 /* before set INT ISR, disable all int */ 1865 outb(inb(info->ioaddr + UART_IER) & 0xf0, 1866 info->ioaddr + UART_IER); 1867 } 1868 } 1869 1870 static int mxser_probe(struct pci_dev *pdev, 1871 const struct pci_device_id *ent) 1872 { 1873 struct mxser_board *brd; 1874 unsigned int i, base; 1875 unsigned long ioaddress; 1876 unsigned short nports = MXSER_NPORTS(ent->driver_data); 1877 struct device *tty_dev; 1878 int retval = -EINVAL; 1879 1880 i = find_first_zero_bit(mxser_boards, MXSER_BOARDS); 1881 if (i >= MXSER_BOARDS) { 1882 dev_err(&pdev->dev, "too many boards found (maximum %d), board " 1883 "not configured\n", MXSER_BOARDS); 1884 goto err; 1885 } 1886 1887 brd = devm_kzalloc(&pdev->dev, struct_size(brd, ports, nports), 1888 GFP_KERNEL); 1889 if (!brd) 1890 goto err; 1891 1892 brd->idx = i; 1893 __set_bit(brd->idx, mxser_boards); 1894 base = i * MXSER_PORTS_PER_BOARD; 1895 1896 retval = pcim_enable_device(pdev); 1897 if (retval) { 1898 dev_err(&pdev->dev, "PCI enable failed\n"); 1899 goto err_zero; 1900 } 1901 1902 /* io address */ 1903 ioaddress = pci_resource_start(pdev, 2); 1904 retval = pci_request_region(pdev, 2, "mxser(IO)"); 1905 if (retval) 1906 goto err_zero; 1907 1908 brd->nports = nports; 1909 for (i = 0; i < nports; i++) 1910 brd->ports[i].ioaddr = ioaddress + 8 * i; 1911 1912 /* vector */ 1913 ioaddress = pci_resource_start(pdev, 3); 1914 retval = pci_request_region(pdev, 3, "mxser(vector)"); 1915 if (retval) 1916 goto err_zero; 1917 brd->vector = ioaddress; 1918 1919 /* irq */ 1920 brd->irq = pdev->irq; 1921 1922 mxser_initbrd(brd, ent->driver_data & MXSER_HIGHBAUD); 1923 1924 retval = devm_request_irq(&pdev->dev, brd->irq, mxser_interrupt, 1925 IRQF_SHARED, "mxser", brd); 1926 if (retval) { 1927 dev_err(&pdev->dev, "request irq failed"); 1928 goto err_relbrd; 1929 } 1930 1931 for (i = 0; i < nports; i++) { 1932 tty_dev = tty_port_register_device(&brd->ports[i].port, 1933 mxvar_sdriver, base + i, &pdev->dev); 1934 if (IS_ERR(tty_dev)) { 1935 retval = PTR_ERR(tty_dev); 1936 for (; i > 0; i--) 1937 tty_unregister_device(mxvar_sdriver, 1938 base + i - 1); 1939 goto err_relbrd; 1940 } 1941 } 1942 1943 pci_set_drvdata(pdev, brd); 1944 1945 return 0; 1946 err_relbrd: 1947 for (i = 0; i < nports; i++) 1948 tty_port_destroy(&brd->ports[i].port); 1949 err_zero: 1950 __clear_bit(brd->idx, mxser_boards); 1951 err: 1952 return retval; 1953 } 1954 1955 static void mxser_remove(struct pci_dev *pdev) 1956 { 1957 struct mxser_board *brd = pci_get_drvdata(pdev); 1958 unsigned int i, base = brd->idx * MXSER_PORTS_PER_BOARD; 1959 1960 for (i = 0; i < brd->nports; i++) { 1961 tty_unregister_device(mxvar_sdriver, base + i); 1962 tty_port_destroy(&brd->ports[i].port); 1963 } 1964 1965 __clear_bit(brd->idx, mxser_boards); 1966 } 1967 1968 static struct pci_driver mxser_driver = { 1969 .name = "mxser", 1970 .id_table = mxser_pcibrds, 1971 .probe = mxser_probe, 1972 .remove = mxser_remove 1973 }; 1974 1975 static int __init mxser_module_init(void) 1976 { 1977 int retval; 1978 1979 mxvar_sdriver = tty_alloc_driver(MXSER_PORTS, TTY_DRIVER_REAL_RAW | 1980 TTY_DRIVER_DYNAMIC_DEV); 1981 if (IS_ERR(mxvar_sdriver)) 1982 return PTR_ERR(mxvar_sdriver); 1983 1984 /* Initialize the tty_driver structure */ 1985 mxvar_sdriver->name = "ttyMI"; 1986 mxvar_sdriver->major = ttymajor; 1987 mxvar_sdriver->minor_start = 0; 1988 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL; 1989 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL; 1990 mxvar_sdriver->init_termios = tty_std_termios; 1991 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL; 1992 tty_set_operations(mxvar_sdriver, &mxser_ops); 1993 1994 retval = tty_register_driver(mxvar_sdriver); 1995 if (retval) { 1996 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family " 1997 "tty driver !\n"); 1998 goto err_put; 1999 } 2000 2001 retval = pci_register_driver(&mxser_driver); 2002 if (retval) { 2003 printk(KERN_ERR "mxser: can't register pci driver\n"); 2004 goto err_unr; 2005 } 2006 2007 return 0; 2008 err_unr: 2009 tty_unregister_driver(mxvar_sdriver); 2010 err_put: 2011 tty_driver_kref_put(mxvar_sdriver); 2012 return retval; 2013 } 2014 2015 static void __exit mxser_module_exit(void) 2016 { 2017 pci_unregister_driver(&mxser_driver); 2018 tty_unregister_driver(mxvar_sdriver); 2019 tty_driver_kref_put(mxvar_sdriver); 2020 } 2021 2022 module_init(mxser_module_init); 2023 module_exit(mxser_module_exit); 2024