xref: /openbmc/linux/drivers/thunderbolt/usb4.c (revision f0931824)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * USB4 specific functionality
4  *
5  * Copyright (C) 2019, Intel Corporation
6  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
7  *	    Rajmohan Mani <rajmohan.mani@intel.com>
8  */
9 
10 #include <linux/delay.h>
11 #include <linux/ktime.h>
12 #include <linux/units.h>
13 
14 #include "sb_regs.h"
15 #include "tb.h"
16 
17 #define USB4_DATA_RETRIES		3
18 #define USB4_DATA_DWORDS		16
19 
20 enum usb4_sb_target {
21 	USB4_SB_TARGET_ROUTER,
22 	USB4_SB_TARGET_PARTNER,
23 	USB4_SB_TARGET_RETIMER,
24 };
25 
26 #define USB4_NVM_READ_OFFSET_MASK	GENMASK(23, 2)
27 #define USB4_NVM_READ_OFFSET_SHIFT	2
28 #define USB4_NVM_READ_LENGTH_MASK	GENMASK(27, 24)
29 #define USB4_NVM_READ_LENGTH_SHIFT	24
30 
31 #define USB4_NVM_SET_OFFSET_MASK	USB4_NVM_READ_OFFSET_MASK
32 #define USB4_NVM_SET_OFFSET_SHIFT	USB4_NVM_READ_OFFSET_SHIFT
33 
34 #define USB4_DROM_ADDRESS_MASK		GENMASK(14, 2)
35 #define USB4_DROM_ADDRESS_SHIFT		2
36 #define USB4_DROM_SIZE_MASK		GENMASK(19, 15)
37 #define USB4_DROM_SIZE_SHIFT		15
38 
39 #define USB4_NVM_SECTOR_SIZE_MASK	GENMASK(23, 0)
40 
41 #define USB4_BA_LENGTH_MASK		GENMASK(7, 0)
42 #define USB4_BA_INDEX_MASK		GENMASK(15, 0)
43 
44 enum usb4_ba_index {
45 	USB4_BA_MAX_USB3 = 0x1,
46 	USB4_BA_MIN_DP_AUX = 0x2,
47 	USB4_BA_MIN_DP_MAIN = 0x3,
48 	USB4_BA_MAX_PCIE = 0x4,
49 	USB4_BA_MAX_HI = 0x5,
50 };
51 
52 #define USB4_BA_VALUE_MASK		GENMASK(31, 16)
53 #define USB4_BA_VALUE_SHIFT		16
54 
55 static int usb4_native_switch_op(struct tb_switch *sw, u16 opcode,
56 				 u32 *metadata, u8 *status,
57 				 const void *tx_data, size_t tx_dwords,
58 				 void *rx_data, size_t rx_dwords)
59 {
60 	u32 val;
61 	int ret;
62 
63 	if (metadata) {
64 		ret = tb_sw_write(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
65 		if (ret)
66 			return ret;
67 	}
68 	if (tx_dwords) {
69 		ret = tb_sw_write(sw, tx_data, TB_CFG_SWITCH, ROUTER_CS_9,
70 				  tx_dwords);
71 		if (ret)
72 			return ret;
73 	}
74 
75 	val = opcode | ROUTER_CS_26_OV;
76 	ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
77 	if (ret)
78 		return ret;
79 
80 	ret = tb_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500);
81 	if (ret)
82 		return ret;
83 
84 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
85 	if (ret)
86 		return ret;
87 
88 	if (val & ROUTER_CS_26_ONS)
89 		return -EOPNOTSUPP;
90 
91 	if (status)
92 		*status = (val & ROUTER_CS_26_STATUS_MASK) >>
93 			ROUTER_CS_26_STATUS_SHIFT;
94 
95 	if (metadata) {
96 		ret = tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1);
97 		if (ret)
98 			return ret;
99 	}
100 	if (rx_dwords) {
101 		ret = tb_sw_read(sw, rx_data, TB_CFG_SWITCH, ROUTER_CS_9,
102 				 rx_dwords);
103 		if (ret)
104 			return ret;
105 	}
106 
107 	return 0;
108 }
109 
110 static int __usb4_switch_op(struct tb_switch *sw, u16 opcode, u32 *metadata,
111 			    u8 *status, const void *tx_data, size_t tx_dwords,
112 			    void *rx_data, size_t rx_dwords)
113 {
114 	const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
115 
116 	if (tx_dwords > USB4_DATA_DWORDS || rx_dwords > USB4_DATA_DWORDS)
117 		return -EINVAL;
118 
119 	/*
120 	 * If the connection manager implementation provides USB4 router
121 	 * operation proxy callback, call it here instead of running the
122 	 * operation natively.
123 	 */
124 	if (cm_ops->usb4_switch_op) {
125 		int ret;
126 
127 		ret = cm_ops->usb4_switch_op(sw, opcode, metadata, status,
128 					     tx_data, tx_dwords, rx_data,
129 					     rx_dwords);
130 		if (ret != -EOPNOTSUPP)
131 			return ret;
132 
133 		/*
134 		 * If the proxy was not supported then run the native
135 		 * router operation instead.
136 		 */
137 	}
138 
139 	return usb4_native_switch_op(sw, opcode, metadata, status, tx_data,
140 				     tx_dwords, rx_data, rx_dwords);
141 }
142 
143 static inline int usb4_switch_op(struct tb_switch *sw, u16 opcode,
144 				 u32 *metadata, u8 *status)
145 {
146 	return __usb4_switch_op(sw, opcode, metadata, status, NULL, 0, NULL, 0);
147 }
148 
149 static inline int usb4_switch_op_data(struct tb_switch *sw, u16 opcode,
150 				      u32 *metadata, u8 *status,
151 				      const void *tx_data, size_t tx_dwords,
152 				      void *rx_data, size_t rx_dwords)
153 {
154 	return __usb4_switch_op(sw, opcode, metadata, status, tx_data,
155 				tx_dwords, rx_data, rx_dwords);
156 }
157 
158 /**
159  * usb4_switch_check_wakes() - Check for wakes and notify PM core about them
160  * @sw: Router whose wakes to check
161  *
162  * Checks wakes occurred during suspend and notify the PM core about them.
163  */
164 void usb4_switch_check_wakes(struct tb_switch *sw)
165 {
166 	bool wakeup_usb4 = false;
167 	struct usb4_port *usb4;
168 	struct tb_port *port;
169 	bool wakeup = false;
170 	u32 val;
171 
172 	if (tb_route(sw)) {
173 		if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1))
174 			return;
175 
176 		tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n",
177 			  (val & ROUTER_CS_6_WOPS) ? "yes" : "no",
178 			  (val & ROUTER_CS_6_WOUS) ? "yes" : "no");
179 
180 		wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS);
181 	}
182 
183 	/*
184 	 * Check for any downstream ports for USB4 wake,
185 	 * connection wake and disconnection wake.
186 	 */
187 	tb_switch_for_each_port(sw, port) {
188 		if (!port->cap_usb4)
189 			continue;
190 
191 		if (tb_port_read(port, &val, TB_CFG_PORT,
192 				 port->cap_usb4 + PORT_CS_18, 1))
193 			break;
194 
195 		tb_port_dbg(port, "USB4 wake: %s, connection wake: %s, disconnection wake: %s\n",
196 			    (val & PORT_CS_18_WOU4S) ? "yes" : "no",
197 			    (val & PORT_CS_18_WOCS) ? "yes" : "no",
198 			    (val & PORT_CS_18_WODS) ? "yes" : "no");
199 
200 		wakeup_usb4 = val & (PORT_CS_18_WOU4S | PORT_CS_18_WOCS |
201 				     PORT_CS_18_WODS);
202 
203 		usb4 = port->usb4;
204 		if (device_may_wakeup(&usb4->dev) && wakeup_usb4)
205 			pm_wakeup_event(&usb4->dev, 0);
206 
207 		wakeup |= wakeup_usb4;
208 	}
209 
210 	if (wakeup)
211 		pm_wakeup_event(&sw->dev, 0);
212 }
213 
214 static bool link_is_usb4(struct tb_port *port)
215 {
216 	u32 val;
217 
218 	if (!port->cap_usb4)
219 		return false;
220 
221 	if (tb_port_read(port, &val, TB_CFG_PORT,
222 			 port->cap_usb4 + PORT_CS_18, 1))
223 		return false;
224 
225 	return !(val & PORT_CS_18_TCM);
226 }
227 
228 /**
229  * usb4_switch_setup() - Additional setup for USB4 device
230  * @sw: USB4 router to setup
231  *
232  * USB4 routers need additional settings in order to enable all the
233  * tunneling. This function enables USB and PCIe tunneling if it can be
234  * enabled (e.g the parent switch also supports them). If USB tunneling
235  * is not available for some reason (like that there is Thunderbolt 3
236  * switch upstream) then the internal xHCI controller is enabled
237  * instead.
238  *
239  * This does not set the configuration valid bit of the router. To do
240  * that call usb4_switch_configuration_valid().
241  */
242 int usb4_switch_setup(struct tb_switch *sw)
243 {
244 	struct tb_switch *parent = tb_switch_parent(sw);
245 	struct tb_port *down;
246 	bool tbt3, xhci;
247 	u32 val = 0;
248 	int ret;
249 
250 	if (!tb_route(sw))
251 		return 0;
252 
253 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1);
254 	if (ret)
255 		return ret;
256 
257 	down = tb_switch_downstream_port(sw);
258 	sw->link_usb4 = link_is_usb4(down);
259 	tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT");
260 
261 	xhci = val & ROUTER_CS_6_HCI;
262 	tbt3 = !(val & ROUTER_CS_6_TNS);
263 
264 	tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n",
265 		  tbt3 ? "yes" : "no", xhci ? "yes" : "no");
266 
267 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
268 	if (ret)
269 		return ret;
270 
271 	if (tb_acpi_may_tunnel_usb3() && sw->link_usb4 &&
272 	    tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) {
273 		val |= ROUTER_CS_5_UTO;
274 		xhci = false;
275 	}
276 
277 	/*
278 	 * Only enable PCIe tunneling if the parent router supports it
279 	 * and it is not disabled.
280 	 */
281 	if (tb_acpi_may_tunnel_pcie() &&
282 	    tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) {
283 		val |= ROUTER_CS_5_PTO;
284 		/*
285 		 * xHCI can be enabled if PCIe tunneling is supported
286 		 * and the parent does not have any USB3 dowstream
287 		 * adapters (so we cannot do USB 3.x tunneling).
288 		 */
289 		if (xhci)
290 			val |= ROUTER_CS_5_HCO;
291 	}
292 
293 	/* TBT3 supported by the CM */
294 	val &= ~ROUTER_CS_5_CNS;
295 
296 	return tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
297 }
298 
299 /**
300  * usb4_switch_configuration_valid() - Set tunneling configuration to be valid
301  * @sw: USB4 router
302  *
303  * Sets configuration valid bit for the router. Must be called before
304  * any tunnels can be set through the router and after
305  * usb4_switch_setup() has been called. Can be called to host and device
306  * routers (does nothing for the latter).
307  *
308  * Returns %0 in success and negative errno otherwise.
309  */
310 int usb4_switch_configuration_valid(struct tb_switch *sw)
311 {
312 	u32 val;
313 	int ret;
314 
315 	if (!tb_route(sw))
316 		return 0;
317 
318 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
319 	if (ret)
320 		return ret;
321 
322 	val |= ROUTER_CS_5_CV;
323 
324 	ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
325 	if (ret)
326 		return ret;
327 
328 	return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR,
329 				      ROUTER_CS_6_CR, 50);
330 }
331 
332 /**
333  * usb4_switch_read_uid() - Read UID from USB4 router
334  * @sw: USB4 router
335  * @uid: UID is stored here
336  *
337  * Reads 64-bit UID from USB4 router config space.
338  */
339 int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid)
340 {
341 	return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2);
342 }
343 
344 static int usb4_switch_drom_read_block(void *data,
345 				       unsigned int dwaddress, void *buf,
346 				       size_t dwords)
347 {
348 	struct tb_switch *sw = data;
349 	u8 status = 0;
350 	u32 metadata;
351 	int ret;
352 
353 	metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK;
354 	metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) &
355 		USB4_DROM_ADDRESS_MASK;
356 
357 	ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_DROM_READ, &metadata,
358 				  &status, NULL, 0, buf, dwords);
359 	if (ret)
360 		return ret;
361 
362 	return status ? -EIO : 0;
363 }
364 
365 /**
366  * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM
367  * @sw: USB4 router
368  * @address: Byte address inside DROM to start reading
369  * @buf: Buffer where the DROM content is stored
370  * @size: Number of bytes to read from DROM
371  *
372  * Uses USB4 router operations to read router DROM. For devices this
373  * should always work but for hosts it may return %-EOPNOTSUPP in which
374  * case the host router does not have DROM.
375  */
376 int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf,
377 			  size_t size)
378 {
379 	return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
380 				usb4_switch_drom_read_block, sw);
381 }
382 
383 /**
384  * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding
385  * @sw: USB4 router
386  *
387  * Checks whether conditions are met so that lane bonding can be
388  * established with the upstream router. Call only for device routers.
389  */
390 bool usb4_switch_lane_bonding_possible(struct tb_switch *sw)
391 {
392 	struct tb_port *up;
393 	int ret;
394 	u32 val;
395 
396 	up = tb_upstream_port(sw);
397 	ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1);
398 	if (ret)
399 		return false;
400 
401 	return !!(val & PORT_CS_18_BE);
402 }
403 
404 /**
405  * usb4_switch_set_wake() - Enabled/disable wake
406  * @sw: USB4 router
407  * @flags: Wakeup flags (%0 to disable)
408  *
409  * Enables/disables router to wake up from sleep.
410  */
411 int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags)
412 {
413 	struct usb4_port *usb4;
414 	struct tb_port *port;
415 	u64 route = tb_route(sw);
416 	u32 val;
417 	int ret;
418 
419 	/*
420 	 * Enable wakes coming from all USB4 downstream ports (from
421 	 * child routers). For device routers do this also for the
422 	 * upstream USB4 port.
423 	 */
424 	tb_switch_for_each_port(sw, port) {
425 		if (!tb_port_is_null(port))
426 			continue;
427 		if (!route && tb_is_upstream_port(port))
428 			continue;
429 		if (!port->cap_usb4)
430 			continue;
431 
432 		ret = tb_port_read(port, &val, TB_CFG_PORT,
433 				   port->cap_usb4 + PORT_CS_19, 1);
434 		if (ret)
435 			return ret;
436 
437 		val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4);
438 
439 		if (tb_is_upstream_port(port)) {
440 			val |= PORT_CS_19_WOU4;
441 		} else {
442 			bool configured = val & PORT_CS_19_PC;
443 			usb4 = port->usb4;
444 
445 			if (((flags & TB_WAKE_ON_CONNECT) |
446 			      device_may_wakeup(&usb4->dev)) && !configured)
447 				val |= PORT_CS_19_WOC;
448 			if (((flags & TB_WAKE_ON_DISCONNECT) |
449 			      device_may_wakeup(&usb4->dev)) && configured)
450 				val |= PORT_CS_19_WOD;
451 			if ((flags & TB_WAKE_ON_USB4) && configured)
452 				val |= PORT_CS_19_WOU4;
453 		}
454 
455 		ret = tb_port_write(port, &val, TB_CFG_PORT,
456 				    port->cap_usb4 + PORT_CS_19, 1);
457 		if (ret)
458 			return ret;
459 	}
460 
461 	/*
462 	 * Enable wakes from PCIe, USB 3.x and DP on this router. Only
463 	 * needed for device routers.
464 	 */
465 	if (route) {
466 		ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
467 		if (ret)
468 			return ret;
469 
470 		val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU | ROUTER_CS_5_WOD);
471 		if (flags & TB_WAKE_ON_USB3)
472 			val |= ROUTER_CS_5_WOU;
473 		if (flags & TB_WAKE_ON_PCIE)
474 			val |= ROUTER_CS_5_WOP;
475 		if (flags & TB_WAKE_ON_DP)
476 			val |= ROUTER_CS_5_WOD;
477 
478 		ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
479 		if (ret)
480 			return ret;
481 	}
482 
483 	return 0;
484 }
485 
486 /**
487  * usb4_switch_set_sleep() - Prepare the router to enter sleep
488  * @sw: USB4 router
489  *
490  * Sets sleep bit for the router. Returns when the router sleep ready
491  * bit has been asserted.
492  */
493 int usb4_switch_set_sleep(struct tb_switch *sw)
494 {
495 	int ret;
496 	u32 val;
497 
498 	/* Set sleep bit and wait for sleep ready to be asserted */
499 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
500 	if (ret)
501 		return ret;
502 
503 	val |= ROUTER_CS_5_SLP;
504 
505 	ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1);
506 	if (ret)
507 		return ret;
508 
509 	return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR,
510 				      ROUTER_CS_6_SLPR, 500);
511 }
512 
513 /**
514  * usb4_switch_nvm_sector_size() - Return router NVM sector size
515  * @sw: USB4 router
516  *
517  * If the router supports NVM operations this function returns the NVM
518  * sector size in bytes. If NVM operations are not supported returns
519  * %-EOPNOTSUPP.
520  */
521 int usb4_switch_nvm_sector_size(struct tb_switch *sw)
522 {
523 	u32 metadata;
524 	u8 status;
525 	int ret;
526 
527 	ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &metadata,
528 			     &status);
529 	if (ret)
530 		return ret;
531 
532 	if (status)
533 		return status == 0x2 ? -EOPNOTSUPP : -EIO;
534 
535 	return metadata & USB4_NVM_SECTOR_SIZE_MASK;
536 }
537 
538 static int usb4_switch_nvm_read_block(void *data,
539 	unsigned int dwaddress, void *buf, size_t dwords)
540 {
541 	struct tb_switch *sw = data;
542 	u8 status = 0;
543 	u32 metadata;
544 	int ret;
545 
546 	metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) &
547 		   USB4_NVM_READ_LENGTH_MASK;
548 	metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) &
549 		   USB4_NVM_READ_OFFSET_MASK;
550 
551 	ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_READ, &metadata,
552 				  &status, NULL, 0, buf, dwords);
553 	if (ret)
554 		return ret;
555 
556 	return status ? -EIO : 0;
557 }
558 
559 /**
560  * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM
561  * @sw: USB4 router
562  * @address: Starting address in bytes
563  * @buf: Read data is placed here
564  * @size: How many bytes to read
565  *
566  * Reads NVM contents of the router. If NVM is not supported returns
567  * %-EOPNOTSUPP.
568  */
569 int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf,
570 			 size_t size)
571 {
572 	return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
573 				usb4_switch_nvm_read_block, sw);
574 }
575 
576 /**
577  * usb4_switch_nvm_set_offset() - Set NVM write offset
578  * @sw: USB4 router
579  * @address: Start offset
580  *
581  * Explicitly sets NVM write offset. Normally when writing to NVM this
582  * is done automatically by usb4_switch_nvm_write().
583  *
584  * Returns %0 in success and negative errno if there was a failure.
585  */
586 int usb4_switch_nvm_set_offset(struct tb_switch *sw, unsigned int address)
587 {
588 	u32 metadata, dwaddress;
589 	u8 status = 0;
590 	int ret;
591 
592 	dwaddress = address / 4;
593 	metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
594 		   USB4_NVM_SET_OFFSET_MASK;
595 
596 	ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &metadata,
597 			     &status);
598 	if (ret)
599 		return ret;
600 
601 	return status ? -EIO : 0;
602 }
603 
604 static int usb4_switch_nvm_write_next_block(void *data, unsigned int dwaddress,
605 					    const void *buf, size_t dwords)
606 {
607 	struct tb_switch *sw = data;
608 	u8 status;
609 	int ret;
610 
611 	ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_WRITE, NULL, &status,
612 				  buf, dwords, NULL, 0);
613 	if (ret)
614 		return ret;
615 
616 	return status ? -EIO : 0;
617 }
618 
619 /**
620  * usb4_switch_nvm_write() - Write to the router NVM
621  * @sw: USB4 router
622  * @address: Start address where to write in bytes
623  * @buf: Pointer to the data to write
624  * @size: Size of @buf in bytes
625  *
626  * Writes @buf to the router NVM using USB4 router operations. If NVM
627  * write is not supported returns %-EOPNOTSUPP.
628  */
629 int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address,
630 			  const void *buf, size_t size)
631 {
632 	int ret;
633 
634 	ret = usb4_switch_nvm_set_offset(sw, address);
635 	if (ret)
636 		return ret;
637 
638 	return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
639 				 usb4_switch_nvm_write_next_block, sw);
640 }
641 
642 /**
643  * usb4_switch_nvm_authenticate() - Authenticate new NVM
644  * @sw: USB4 router
645  *
646  * After the new NVM has been written via usb4_switch_nvm_write(), this
647  * function triggers NVM authentication process. The router gets power
648  * cycled and if the authentication is successful the new NVM starts
649  * running. In case of failure returns negative errno.
650  *
651  * The caller should call usb4_switch_nvm_authenticate_status() to read
652  * the status of the authentication after power cycle. It should be the
653  * first router operation to avoid the status being lost.
654  */
655 int usb4_switch_nvm_authenticate(struct tb_switch *sw)
656 {
657 	int ret;
658 
659 	ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, NULL, NULL);
660 	switch (ret) {
661 	/*
662 	 * The router is power cycled once NVM_AUTH is started so it is
663 	 * expected to get any of the following errors back.
664 	 */
665 	case -EACCES:
666 	case -ENOTCONN:
667 	case -ETIMEDOUT:
668 		return 0;
669 
670 	default:
671 		return ret;
672 	}
673 }
674 
675 /**
676  * usb4_switch_nvm_authenticate_status() - Read status of last NVM authenticate
677  * @sw: USB4 router
678  * @status: Status code of the operation
679  *
680  * The function checks if there is status available from the last NVM
681  * authenticate router operation. If there is status then %0 is returned
682  * and the status code is placed in @status. Returns negative errno in case
683  * of failure.
684  *
685  * Must be called before any other router operation.
686  */
687 int usb4_switch_nvm_authenticate_status(struct tb_switch *sw, u32 *status)
688 {
689 	const struct tb_cm_ops *cm_ops = sw->tb->cm_ops;
690 	u16 opcode;
691 	u32 val;
692 	int ret;
693 
694 	if (cm_ops->usb4_switch_nvm_authenticate_status) {
695 		ret = cm_ops->usb4_switch_nvm_authenticate_status(sw, status);
696 		if (ret != -EOPNOTSUPP)
697 			return ret;
698 	}
699 
700 	ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1);
701 	if (ret)
702 		return ret;
703 
704 	/* Check that the opcode is correct */
705 	opcode = val & ROUTER_CS_26_OPCODE_MASK;
706 	if (opcode == USB4_SWITCH_OP_NVM_AUTH) {
707 		if (val & ROUTER_CS_26_OV)
708 			return -EBUSY;
709 		if (val & ROUTER_CS_26_ONS)
710 			return -EOPNOTSUPP;
711 
712 		*status = (val & ROUTER_CS_26_STATUS_MASK) >>
713 			ROUTER_CS_26_STATUS_SHIFT;
714 	} else {
715 		*status = 0;
716 	}
717 
718 	return 0;
719 }
720 
721 /**
722  * usb4_switch_credits_init() - Read buffer allocation parameters
723  * @sw: USB4 router
724  *
725  * Reads @sw buffer allocation parameters and initializes @sw buffer
726  * allocation fields accordingly. Specifically @sw->credits_allocation
727  * is set to %true if these parameters can be used in tunneling.
728  *
729  * Returns %0 on success and negative errno otherwise.
730  */
731 int usb4_switch_credits_init(struct tb_switch *sw)
732 {
733 	int max_usb3, min_dp_aux, min_dp_main, max_pcie, max_dma;
734 	int ret, length, i, nports;
735 	const struct tb_port *port;
736 	u32 data[USB4_DATA_DWORDS];
737 	u32 metadata = 0;
738 	u8 status = 0;
739 
740 	memset(data, 0, sizeof(data));
741 	ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_BUFFER_ALLOC, &metadata,
742 				  &status, NULL, 0, data, ARRAY_SIZE(data));
743 	if (ret)
744 		return ret;
745 	if (status)
746 		return -EIO;
747 
748 	length = metadata & USB4_BA_LENGTH_MASK;
749 	if (WARN_ON(length > ARRAY_SIZE(data)))
750 		return -EMSGSIZE;
751 
752 	max_usb3 = -1;
753 	min_dp_aux = -1;
754 	min_dp_main = -1;
755 	max_pcie = -1;
756 	max_dma = -1;
757 
758 	tb_sw_dbg(sw, "credit allocation parameters:\n");
759 
760 	for (i = 0; i < length; i++) {
761 		u16 index, value;
762 
763 		index = data[i] & USB4_BA_INDEX_MASK;
764 		value = (data[i] & USB4_BA_VALUE_MASK) >> USB4_BA_VALUE_SHIFT;
765 
766 		switch (index) {
767 		case USB4_BA_MAX_USB3:
768 			tb_sw_dbg(sw, " USB3: %u\n", value);
769 			max_usb3 = value;
770 			break;
771 		case USB4_BA_MIN_DP_AUX:
772 			tb_sw_dbg(sw, " DP AUX: %u\n", value);
773 			min_dp_aux = value;
774 			break;
775 		case USB4_BA_MIN_DP_MAIN:
776 			tb_sw_dbg(sw, " DP main: %u\n", value);
777 			min_dp_main = value;
778 			break;
779 		case USB4_BA_MAX_PCIE:
780 			tb_sw_dbg(sw, " PCIe: %u\n", value);
781 			max_pcie = value;
782 			break;
783 		case USB4_BA_MAX_HI:
784 			tb_sw_dbg(sw, " DMA: %u\n", value);
785 			max_dma = value;
786 			break;
787 		default:
788 			tb_sw_dbg(sw, " unknown credit allocation index %#x, skipping\n",
789 				  index);
790 			break;
791 		}
792 	}
793 
794 	/*
795 	 * Validate the buffer allocation preferences. If we find
796 	 * issues, log a warning and fall back using the hard-coded
797 	 * values.
798 	 */
799 
800 	/* Host router must report baMaxHI */
801 	if (!tb_route(sw) && max_dma < 0) {
802 		tb_sw_warn(sw, "host router is missing baMaxHI\n");
803 		goto err_invalid;
804 	}
805 
806 	nports = 0;
807 	tb_switch_for_each_port(sw, port) {
808 		if (tb_port_is_null(port))
809 			nports++;
810 	}
811 
812 	/* Must have DP buffer allocation (multiple USB4 ports) */
813 	if (nports > 2 && (min_dp_aux < 0 || min_dp_main < 0)) {
814 		tb_sw_warn(sw, "multiple USB4 ports require baMinDPaux/baMinDPmain\n");
815 		goto err_invalid;
816 	}
817 
818 	tb_switch_for_each_port(sw, port) {
819 		if (tb_port_is_dpout(port) && min_dp_main < 0) {
820 			tb_sw_warn(sw, "missing baMinDPmain");
821 			goto err_invalid;
822 		}
823 		if ((tb_port_is_dpin(port) || tb_port_is_dpout(port)) &&
824 		    min_dp_aux < 0) {
825 			tb_sw_warn(sw, "missing baMinDPaux");
826 			goto err_invalid;
827 		}
828 		if ((tb_port_is_usb3_down(port) || tb_port_is_usb3_up(port)) &&
829 		    max_usb3 < 0) {
830 			tb_sw_warn(sw, "missing baMaxUSB3");
831 			goto err_invalid;
832 		}
833 		if ((tb_port_is_pcie_down(port) || tb_port_is_pcie_up(port)) &&
834 		    max_pcie < 0) {
835 			tb_sw_warn(sw, "missing baMaxPCIe");
836 			goto err_invalid;
837 		}
838 	}
839 
840 	/*
841 	 * Buffer allocation passed the validation so we can use it in
842 	 * path creation.
843 	 */
844 	sw->credit_allocation = true;
845 	if (max_usb3 > 0)
846 		sw->max_usb3_credits = max_usb3;
847 	if (min_dp_aux > 0)
848 		sw->min_dp_aux_credits = min_dp_aux;
849 	if (min_dp_main > 0)
850 		sw->min_dp_main_credits = min_dp_main;
851 	if (max_pcie > 0)
852 		sw->max_pcie_credits = max_pcie;
853 	if (max_dma > 0)
854 		sw->max_dma_credits = max_dma;
855 
856 	return 0;
857 
858 err_invalid:
859 	return -EINVAL;
860 }
861 
862 /**
863  * usb4_switch_query_dp_resource() - Query availability of DP IN resource
864  * @sw: USB4 router
865  * @in: DP IN adapter
866  *
867  * For DP tunneling this function can be used to query availability of
868  * DP IN resource. Returns true if the resource is available for DP
869  * tunneling, false otherwise.
870  */
871 bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in)
872 {
873 	u32 metadata = in->port;
874 	u8 status;
875 	int ret;
876 
877 	ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &metadata,
878 			     &status);
879 	/*
880 	 * If DP resource allocation is not supported assume it is
881 	 * always available.
882 	 */
883 	if (ret == -EOPNOTSUPP)
884 		return true;
885 	if (ret)
886 		return false;
887 
888 	return !status;
889 }
890 
891 /**
892  * usb4_switch_alloc_dp_resource() - Allocate DP IN resource
893  * @sw: USB4 router
894  * @in: DP IN adapter
895  *
896  * Allocates DP IN resource for DP tunneling using USB4 router
897  * operations. If the resource was allocated returns %0. Otherwise
898  * returns negative errno, in particular %-EBUSY if the resource is
899  * already allocated.
900  */
901 int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
902 {
903 	u32 metadata = in->port;
904 	u8 status;
905 	int ret;
906 
907 	ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &metadata,
908 			     &status);
909 	if (ret == -EOPNOTSUPP)
910 		return 0;
911 	if (ret)
912 		return ret;
913 
914 	return status ? -EBUSY : 0;
915 }
916 
917 /**
918  * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource
919  * @sw: USB4 router
920  * @in: DP IN adapter
921  *
922  * Releases the previously allocated DP IN resource.
923  */
924 int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in)
925 {
926 	u32 metadata = in->port;
927 	u8 status;
928 	int ret;
929 
930 	ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &metadata,
931 			     &status);
932 	if (ret == -EOPNOTSUPP)
933 		return 0;
934 	if (ret)
935 		return ret;
936 
937 	return status ? -EIO : 0;
938 }
939 
940 static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port)
941 {
942 	struct tb_port *p;
943 	int usb4_idx = 0;
944 
945 	/* Assume port is primary */
946 	tb_switch_for_each_port(sw, p) {
947 		if (!tb_port_is_null(p))
948 			continue;
949 		if (tb_is_upstream_port(p))
950 			continue;
951 		if (!p->link_nr) {
952 			if (p == port)
953 				break;
954 			usb4_idx++;
955 		}
956 	}
957 
958 	return usb4_idx;
959 }
960 
961 /**
962  * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter
963  * @sw: USB4 router
964  * @port: USB4 port
965  *
966  * USB4 routers have direct mapping between USB4 ports and PCIe
967  * downstream adapters where the PCIe topology is extended. This
968  * function returns the corresponding downstream PCIe adapter or %NULL
969  * if no such mapping was possible.
970  */
971 struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw,
972 					  const struct tb_port *port)
973 {
974 	int usb4_idx = usb4_port_idx(sw, port);
975 	struct tb_port *p;
976 	int pcie_idx = 0;
977 
978 	/* Find PCIe down port matching usb4_port */
979 	tb_switch_for_each_port(sw, p) {
980 		if (!tb_port_is_pcie_down(p))
981 			continue;
982 
983 		if (pcie_idx == usb4_idx)
984 			return p;
985 
986 		pcie_idx++;
987 	}
988 
989 	return NULL;
990 }
991 
992 /**
993  * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter
994  * @sw: USB4 router
995  * @port: USB4 port
996  *
997  * USB4 routers have direct mapping between USB4 ports and USB 3.x
998  * downstream adapters where the USB 3.x topology is extended. This
999  * function returns the corresponding downstream USB 3.x adapter or
1000  * %NULL if no such mapping was possible.
1001  */
1002 struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw,
1003 					  const struct tb_port *port)
1004 {
1005 	int usb4_idx = usb4_port_idx(sw, port);
1006 	struct tb_port *p;
1007 	int usb_idx = 0;
1008 
1009 	/* Find USB3 down port matching usb4_port */
1010 	tb_switch_for_each_port(sw, p) {
1011 		if (!tb_port_is_usb3_down(p))
1012 			continue;
1013 
1014 		if (usb_idx == usb4_idx)
1015 			return p;
1016 
1017 		usb_idx++;
1018 	}
1019 
1020 	return NULL;
1021 }
1022 
1023 /**
1024  * usb4_switch_add_ports() - Add USB4 ports for this router
1025  * @sw: USB4 router
1026  *
1027  * For USB4 router finds all USB4 ports and registers devices for each.
1028  * Can be called to any router.
1029  *
1030  * Return %0 in case of success and negative errno in case of failure.
1031  */
1032 int usb4_switch_add_ports(struct tb_switch *sw)
1033 {
1034 	struct tb_port *port;
1035 
1036 	if (tb_switch_is_icm(sw) || !tb_switch_is_usb4(sw))
1037 		return 0;
1038 
1039 	tb_switch_for_each_port(sw, port) {
1040 		struct usb4_port *usb4;
1041 
1042 		if (!tb_port_is_null(port))
1043 			continue;
1044 		if (!port->cap_usb4)
1045 			continue;
1046 
1047 		usb4 = usb4_port_device_add(port);
1048 		if (IS_ERR(usb4)) {
1049 			usb4_switch_remove_ports(sw);
1050 			return PTR_ERR(usb4);
1051 		}
1052 
1053 		port->usb4 = usb4;
1054 	}
1055 
1056 	return 0;
1057 }
1058 
1059 /**
1060  * usb4_switch_remove_ports() - Removes USB4 ports from this router
1061  * @sw: USB4 router
1062  *
1063  * Unregisters previously registered USB4 ports.
1064  */
1065 void usb4_switch_remove_ports(struct tb_switch *sw)
1066 {
1067 	struct tb_port *port;
1068 
1069 	tb_switch_for_each_port(sw, port) {
1070 		if (port->usb4) {
1071 			usb4_port_device_remove(port->usb4);
1072 			port->usb4 = NULL;
1073 		}
1074 	}
1075 }
1076 
1077 /**
1078  * usb4_port_unlock() - Unlock USB4 downstream port
1079  * @port: USB4 port to unlock
1080  *
1081  * Unlocks USB4 downstream port so that the connection manager can
1082  * access the router below this port.
1083  */
1084 int usb4_port_unlock(struct tb_port *port)
1085 {
1086 	int ret;
1087 	u32 val;
1088 
1089 	ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1090 	if (ret)
1091 		return ret;
1092 
1093 	val &= ~ADP_CS_4_LCK;
1094 	return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1);
1095 }
1096 
1097 /**
1098  * usb4_port_hotplug_enable() - Enables hotplug for a port
1099  * @port: USB4 port to operate on
1100  *
1101  * Enables hot plug events on a given port. This is only intended
1102  * to be used on lane, DP-IN, and DP-OUT adapters.
1103  */
1104 int usb4_port_hotplug_enable(struct tb_port *port)
1105 {
1106 	int ret;
1107 	u32 val;
1108 
1109 	ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1110 	if (ret)
1111 		return ret;
1112 
1113 	val &= ~ADP_CS_5_DHP;
1114 	return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_5, 1);
1115 }
1116 
1117 /**
1118  * usb4_port_reset() - Issue downstream port reset
1119  * @port: USB4 port to reset
1120  *
1121  * Issues downstream port reset to @port.
1122  */
1123 int usb4_port_reset(struct tb_port *port)
1124 {
1125 	int ret;
1126 	u32 val;
1127 
1128 	if (!port->cap_usb4)
1129 		return -EINVAL;
1130 
1131 	ret = tb_port_read(port, &val, TB_CFG_PORT,
1132 			   port->cap_usb4 + PORT_CS_19, 1);
1133 	if (ret)
1134 		return ret;
1135 
1136 	val |= PORT_CS_19_DPR;
1137 
1138 	ret = tb_port_write(port, &val, TB_CFG_PORT,
1139 			    port->cap_usb4 + PORT_CS_19, 1);
1140 	if (ret)
1141 		return ret;
1142 
1143 	fsleep(10000);
1144 
1145 	ret = tb_port_read(port, &val, TB_CFG_PORT,
1146 			   port->cap_usb4 + PORT_CS_19, 1);
1147 	if (ret)
1148 		return ret;
1149 
1150 	val &= ~PORT_CS_19_DPR;
1151 
1152 	return tb_port_write(port, &val, TB_CFG_PORT,
1153 			     port->cap_usb4 + PORT_CS_19, 1);
1154 }
1155 
1156 static int usb4_port_set_configured(struct tb_port *port, bool configured)
1157 {
1158 	int ret;
1159 	u32 val;
1160 
1161 	if (!port->cap_usb4)
1162 		return -EINVAL;
1163 
1164 	ret = tb_port_read(port, &val, TB_CFG_PORT,
1165 			   port->cap_usb4 + PORT_CS_19, 1);
1166 	if (ret)
1167 		return ret;
1168 
1169 	if (configured)
1170 		val |= PORT_CS_19_PC;
1171 	else
1172 		val &= ~PORT_CS_19_PC;
1173 
1174 	return tb_port_write(port, &val, TB_CFG_PORT,
1175 			     port->cap_usb4 + PORT_CS_19, 1);
1176 }
1177 
1178 /**
1179  * usb4_port_configure() - Set USB4 port configured
1180  * @port: USB4 router
1181  *
1182  * Sets the USB4 link to be configured for power management purposes.
1183  */
1184 int usb4_port_configure(struct tb_port *port)
1185 {
1186 	return usb4_port_set_configured(port, true);
1187 }
1188 
1189 /**
1190  * usb4_port_unconfigure() - Set USB4 port unconfigured
1191  * @port: USB4 router
1192  *
1193  * Sets the USB4 link to be unconfigured for power management purposes.
1194  */
1195 void usb4_port_unconfigure(struct tb_port *port)
1196 {
1197 	usb4_port_set_configured(port, false);
1198 }
1199 
1200 static int usb4_set_xdomain_configured(struct tb_port *port, bool configured)
1201 {
1202 	int ret;
1203 	u32 val;
1204 
1205 	if (!port->cap_usb4)
1206 		return -EINVAL;
1207 
1208 	ret = tb_port_read(port, &val, TB_CFG_PORT,
1209 			   port->cap_usb4 + PORT_CS_19, 1);
1210 	if (ret)
1211 		return ret;
1212 
1213 	if (configured)
1214 		val |= PORT_CS_19_PID;
1215 	else
1216 		val &= ~PORT_CS_19_PID;
1217 
1218 	return tb_port_write(port, &val, TB_CFG_PORT,
1219 			     port->cap_usb4 + PORT_CS_19, 1);
1220 }
1221 
1222 /**
1223  * usb4_port_configure_xdomain() - Configure port for XDomain
1224  * @port: USB4 port connected to another host
1225  * @xd: XDomain that is connected to the port
1226  *
1227  * Marks the USB4 port as being connected to another host and updates
1228  * the link type. Returns %0 in success and negative errno in failure.
1229  */
1230 int usb4_port_configure_xdomain(struct tb_port *port, struct tb_xdomain *xd)
1231 {
1232 	xd->link_usb4 = link_is_usb4(port);
1233 	return usb4_set_xdomain_configured(port, true);
1234 }
1235 
1236 /**
1237  * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain
1238  * @port: USB4 port that was connected to another host
1239  *
1240  * Clears USB4 port from being marked as XDomain.
1241  */
1242 void usb4_port_unconfigure_xdomain(struct tb_port *port)
1243 {
1244 	usb4_set_xdomain_configured(port, false);
1245 }
1246 
1247 static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit,
1248 				  u32 value, int timeout_msec)
1249 {
1250 	ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec);
1251 
1252 	do {
1253 		u32 val;
1254 		int ret;
1255 
1256 		ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1);
1257 		if (ret)
1258 			return ret;
1259 
1260 		if ((val & bit) == value)
1261 			return 0;
1262 
1263 		usleep_range(50, 100);
1264 	} while (ktime_before(ktime_get(), timeout));
1265 
1266 	return -ETIMEDOUT;
1267 }
1268 
1269 static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords)
1270 {
1271 	if (dwords > USB4_DATA_DWORDS)
1272 		return -EINVAL;
1273 
1274 	return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1275 			    dwords);
1276 }
1277 
1278 static int usb4_port_write_data(struct tb_port *port, const void *data,
1279 				size_t dwords)
1280 {
1281 	if (dwords > USB4_DATA_DWORDS)
1282 		return -EINVAL;
1283 
1284 	return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2,
1285 			     dwords);
1286 }
1287 
1288 static int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target,
1289 			     u8 index, u8 reg, void *buf, u8 size)
1290 {
1291 	size_t dwords = DIV_ROUND_UP(size, 4);
1292 	int ret;
1293 	u32 val;
1294 
1295 	if (!port->cap_usb4)
1296 		return -EINVAL;
1297 
1298 	val = reg;
1299 	val |= size << PORT_CS_1_LENGTH_SHIFT;
1300 	val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1301 	if (target == USB4_SB_TARGET_RETIMER)
1302 		val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1303 	val |= PORT_CS_1_PND;
1304 
1305 	ret = tb_port_write(port, &val, TB_CFG_PORT,
1306 			    port->cap_usb4 + PORT_CS_1, 1);
1307 	if (ret)
1308 		return ret;
1309 
1310 	ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1311 				     PORT_CS_1_PND, 0, 500);
1312 	if (ret)
1313 		return ret;
1314 
1315 	ret = tb_port_read(port, &val, TB_CFG_PORT,
1316 			    port->cap_usb4 + PORT_CS_1, 1);
1317 	if (ret)
1318 		return ret;
1319 
1320 	if (val & PORT_CS_1_NR)
1321 		return -ENODEV;
1322 	if (val & PORT_CS_1_RC)
1323 		return -EIO;
1324 
1325 	return buf ? usb4_port_read_data(port, buf, dwords) : 0;
1326 }
1327 
1328 static int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target,
1329 			      u8 index, u8 reg, const void *buf, u8 size)
1330 {
1331 	size_t dwords = DIV_ROUND_UP(size, 4);
1332 	int ret;
1333 	u32 val;
1334 
1335 	if (!port->cap_usb4)
1336 		return -EINVAL;
1337 
1338 	if (buf) {
1339 		ret = usb4_port_write_data(port, buf, dwords);
1340 		if (ret)
1341 			return ret;
1342 	}
1343 
1344 	val = reg;
1345 	val |= size << PORT_CS_1_LENGTH_SHIFT;
1346 	val |= PORT_CS_1_WNR_WRITE;
1347 	val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK;
1348 	if (target == USB4_SB_TARGET_RETIMER)
1349 		val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT);
1350 	val |= PORT_CS_1_PND;
1351 
1352 	ret = tb_port_write(port, &val, TB_CFG_PORT,
1353 			    port->cap_usb4 + PORT_CS_1, 1);
1354 	if (ret)
1355 		return ret;
1356 
1357 	ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1,
1358 				     PORT_CS_1_PND, 0, 500);
1359 	if (ret)
1360 		return ret;
1361 
1362 	ret = tb_port_read(port, &val, TB_CFG_PORT,
1363 			    port->cap_usb4 + PORT_CS_1, 1);
1364 	if (ret)
1365 		return ret;
1366 
1367 	if (val & PORT_CS_1_NR)
1368 		return -ENODEV;
1369 	if (val & PORT_CS_1_RC)
1370 		return -EIO;
1371 
1372 	return 0;
1373 }
1374 
1375 static int usb4_port_sb_opcode_err_to_errno(u32 val)
1376 {
1377 	switch (val) {
1378 	case 0:
1379 		return 0;
1380 	case USB4_SB_OPCODE_ERR:
1381 		return -EAGAIN;
1382 	case USB4_SB_OPCODE_ONS:
1383 		return -EOPNOTSUPP;
1384 	default:
1385 		return -EIO;
1386 	}
1387 }
1388 
1389 static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target,
1390 			   u8 index, enum usb4_sb_opcode opcode, int timeout_msec)
1391 {
1392 	ktime_t timeout;
1393 	u32 val;
1394 	int ret;
1395 
1396 	val = opcode;
1397 	ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val,
1398 				 sizeof(val));
1399 	if (ret)
1400 		return ret;
1401 
1402 	timeout = ktime_add_ms(ktime_get(), timeout_msec);
1403 
1404 	do {
1405 		/* Check results */
1406 		ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE,
1407 					&val, sizeof(val));
1408 		if (ret)
1409 			return ret;
1410 
1411 		if (val != opcode)
1412 			return usb4_port_sb_opcode_err_to_errno(val);
1413 	} while (ktime_before(ktime_get(), timeout));
1414 
1415 	return -ETIMEDOUT;
1416 }
1417 
1418 static int usb4_port_set_router_offline(struct tb_port *port, bool offline)
1419 {
1420 	u32 val = !offline;
1421 	int ret;
1422 
1423 	ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1424 				  USB4_SB_METADATA, &val, sizeof(val));
1425 	if (ret)
1426 		return ret;
1427 
1428 	val = USB4_SB_OPCODE_ROUTER_OFFLINE;
1429 	return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1430 				  USB4_SB_OPCODE, &val, sizeof(val));
1431 }
1432 
1433 /**
1434  * usb4_port_router_offline() - Put the USB4 port to offline mode
1435  * @port: USB4 port
1436  *
1437  * This function puts the USB4 port into offline mode. In this mode the
1438  * port does not react on hotplug events anymore. This needs to be
1439  * called before retimer access is done when the USB4 links is not up.
1440  *
1441  * Returns %0 in case of success and negative errno if there was an
1442  * error.
1443  */
1444 int usb4_port_router_offline(struct tb_port *port)
1445 {
1446 	return usb4_port_set_router_offline(port, true);
1447 }
1448 
1449 /**
1450  * usb4_port_router_online() - Put the USB4 port back to online
1451  * @port: USB4 port
1452  *
1453  * Makes the USB4 port functional again.
1454  */
1455 int usb4_port_router_online(struct tb_port *port)
1456 {
1457 	return usb4_port_set_router_offline(port, false);
1458 }
1459 
1460 /**
1461  * usb4_port_enumerate_retimers() - Send RT broadcast transaction
1462  * @port: USB4 port
1463  *
1464  * This forces the USB4 port to send broadcast RT transaction which
1465  * makes the retimers on the link to assign index to themselves. Returns
1466  * %0 in case of success and negative errno if there was an error.
1467  */
1468 int usb4_port_enumerate_retimers(struct tb_port *port)
1469 {
1470 	u32 val;
1471 
1472 	val = USB4_SB_OPCODE_ENUMERATE_RETIMERS;
1473 	return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1474 				  USB4_SB_OPCODE, &val, sizeof(val));
1475 }
1476 
1477 /**
1478  * usb4_port_clx_supported() - Check if CLx is supported by the link
1479  * @port: Port to check for CLx support for
1480  *
1481  * PORT_CS_18_CPS bit reflects if the link supports CLx including
1482  * active cables (if connected on the link).
1483  */
1484 bool usb4_port_clx_supported(struct tb_port *port)
1485 {
1486 	int ret;
1487 	u32 val;
1488 
1489 	ret = tb_port_read(port, &val, TB_CFG_PORT,
1490 			   port->cap_usb4 + PORT_CS_18, 1);
1491 	if (ret)
1492 		return false;
1493 
1494 	return !!(val & PORT_CS_18_CPS);
1495 }
1496 
1497 /**
1498  * usb4_port_margining_caps() - Read USB4 port marginig capabilities
1499  * @port: USB4 port
1500  * @caps: Array with at least two elements to hold the results
1501  *
1502  * Reads the USB4 port lane margining capabilities into @caps.
1503  */
1504 int usb4_port_margining_caps(struct tb_port *port, u32 *caps)
1505 {
1506 	int ret;
1507 
1508 	ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1509 			      USB4_SB_OPCODE_READ_LANE_MARGINING_CAP, 500);
1510 	if (ret)
1511 		return ret;
1512 
1513 	return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
1514 				 USB4_SB_DATA, caps, sizeof(*caps) * 2);
1515 }
1516 
1517 /**
1518  * usb4_port_hw_margin() - Run hardware lane margining on port
1519  * @port: USB4 port
1520  * @lanes: Which lanes to run (must match the port capabilities). Can be
1521  *	   %0, %1 or %7.
1522  * @ber_level: BER level contour value
1523  * @timing: Perform timing margining instead of voltage
1524  * @right_high: Use Right/high margin instead of left/low
1525  * @results: Array with at least two elements to hold the results
1526  *
1527  * Runs hardware lane margining on USB4 port and returns the result in
1528  * @results.
1529  */
1530 int usb4_port_hw_margin(struct tb_port *port, unsigned int lanes,
1531 			unsigned int ber_level, bool timing, bool right_high,
1532 			u32 *results)
1533 {
1534 	u32 val;
1535 	int ret;
1536 
1537 	val = lanes;
1538 	if (timing)
1539 		val |= USB4_MARGIN_HW_TIME;
1540 	if (right_high)
1541 		val |= USB4_MARGIN_HW_RH;
1542 	if (ber_level)
1543 		val |= (ber_level << USB4_MARGIN_HW_BER_SHIFT) &
1544 			USB4_MARGIN_HW_BER_MASK;
1545 
1546 	ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1547 				 USB4_SB_METADATA, &val, sizeof(val));
1548 	if (ret)
1549 		return ret;
1550 
1551 	ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1552 			      USB4_SB_OPCODE_RUN_HW_LANE_MARGINING, 2500);
1553 	if (ret)
1554 		return ret;
1555 
1556 	return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
1557 				 USB4_SB_DATA, results, sizeof(*results) * 2);
1558 }
1559 
1560 /**
1561  * usb4_port_sw_margin() - Run software lane margining on port
1562  * @port: USB4 port
1563  * @lanes: Which lanes to run (must match the port capabilities). Can be
1564  *	   %0, %1 or %7.
1565  * @timing: Perform timing margining instead of voltage
1566  * @right_high: Use Right/high margin instead of left/low
1567  * @counter: What to do with the error counter
1568  *
1569  * Runs software lane margining on USB4 port. Read back the error
1570  * counters by calling usb4_port_sw_margin_errors(). Returns %0 in
1571  * success and negative errno otherwise.
1572  */
1573 int usb4_port_sw_margin(struct tb_port *port, unsigned int lanes, bool timing,
1574 			bool right_high, u32 counter)
1575 {
1576 	u32 val;
1577 	int ret;
1578 
1579 	val = lanes;
1580 	if (timing)
1581 		val |= USB4_MARGIN_SW_TIME;
1582 	if (right_high)
1583 		val |= USB4_MARGIN_SW_RH;
1584 	val |= (counter << USB4_MARGIN_SW_COUNTER_SHIFT) &
1585 		USB4_MARGIN_SW_COUNTER_MASK;
1586 
1587 	ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0,
1588 				 USB4_SB_METADATA, &val, sizeof(val));
1589 	if (ret)
1590 		return ret;
1591 
1592 	return usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1593 			       USB4_SB_OPCODE_RUN_SW_LANE_MARGINING, 2500);
1594 }
1595 
1596 /**
1597  * usb4_port_sw_margin_errors() - Read the software margining error counters
1598  * @port: USB4 port
1599  * @errors: Error metadata is copied here.
1600  *
1601  * This reads back the software margining error counters from the port.
1602  * Returns %0 in success and negative errno otherwise.
1603  */
1604 int usb4_port_sw_margin_errors(struct tb_port *port, u32 *errors)
1605 {
1606 	int ret;
1607 
1608 	ret = usb4_port_sb_op(port, USB4_SB_TARGET_ROUTER, 0,
1609 			      USB4_SB_OPCODE_READ_SW_MARGIN_ERR, 150);
1610 	if (ret)
1611 		return ret;
1612 
1613 	return usb4_port_sb_read(port, USB4_SB_TARGET_ROUTER, 0,
1614 				 USB4_SB_METADATA, errors, sizeof(*errors));
1615 }
1616 
1617 static inline int usb4_port_retimer_op(struct tb_port *port, u8 index,
1618 				       enum usb4_sb_opcode opcode,
1619 				       int timeout_msec)
1620 {
1621 	return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode,
1622 			       timeout_msec);
1623 }
1624 
1625 /**
1626  * usb4_port_retimer_set_inbound_sbtx() - Enable sideband channel transactions
1627  * @port: USB4 port
1628  * @index: Retimer index
1629  *
1630  * Enables sideband channel transations on SBTX. Can be used when USB4
1631  * link does not go up, for example if there is no device connected.
1632  */
1633 int usb4_port_retimer_set_inbound_sbtx(struct tb_port *port, u8 index)
1634 {
1635 	int ret;
1636 
1637 	ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1638 				   500);
1639 
1640 	if (ret != -ENODEV)
1641 		return ret;
1642 
1643 	/*
1644 	 * Per the USB4 retimer spec, the retimer is not required to
1645 	 * send an RT (Retimer Transaction) response for the first
1646 	 * SET_INBOUND_SBTX command
1647 	 */
1648 	return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX,
1649 				    500);
1650 }
1651 
1652 /**
1653  * usb4_port_retimer_unset_inbound_sbtx() - Disable sideband channel transactions
1654  * @port: USB4 port
1655  * @index: Retimer index
1656  *
1657  * Disables sideband channel transations on SBTX. The reverse of
1658  * usb4_port_retimer_set_inbound_sbtx().
1659  */
1660 int usb4_port_retimer_unset_inbound_sbtx(struct tb_port *port, u8 index)
1661 {
1662 	return usb4_port_retimer_op(port, index,
1663 				    USB4_SB_OPCODE_UNSET_INBOUND_SBTX, 500);
1664 }
1665 
1666 /**
1667  * usb4_port_retimer_read() - Read from retimer sideband registers
1668  * @port: USB4 port
1669  * @index: Retimer index
1670  * @reg: Sideband register to read
1671  * @buf: Data from @reg is stored here
1672  * @size: Number of bytes to read
1673  *
1674  * Function reads retimer sideband registers starting from @reg. The
1675  * retimer is connected to @port at @index. Returns %0 in case of
1676  * success, and read data is copied to @buf. If there is no retimer
1677  * present at given @index returns %-ENODEV. In any other failure
1678  * returns negative errno.
1679  */
1680 int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf,
1681 			   u8 size)
1682 {
1683 	return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index, reg, buf,
1684 				 size);
1685 }
1686 
1687 /**
1688  * usb4_port_retimer_write() - Write to retimer sideband registers
1689  * @port: USB4 port
1690  * @index: Retimer index
1691  * @reg: Sideband register to write
1692  * @buf: Data that is written starting from @reg
1693  * @size: Number of bytes to write
1694  *
1695  * Writes retimer sideband registers starting from @reg. The retimer is
1696  * connected to @port at @index. Returns %0 in case of success. If there
1697  * is no retimer present at given @index returns %-ENODEV. In any other
1698  * failure returns negative errno.
1699  */
1700 int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg,
1701 			    const void *buf, u8 size)
1702 {
1703 	return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, reg, buf,
1704 				  size);
1705 }
1706 
1707 /**
1708  * usb4_port_retimer_is_last() - Is the retimer last on-board retimer
1709  * @port: USB4 port
1710  * @index: Retimer index
1711  *
1712  * If the retimer at @index is last one (connected directly to the
1713  * Type-C port) this function returns %1. If it is not returns %0. If
1714  * the retimer is not present returns %-ENODEV. Otherwise returns
1715  * negative errno.
1716  */
1717 int usb4_port_retimer_is_last(struct tb_port *port, u8 index)
1718 {
1719 	u32 metadata;
1720 	int ret;
1721 
1722 	ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER,
1723 				   500);
1724 	if (ret)
1725 		return ret;
1726 
1727 	ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata,
1728 				     sizeof(metadata));
1729 	return ret ? ret : metadata & 1;
1730 }
1731 
1732 /**
1733  * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size
1734  * @port: USB4 port
1735  * @index: Retimer index
1736  *
1737  * Reads NVM sector size (in bytes) of a retimer at @index. This
1738  * operation can be used to determine whether the retimer supports NVM
1739  * upgrade for example. Returns sector size in bytes or negative errno
1740  * in case of error. Specifically returns %-ENODEV if there is no
1741  * retimer at @index.
1742  */
1743 int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index)
1744 {
1745 	u32 metadata;
1746 	int ret;
1747 
1748 	ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE,
1749 				   500);
1750 	if (ret)
1751 		return ret;
1752 
1753 	ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata,
1754 				     sizeof(metadata));
1755 	return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK;
1756 }
1757 
1758 /**
1759  * usb4_port_retimer_nvm_set_offset() - Set NVM write offset
1760  * @port: USB4 port
1761  * @index: Retimer index
1762  * @address: Start offset
1763  *
1764  * Exlicitly sets NVM write offset. Normally when writing to NVM this is
1765  * done automatically by usb4_port_retimer_nvm_write().
1766  *
1767  * Returns %0 in success and negative errno if there was a failure.
1768  */
1769 int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index,
1770 				     unsigned int address)
1771 {
1772 	u32 metadata, dwaddress;
1773 	int ret;
1774 
1775 	dwaddress = address / 4;
1776 	metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) &
1777 		  USB4_NVM_SET_OFFSET_MASK;
1778 
1779 	ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata,
1780 				      sizeof(metadata));
1781 	if (ret)
1782 		return ret;
1783 
1784 	return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET,
1785 				    500);
1786 }
1787 
1788 struct retimer_info {
1789 	struct tb_port *port;
1790 	u8 index;
1791 };
1792 
1793 static int usb4_port_retimer_nvm_write_next_block(void *data,
1794 	unsigned int dwaddress, const void *buf, size_t dwords)
1795 
1796 {
1797 	const struct retimer_info *info = data;
1798 	struct tb_port *port = info->port;
1799 	u8 index = info->index;
1800 	int ret;
1801 
1802 	ret = usb4_port_retimer_write(port, index, USB4_SB_DATA,
1803 				      buf, dwords * 4);
1804 	if (ret)
1805 		return ret;
1806 
1807 	return usb4_port_retimer_op(port, index,
1808 			USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000);
1809 }
1810 
1811 /**
1812  * usb4_port_retimer_nvm_write() - Write to retimer NVM
1813  * @port: USB4 port
1814  * @index: Retimer index
1815  * @address: Byte address where to start the write
1816  * @buf: Data to write
1817  * @size: Size in bytes how much to write
1818  *
1819  * Writes @size bytes from @buf to the retimer NVM. Used for NVM
1820  * upgrade. Returns %0 if the data was written successfully and negative
1821  * errno in case of failure. Specifically returns %-ENODEV if there is
1822  * no retimer at @index.
1823  */
1824 int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address,
1825 				const void *buf, size_t size)
1826 {
1827 	struct retimer_info info = { .port = port, .index = index };
1828 	int ret;
1829 
1830 	ret = usb4_port_retimer_nvm_set_offset(port, index, address);
1831 	if (ret)
1832 		return ret;
1833 
1834 	return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES,
1835 				 usb4_port_retimer_nvm_write_next_block, &info);
1836 }
1837 
1838 /**
1839  * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade
1840  * @port: USB4 port
1841  * @index: Retimer index
1842  *
1843  * After the new NVM image has been written via usb4_port_retimer_nvm_write()
1844  * this function can be used to trigger the NVM upgrade process. If
1845  * successful the retimer restarts with the new NVM and may not have the
1846  * index set so one needs to call usb4_port_enumerate_retimers() to
1847  * force index to be assigned.
1848  */
1849 int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index)
1850 {
1851 	u32 val;
1852 
1853 	/*
1854 	 * We need to use the raw operation here because once the
1855 	 * authentication completes the retimer index is not set anymore
1856 	 * so we do not get back the status now.
1857 	 */
1858 	val = USB4_SB_OPCODE_NVM_AUTH_WRITE;
1859 	return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index,
1860 				  USB4_SB_OPCODE, &val, sizeof(val));
1861 }
1862 
1863 /**
1864  * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade
1865  * @port: USB4 port
1866  * @index: Retimer index
1867  * @status: Raw status code read from metadata
1868  *
1869  * This can be called after usb4_port_retimer_nvm_authenticate() and
1870  * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade.
1871  *
1872  * Returns %0 if the authentication status was successfully read. The
1873  * completion metadata (the result) is then stored into @status. If
1874  * reading the status fails, returns negative errno.
1875  */
1876 int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index,
1877 					      u32 *status)
1878 {
1879 	u32 metadata, val;
1880 	int ret;
1881 
1882 	ret = usb4_port_retimer_read(port, index, USB4_SB_OPCODE, &val,
1883 				     sizeof(val));
1884 	if (ret)
1885 		return ret;
1886 
1887 	ret = usb4_port_sb_opcode_err_to_errno(val);
1888 	switch (ret) {
1889 	case 0:
1890 		*status = 0;
1891 		return 0;
1892 
1893 	case -EAGAIN:
1894 		ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA,
1895 					     &metadata, sizeof(metadata));
1896 		if (ret)
1897 			return ret;
1898 
1899 		*status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK;
1900 		return 0;
1901 
1902 	default:
1903 		return ret;
1904 	}
1905 }
1906 
1907 static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress,
1908 					    void *buf, size_t dwords)
1909 {
1910 	const struct retimer_info *info = data;
1911 	struct tb_port *port = info->port;
1912 	u8 index = info->index;
1913 	u32 metadata;
1914 	int ret;
1915 
1916 	metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT;
1917 	if (dwords < USB4_DATA_DWORDS)
1918 		metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT;
1919 
1920 	ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata,
1921 				      sizeof(metadata));
1922 	if (ret)
1923 		return ret;
1924 
1925 	ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500);
1926 	if (ret)
1927 		return ret;
1928 
1929 	return usb4_port_retimer_read(port, index, USB4_SB_DATA, buf,
1930 				      dwords * 4);
1931 }
1932 
1933 /**
1934  * usb4_port_retimer_nvm_read() - Read contents of retimer NVM
1935  * @port: USB4 port
1936  * @index: Retimer index
1937  * @address: NVM address (in bytes) to start reading
1938  * @buf: Data read from NVM is stored here
1939  * @size: Number of bytes to read
1940  *
1941  * Reads retimer NVM and copies the contents to @buf. Returns %0 if the
1942  * read was successful and negative errno in case of failure.
1943  * Specifically returns %-ENODEV if there is no retimer at @index.
1944  */
1945 int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index,
1946 			       unsigned int address, void *buf, size_t size)
1947 {
1948 	struct retimer_info info = { .port = port, .index = index };
1949 
1950 	return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES,
1951 				usb4_port_retimer_nvm_read_block, &info);
1952 }
1953 
1954 static inline unsigned int
1955 usb4_usb3_port_max_bandwidth(const struct tb_port *port, unsigned int bw)
1956 {
1957 	/* Take the possible bandwidth limitation into account */
1958 	if (port->max_bw)
1959 		return min(bw, port->max_bw);
1960 	return bw;
1961 }
1962 
1963 /**
1964  * usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate
1965  * @port: USB3 adapter port
1966  *
1967  * Return maximum supported link rate of a USB3 adapter in Mb/s.
1968  * Negative errno in case of error.
1969  */
1970 int usb4_usb3_port_max_link_rate(struct tb_port *port)
1971 {
1972 	int ret, lr;
1973 	u32 val;
1974 
1975 	if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
1976 		return -EINVAL;
1977 
1978 	ret = tb_port_read(port, &val, TB_CFG_PORT,
1979 			   port->cap_adap + ADP_USB3_CS_4, 1);
1980 	if (ret)
1981 		return ret;
1982 
1983 	lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT;
1984 	ret = lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000;
1985 
1986 	return usb4_usb3_port_max_bandwidth(port, ret);
1987 }
1988 
1989 /**
1990  * usb4_usb3_port_actual_link_rate() - Established USB3 link rate
1991  * @port: USB3 adapter port
1992  *
1993  * Return actual established link rate of a USB3 adapter in Mb/s. If the
1994  * link is not up returns %0 and negative errno in case of failure.
1995  */
1996 int usb4_usb3_port_actual_link_rate(struct tb_port *port)
1997 {
1998 	int ret, lr;
1999 	u32 val;
2000 
2001 	if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port))
2002 		return -EINVAL;
2003 
2004 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2005 			   port->cap_adap + ADP_USB3_CS_4, 1);
2006 	if (ret)
2007 		return ret;
2008 
2009 	if (!(val & ADP_USB3_CS_4_ULV))
2010 		return 0;
2011 
2012 	lr = val & ADP_USB3_CS_4_ALR_MASK;
2013 	ret = lr == ADP_USB3_CS_4_ALR_20G ? 20000 : 10000;
2014 
2015 	return usb4_usb3_port_max_bandwidth(port, ret);
2016 }
2017 
2018 static int usb4_usb3_port_cm_request(struct tb_port *port, bool request)
2019 {
2020 	int ret;
2021 	u32 val;
2022 
2023 	if (!tb_port_is_usb3_down(port))
2024 		return -EINVAL;
2025 	if (tb_route(port->sw))
2026 		return -EINVAL;
2027 
2028 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2029 			   port->cap_adap + ADP_USB3_CS_2, 1);
2030 	if (ret)
2031 		return ret;
2032 
2033 	if (request)
2034 		val |= ADP_USB3_CS_2_CMR;
2035 	else
2036 		val &= ~ADP_USB3_CS_2_CMR;
2037 
2038 	ret = tb_port_write(port, &val, TB_CFG_PORT,
2039 			    port->cap_adap + ADP_USB3_CS_2, 1);
2040 	if (ret)
2041 		return ret;
2042 
2043 	/*
2044 	 * We can use val here directly as the CMR bit is in the same place
2045 	 * as HCA. Just mask out others.
2046 	 */
2047 	val &= ADP_USB3_CS_2_CMR;
2048 	return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1,
2049 				      ADP_USB3_CS_1_HCA, val, 1500);
2050 }
2051 
2052 static inline int usb4_usb3_port_set_cm_request(struct tb_port *port)
2053 {
2054 	return usb4_usb3_port_cm_request(port, true);
2055 }
2056 
2057 static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port)
2058 {
2059 	return usb4_usb3_port_cm_request(port, false);
2060 }
2061 
2062 static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale)
2063 {
2064 	unsigned long uframes;
2065 
2066 	uframes = bw * 512UL << scale;
2067 	return DIV_ROUND_CLOSEST(uframes * 8000, MEGA);
2068 }
2069 
2070 static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale)
2071 {
2072 	unsigned long uframes;
2073 
2074 	/* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */
2075 	uframes = ((unsigned long)mbps * MEGA) / 8000;
2076 	return DIV_ROUND_UP(uframes, 512UL << scale);
2077 }
2078 
2079 static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port,
2080 						   int *upstream_bw,
2081 						   int *downstream_bw)
2082 {
2083 	u32 val, bw, scale;
2084 	int ret;
2085 
2086 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2087 			   port->cap_adap + ADP_USB3_CS_2, 1);
2088 	if (ret)
2089 		return ret;
2090 
2091 	ret = tb_port_read(port, &scale, TB_CFG_PORT,
2092 			   port->cap_adap + ADP_USB3_CS_3, 1);
2093 	if (ret)
2094 		return ret;
2095 
2096 	scale &= ADP_USB3_CS_3_SCALE_MASK;
2097 
2098 	bw = val & ADP_USB3_CS_2_AUBW_MASK;
2099 	*upstream_bw = usb3_bw_to_mbps(bw, scale);
2100 
2101 	bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT;
2102 	*downstream_bw = usb3_bw_to_mbps(bw, scale);
2103 
2104 	return 0;
2105 }
2106 
2107 /**
2108  * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3
2109  * @port: USB3 adapter port
2110  * @upstream_bw: Allocated upstream bandwidth is stored here
2111  * @downstream_bw: Allocated downstream bandwidth is stored here
2112  *
2113  * Stores currently allocated USB3 bandwidth into @upstream_bw and
2114  * @downstream_bw in Mb/s. Returns %0 in case of success and negative
2115  * errno in failure.
2116  */
2117 int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw,
2118 				       int *downstream_bw)
2119 {
2120 	int ret;
2121 
2122 	ret = usb4_usb3_port_set_cm_request(port);
2123 	if (ret)
2124 		return ret;
2125 
2126 	ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw,
2127 						      downstream_bw);
2128 	usb4_usb3_port_clear_cm_request(port);
2129 
2130 	return ret;
2131 }
2132 
2133 static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port,
2134 						  int *upstream_bw,
2135 						  int *downstream_bw)
2136 {
2137 	u32 val, bw, scale;
2138 	int ret;
2139 
2140 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2141 			   port->cap_adap + ADP_USB3_CS_1, 1);
2142 	if (ret)
2143 		return ret;
2144 
2145 	ret = tb_port_read(port, &scale, TB_CFG_PORT,
2146 			   port->cap_adap + ADP_USB3_CS_3, 1);
2147 	if (ret)
2148 		return ret;
2149 
2150 	scale &= ADP_USB3_CS_3_SCALE_MASK;
2151 
2152 	bw = val & ADP_USB3_CS_1_CUBW_MASK;
2153 	*upstream_bw = usb3_bw_to_mbps(bw, scale);
2154 
2155 	bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT;
2156 	*downstream_bw = usb3_bw_to_mbps(bw, scale);
2157 
2158 	return 0;
2159 }
2160 
2161 static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port,
2162 						    int upstream_bw,
2163 						    int downstream_bw)
2164 {
2165 	u32 val, ubw, dbw, scale;
2166 	int ret, max_bw;
2167 
2168 	/* Figure out suitable scale */
2169 	scale = 0;
2170 	max_bw = max(upstream_bw, downstream_bw);
2171 	while (scale < 64) {
2172 		if (mbps_to_usb3_bw(max_bw, scale) < 4096)
2173 			break;
2174 		scale++;
2175 	}
2176 
2177 	if (WARN_ON(scale >= 64))
2178 		return -EINVAL;
2179 
2180 	ret = tb_port_write(port, &scale, TB_CFG_PORT,
2181 			    port->cap_adap + ADP_USB3_CS_3, 1);
2182 	if (ret)
2183 		return ret;
2184 
2185 	ubw = mbps_to_usb3_bw(upstream_bw, scale);
2186 	dbw = mbps_to_usb3_bw(downstream_bw, scale);
2187 
2188 	tb_port_dbg(port, "scaled bandwidth %u/%u, scale %u\n", ubw, dbw, scale);
2189 
2190 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2191 			   port->cap_adap + ADP_USB3_CS_2, 1);
2192 	if (ret)
2193 		return ret;
2194 
2195 	val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK);
2196 	val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT;
2197 	val |= ubw;
2198 
2199 	return tb_port_write(port, &val, TB_CFG_PORT,
2200 			     port->cap_adap + ADP_USB3_CS_2, 1);
2201 }
2202 
2203 /**
2204  * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3
2205  * @port: USB3 adapter port
2206  * @upstream_bw: New upstream bandwidth
2207  * @downstream_bw: New downstream bandwidth
2208  *
2209  * This can be used to set how much bandwidth is allocated for the USB3
2210  * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the
2211  * new values programmed to the USB3 adapter allocation registers. If
2212  * the values are lower than what is currently consumed the allocation
2213  * is set to what is currently consumed instead (consumed bandwidth
2214  * cannot be taken away by CM). The actual new values are returned in
2215  * @upstream_bw and @downstream_bw.
2216  *
2217  * Returns %0 in case of success and negative errno if there was a
2218  * failure.
2219  */
2220 int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw,
2221 				      int *downstream_bw)
2222 {
2223 	int ret, consumed_up, consumed_down, allocate_up, allocate_down;
2224 
2225 	ret = usb4_usb3_port_set_cm_request(port);
2226 	if (ret)
2227 		return ret;
2228 
2229 	ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2230 						     &consumed_down);
2231 	if (ret)
2232 		goto err_request;
2233 
2234 	/* Don't allow it go lower than what is consumed */
2235 	allocate_up = max(*upstream_bw, consumed_up);
2236 	allocate_down = max(*downstream_bw, consumed_down);
2237 
2238 	ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up,
2239 						       allocate_down);
2240 	if (ret)
2241 		goto err_request;
2242 
2243 	*upstream_bw = allocate_up;
2244 	*downstream_bw = allocate_down;
2245 
2246 err_request:
2247 	usb4_usb3_port_clear_cm_request(port);
2248 	return ret;
2249 }
2250 
2251 /**
2252  * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth
2253  * @port: USB3 adapter port
2254  * @upstream_bw: New allocated upstream bandwidth
2255  * @downstream_bw: New allocated downstream bandwidth
2256  *
2257  * Releases USB3 allocated bandwidth down to what is actually consumed.
2258  * The new bandwidth is returned in @upstream_bw and @downstream_bw.
2259  *
2260  * Returns 0% in success and negative errno in case of failure.
2261  */
2262 int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw,
2263 				     int *downstream_bw)
2264 {
2265 	int ret, consumed_up, consumed_down;
2266 
2267 	ret = usb4_usb3_port_set_cm_request(port);
2268 	if (ret)
2269 		return ret;
2270 
2271 	ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up,
2272 						     &consumed_down);
2273 	if (ret)
2274 		goto err_request;
2275 
2276 	/*
2277 	 * Always keep 1000 Mb/s to make sure xHCI has at least some
2278 	 * bandwidth available for isochronous traffic.
2279 	 */
2280 	if (consumed_up < 1000)
2281 		consumed_up = 1000;
2282 	if (consumed_down < 1000)
2283 		consumed_down = 1000;
2284 
2285 	ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up,
2286 						       consumed_down);
2287 	if (ret)
2288 		goto err_request;
2289 
2290 	*upstream_bw = consumed_up;
2291 	*downstream_bw = consumed_down;
2292 
2293 err_request:
2294 	usb4_usb3_port_clear_cm_request(port);
2295 	return ret;
2296 }
2297 
2298 static bool is_usb4_dpin(const struct tb_port *port)
2299 {
2300 	if (!tb_port_is_dpin(port))
2301 		return false;
2302 	if (!tb_switch_is_usb4(port->sw))
2303 		return false;
2304 	return true;
2305 }
2306 
2307 /**
2308  * usb4_dp_port_set_cm_id() - Assign CM ID to the DP IN adapter
2309  * @port: DP IN adapter
2310  * @cm_id: CM ID to assign
2311  *
2312  * Sets CM ID for the @port. Returns %0 on success and negative errno
2313  * otherwise. Speficially returns %-EOPNOTSUPP if the @port does not
2314  * support this.
2315  */
2316 int usb4_dp_port_set_cm_id(struct tb_port *port, int cm_id)
2317 {
2318 	u32 val;
2319 	int ret;
2320 
2321 	if (!is_usb4_dpin(port))
2322 		return -EOPNOTSUPP;
2323 
2324 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2325 			   port->cap_adap + ADP_DP_CS_2, 1);
2326 	if (ret)
2327 		return ret;
2328 
2329 	val &= ~ADP_DP_CS_2_CM_ID_MASK;
2330 	val |= cm_id << ADP_DP_CS_2_CM_ID_SHIFT;
2331 
2332 	return tb_port_write(port, &val, TB_CFG_PORT,
2333 			     port->cap_adap + ADP_DP_CS_2, 1);
2334 }
2335 
2336 /**
2337  * usb4_dp_port_bandwidth_mode_supported() - Is the bandwidth allocation mode
2338  *					     supported
2339  * @port: DP IN adapter to check
2340  *
2341  * Can be called to any DP IN adapter. Returns true if the adapter
2342  * supports USB4 bandwidth allocation mode, false otherwise.
2343  */
2344 bool usb4_dp_port_bandwidth_mode_supported(struct tb_port *port)
2345 {
2346 	int ret;
2347 	u32 val;
2348 
2349 	if (!is_usb4_dpin(port))
2350 		return false;
2351 
2352 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2353 			   port->cap_adap + DP_LOCAL_CAP, 1);
2354 	if (ret)
2355 		return false;
2356 
2357 	return !!(val & DP_COMMON_CAP_BW_MODE);
2358 }
2359 
2360 /**
2361  * usb4_dp_port_bandwidth_mode_enabled() - Is the bandwidth allocation mode
2362  *					   enabled
2363  * @port: DP IN adapter to check
2364  *
2365  * Can be called to any DP IN adapter. Returns true if the bandwidth
2366  * allocation mode has been enabled, false otherwise.
2367  */
2368 bool usb4_dp_port_bandwidth_mode_enabled(struct tb_port *port)
2369 {
2370 	int ret;
2371 	u32 val;
2372 
2373 	if (!is_usb4_dpin(port))
2374 		return false;
2375 
2376 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2377 			   port->cap_adap + ADP_DP_CS_8, 1);
2378 	if (ret)
2379 		return false;
2380 
2381 	return !!(val & ADP_DP_CS_8_DPME);
2382 }
2383 
2384 /**
2385  * usb4_dp_port_set_cm_bandwidth_mode_supported() - Set/clear CM support for
2386  *						    bandwidth allocation mode
2387  * @port: DP IN adapter
2388  * @supported: Does the CM support bandwidth allocation mode
2389  *
2390  * Can be called to any DP IN adapter. Sets or clears the CM support bit
2391  * of the DP IN adapter. Returns %0 in success and negative errno
2392  * otherwise. Specifically returns %-OPNOTSUPP if the passed in adapter
2393  * does not support this.
2394  */
2395 int usb4_dp_port_set_cm_bandwidth_mode_supported(struct tb_port *port,
2396 						 bool supported)
2397 {
2398 	u32 val;
2399 	int ret;
2400 
2401 	if (!is_usb4_dpin(port))
2402 		return -EOPNOTSUPP;
2403 
2404 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2405 			   port->cap_adap + ADP_DP_CS_2, 1);
2406 	if (ret)
2407 		return ret;
2408 
2409 	if (supported)
2410 		val |= ADP_DP_CS_2_CMMS;
2411 	else
2412 		val &= ~ADP_DP_CS_2_CMMS;
2413 
2414 	return tb_port_write(port, &val, TB_CFG_PORT,
2415 			     port->cap_adap + ADP_DP_CS_2, 1);
2416 }
2417 
2418 /**
2419  * usb4_dp_port_group_id() - Return Group ID assigned for the adapter
2420  * @port: DP IN adapter
2421  *
2422  * Reads bandwidth allocation Group ID from the DP IN adapter and
2423  * returns it. If the adapter does not support setting Group_ID
2424  * %-EOPNOTSUPP is returned.
2425  */
2426 int usb4_dp_port_group_id(struct tb_port *port)
2427 {
2428 	u32 val;
2429 	int ret;
2430 
2431 	if (!is_usb4_dpin(port))
2432 		return -EOPNOTSUPP;
2433 
2434 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2435 			   port->cap_adap + ADP_DP_CS_2, 1);
2436 	if (ret)
2437 		return ret;
2438 
2439 	return (val & ADP_DP_CS_2_GROUP_ID_MASK) >> ADP_DP_CS_2_GROUP_ID_SHIFT;
2440 }
2441 
2442 /**
2443  * usb4_dp_port_set_group_id() - Set adapter Group ID
2444  * @port: DP IN adapter
2445  * @group_id: Group ID for the adapter
2446  *
2447  * Sets bandwidth allocation mode Group ID for the DP IN adapter.
2448  * Returns %0 in case of success and negative errno otherwise.
2449  * Specifically returns %-EOPNOTSUPP if the adapter does not support
2450  * this.
2451  */
2452 int usb4_dp_port_set_group_id(struct tb_port *port, int group_id)
2453 {
2454 	u32 val;
2455 	int ret;
2456 
2457 	if (!is_usb4_dpin(port))
2458 		return -EOPNOTSUPP;
2459 
2460 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2461 			   port->cap_adap + ADP_DP_CS_2, 1);
2462 	if (ret)
2463 		return ret;
2464 
2465 	val &= ~ADP_DP_CS_2_GROUP_ID_MASK;
2466 	val |= group_id << ADP_DP_CS_2_GROUP_ID_SHIFT;
2467 
2468 	return tb_port_write(port, &val, TB_CFG_PORT,
2469 			     port->cap_adap + ADP_DP_CS_2, 1);
2470 }
2471 
2472 /**
2473  * usb4_dp_port_nrd() - Read non-reduced rate and lanes
2474  * @port: DP IN adapter
2475  * @rate: Non-reduced rate in Mb/s is placed here
2476  * @lanes: Non-reduced lanes are placed here
2477  *
2478  * Reads the non-reduced rate and lanes from the DP IN adapter. Returns
2479  * %0 in success and negative errno otherwise. Specifically returns
2480  * %-EOPNOTSUPP if the adapter does not support this.
2481  */
2482 int usb4_dp_port_nrd(struct tb_port *port, int *rate, int *lanes)
2483 {
2484 	u32 val, tmp;
2485 	int ret;
2486 
2487 	if (!is_usb4_dpin(port))
2488 		return -EOPNOTSUPP;
2489 
2490 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2491 			   port->cap_adap + ADP_DP_CS_2, 1);
2492 	if (ret)
2493 		return ret;
2494 
2495 	tmp = (val & ADP_DP_CS_2_NRD_MLR_MASK) >> ADP_DP_CS_2_NRD_MLR_SHIFT;
2496 	switch (tmp) {
2497 	case DP_COMMON_CAP_RATE_RBR:
2498 		*rate = 1620;
2499 		break;
2500 	case DP_COMMON_CAP_RATE_HBR:
2501 		*rate = 2700;
2502 		break;
2503 	case DP_COMMON_CAP_RATE_HBR2:
2504 		*rate = 5400;
2505 		break;
2506 	case DP_COMMON_CAP_RATE_HBR3:
2507 		*rate = 8100;
2508 		break;
2509 	}
2510 
2511 	tmp = val & ADP_DP_CS_2_NRD_MLC_MASK;
2512 	switch (tmp) {
2513 	case DP_COMMON_CAP_1_LANE:
2514 		*lanes = 1;
2515 		break;
2516 	case DP_COMMON_CAP_2_LANES:
2517 		*lanes = 2;
2518 		break;
2519 	case DP_COMMON_CAP_4_LANES:
2520 		*lanes = 4;
2521 		break;
2522 	}
2523 
2524 	return 0;
2525 }
2526 
2527 /**
2528  * usb4_dp_port_set_nrd() - Set non-reduced rate and lanes
2529  * @port: DP IN adapter
2530  * @rate: Non-reduced rate in Mb/s
2531  * @lanes: Non-reduced lanes
2532  *
2533  * Before the capabilities reduction this function can be used to set
2534  * the non-reduced values for the DP IN adapter. Returns %0 in success
2535  * and negative errno otherwise. If the adapter does not support this
2536  * %-EOPNOTSUPP is returned.
2537  */
2538 int usb4_dp_port_set_nrd(struct tb_port *port, int rate, int lanes)
2539 {
2540 	u32 val;
2541 	int ret;
2542 
2543 	if (!is_usb4_dpin(port))
2544 		return -EOPNOTSUPP;
2545 
2546 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2547 			   port->cap_adap + ADP_DP_CS_2, 1);
2548 	if (ret)
2549 		return ret;
2550 
2551 	val &= ~ADP_DP_CS_2_NRD_MLR_MASK;
2552 
2553 	switch (rate) {
2554 	case 1620:
2555 		break;
2556 	case 2700:
2557 		val |= (DP_COMMON_CAP_RATE_HBR << ADP_DP_CS_2_NRD_MLR_SHIFT)
2558 			& ADP_DP_CS_2_NRD_MLR_MASK;
2559 		break;
2560 	case 5400:
2561 		val |= (DP_COMMON_CAP_RATE_HBR2 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2562 			& ADP_DP_CS_2_NRD_MLR_MASK;
2563 		break;
2564 	case 8100:
2565 		val |= (DP_COMMON_CAP_RATE_HBR3 << ADP_DP_CS_2_NRD_MLR_SHIFT)
2566 			& ADP_DP_CS_2_NRD_MLR_MASK;
2567 		break;
2568 	default:
2569 		return -EINVAL;
2570 	}
2571 
2572 	val &= ~ADP_DP_CS_2_NRD_MLC_MASK;
2573 
2574 	switch (lanes) {
2575 	case 1:
2576 		break;
2577 	case 2:
2578 		val |= DP_COMMON_CAP_2_LANES;
2579 		break;
2580 	case 4:
2581 		val |= DP_COMMON_CAP_4_LANES;
2582 		break;
2583 	default:
2584 		return -EINVAL;
2585 	}
2586 
2587 	return tb_port_write(port, &val, TB_CFG_PORT,
2588 			     port->cap_adap + ADP_DP_CS_2, 1);
2589 }
2590 
2591 /**
2592  * usb4_dp_port_granularity() - Return granularity for the bandwidth values
2593  * @port: DP IN adapter
2594  *
2595  * Reads the programmed granularity from @port. If the DP IN adapter does
2596  * not support bandwidth allocation mode returns %-EOPNOTSUPP and negative
2597  * errno in other error cases.
2598  */
2599 int usb4_dp_port_granularity(struct tb_port *port)
2600 {
2601 	u32 val;
2602 	int ret;
2603 
2604 	if (!is_usb4_dpin(port))
2605 		return -EOPNOTSUPP;
2606 
2607 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2608 			   port->cap_adap + ADP_DP_CS_2, 1);
2609 	if (ret)
2610 		return ret;
2611 
2612 	val &= ADP_DP_CS_2_GR_MASK;
2613 	val >>= ADP_DP_CS_2_GR_SHIFT;
2614 
2615 	switch (val) {
2616 	case ADP_DP_CS_2_GR_0_25G:
2617 		return 250;
2618 	case ADP_DP_CS_2_GR_0_5G:
2619 		return 500;
2620 	case ADP_DP_CS_2_GR_1G:
2621 		return 1000;
2622 	}
2623 
2624 	return -EINVAL;
2625 }
2626 
2627 /**
2628  * usb4_dp_port_set_granularity() - Set granularity for the bandwidth values
2629  * @port: DP IN adapter
2630  * @granularity: Granularity in Mb/s. Supported values: 1000, 500 and 250.
2631  *
2632  * Sets the granularity used with the estimated, allocated and requested
2633  * bandwidth. Returns %0 in success and negative errno otherwise. If the
2634  * adapter does not support this %-EOPNOTSUPP is returned.
2635  */
2636 int usb4_dp_port_set_granularity(struct tb_port *port, int granularity)
2637 {
2638 	u32 val;
2639 	int ret;
2640 
2641 	if (!is_usb4_dpin(port))
2642 		return -EOPNOTSUPP;
2643 
2644 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2645 			   port->cap_adap + ADP_DP_CS_2, 1);
2646 	if (ret)
2647 		return ret;
2648 
2649 	val &= ~ADP_DP_CS_2_GR_MASK;
2650 
2651 	switch (granularity) {
2652 	case 250:
2653 		val |= ADP_DP_CS_2_GR_0_25G << ADP_DP_CS_2_GR_SHIFT;
2654 		break;
2655 	case 500:
2656 		val |= ADP_DP_CS_2_GR_0_5G << ADP_DP_CS_2_GR_SHIFT;
2657 		break;
2658 	case 1000:
2659 		val |= ADP_DP_CS_2_GR_1G << ADP_DP_CS_2_GR_SHIFT;
2660 		break;
2661 	default:
2662 		return -EINVAL;
2663 	}
2664 
2665 	return tb_port_write(port, &val, TB_CFG_PORT,
2666 			     port->cap_adap + ADP_DP_CS_2, 1);
2667 }
2668 
2669 /**
2670  * usb4_dp_port_set_estimated_bandwidth() - Set estimated bandwidth
2671  * @port: DP IN adapter
2672  * @bw: Estimated bandwidth in Mb/s.
2673  *
2674  * Sets the estimated bandwidth to @bw. Set the granularity by calling
2675  * usb4_dp_port_set_granularity() before calling this. The @bw is round
2676  * down to the closest granularity multiplier. Returns %0 in success
2677  * and negative errno otherwise. Specifically returns %-EOPNOTSUPP if
2678  * the adapter does not support this.
2679  */
2680 int usb4_dp_port_set_estimated_bandwidth(struct tb_port *port, int bw)
2681 {
2682 	u32 val, granularity;
2683 	int ret;
2684 
2685 	if (!is_usb4_dpin(port))
2686 		return -EOPNOTSUPP;
2687 
2688 	ret = usb4_dp_port_granularity(port);
2689 	if (ret < 0)
2690 		return ret;
2691 	granularity = ret;
2692 
2693 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2694 			   port->cap_adap + ADP_DP_CS_2, 1);
2695 	if (ret)
2696 		return ret;
2697 
2698 	val &= ~ADP_DP_CS_2_ESTIMATED_BW_MASK;
2699 	val |= (bw / granularity) << ADP_DP_CS_2_ESTIMATED_BW_SHIFT;
2700 
2701 	return tb_port_write(port, &val, TB_CFG_PORT,
2702 			     port->cap_adap + ADP_DP_CS_2, 1);
2703 }
2704 
2705 /**
2706  * usb4_dp_port_allocated_bandwidth() - Return allocated bandwidth
2707  * @port: DP IN adapter
2708  *
2709  * Reads and returns allocated bandwidth for @port in Mb/s (taking into
2710  * account the programmed granularity). Returns negative errno in case
2711  * of error.
2712  */
2713 int usb4_dp_port_allocated_bandwidth(struct tb_port *port)
2714 {
2715 	u32 val, granularity;
2716 	int ret;
2717 
2718 	if (!is_usb4_dpin(port))
2719 		return -EOPNOTSUPP;
2720 
2721 	ret = usb4_dp_port_granularity(port);
2722 	if (ret < 0)
2723 		return ret;
2724 	granularity = ret;
2725 
2726 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2727 			   port->cap_adap + DP_STATUS, 1);
2728 	if (ret)
2729 		return ret;
2730 
2731 	val &= DP_STATUS_ALLOCATED_BW_MASK;
2732 	val >>= DP_STATUS_ALLOCATED_BW_SHIFT;
2733 
2734 	return val * granularity;
2735 }
2736 
2737 static int __usb4_dp_port_set_cm_ack(struct tb_port *port, bool ack)
2738 {
2739 	u32 val;
2740 	int ret;
2741 
2742 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2743 			   port->cap_adap + ADP_DP_CS_2, 1);
2744 	if (ret)
2745 		return ret;
2746 
2747 	if (ack)
2748 		val |= ADP_DP_CS_2_CA;
2749 	else
2750 		val &= ~ADP_DP_CS_2_CA;
2751 
2752 	return tb_port_write(port, &val, TB_CFG_PORT,
2753 			     port->cap_adap + ADP_DP_CS_2, 1);
2754 }
2755 
2756 static inline int usb4_dp_port_set_cm_ack(struct tb_port *port)
2757 {
2758 	return __usb4_dp_port_set_cm_ack(port, true);
2759 }
2760 
2761 static int usb4_dp_port_wait_and_clear_cm_ack(struct tb_port *port,
2762 					      int timeout_msec)
2763 {
2764 	ktime_t end;
2765 	u32 val;
2766 	int ret;
2767 
2768 	ret = __usb4_dp_port_set_cm_ack(port, false);
2769 	if (ret)
2770 		return ret;
2771 
2772 	end = ktime_add_ms(ktime_get(), timeout_msec);
2773 	do {
2774 		ret = tb_port_read(port, &val, TB_CFG_PORT,
2775 				   port->cap_adap + ADP_DP_CS_8, 1);
2776 		if (ret)
2777 			return ret;
2778 
2779 		if (!(val & ADP_DP_CS_8_DR))
2780 			break;
2781 
2782 		usleep_range(50, 100);
2783 	} while (ktime_before(ktime_get(), end));
2784 
2785 	if (val & ADP_DP_CS_8_DR)
2786 		return -ETIMEDOUT;
2787 
2788 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2789 			   port->cap_adap + ADP_DP_CS_2, 1);
2790 	if (ret)
2791 		return ret;
2792 
2793 	val &= ~ADP_DP_CS_2_CA;
2794 	return tb_port_write(port, &val, TB_CFG_PORT,
2795 			     port->cap_adap + ADP_DP_CS_2, 1);
2796 }
2797 
2798 /**
2799  * usb4_dp_port_allocate_bandwidth() - Set allocated bandwidth
2800  * @port: DP IN adapter
2801  * @bw: New allocated bandwidth in Mb/s
2802  *
2803  * Communicates the new allocated bandwidth with the DPCD (graphics
2804  * driver). Takes into account the programmed granularity. Returns %0 in
2805  * success and negative errno in case of error.
2806  */
2807 int usb4_dp_port_allocate_bandwidth(struct tb_port *port, int bw)
2808 {
2809 	u32 val, granularity;
2810 	int ret;
2811 
2812 	if (!is_usb4_dpin(port))
2813 		return -EOPNOTSUPP;
2814 
2815 	ret = usb4_dp_port_granularity(port);
2816 	if (ret < 0)
2817 		return ret;
2818 	granularity = ret;
2819 
2820 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2821 			   port->cap_adap + DP_STATUS, 1);
2822 	if (ret)
2823 		return ret;
2824 
2825 	val &= ~DP_STATUS_ALLOCATED_BW_MASK;
2826 	val |= (bw / granularity) << DP_STATUS_ALLOCATED_BW_SHIFT;
2827 
2828 	ret = tb_port_write(port, &val, TB_CFG_PORT,
2829 			    port->cap_adap + DP_STATUS, 1);
2830 	if (ret)
2831 		return ret;
2832 
2833 	ret = usb4_dp_port_set_cm_ack(port);
2834 	if (ret)
2835 		return ret;
2836 
2837 	return usb4_dp_port_wait_and_clear_cm_ack(port, 500);
2838 }
2839 
2840 /**
2841  * usb4_dp_port_requested_bandwidth() - Read requested bandwidth
2842  * @port: DP IN adapter
2843  *
2844  * Reads the DPCD (graphics driver) requested bandwidth and returns it
2845  * in Mb/s. Takes the programmed granularity into account. In case of
2846  * error returns negative errno. Specifically returns %-EOPNOTSUPP if
2847  * the adapter does not support bandwidth allocation mode, and %ENODATA
2848  * if there is no active bandwidth request from the graphics driver.
2849  */
2850 int usb4_dp_port_requested_bandwidth(struct tb_port *port)
2851 {
2852 	u32 val, granularity;
2853 	int ret;
2854 
2855 	if (!is_usb4_dpin(port))
2856 		return -EOPNOTSUPP;
2857 
2858 	ret = usb4_dp_port_granularity(port);
2859 	if (ret < 0)
2860 		return ret;
2861 	granularity = ret;
2862 
2863 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2864 			   port->cap_adap + ADP_DP_CS_8, 1);
2865 	if (ret)
2866 		return ret;
2867 
2868 	if (!(val & ADP_DP_CS_8_DR))
2869 		return -ENODATA;
2870 
2871 	return (val & ADP_DP_CS_8_REQUESTED_BW_MASK) * granularity;
2872 }
2873 
2874 /**
2875  * usb4_pci_port_set_ext_encapsulation() - Enable/disable extended encapsulation
2876  * @port: PCIe adapter
2877  * @enable: Enable/disable extended encapsulation
2878  *
2879  * Enables or disables extended encapsulation used in PCIe tunneling. Caller
2880  * needs to make sure both adapters support this before enabling. Returns %0 on
2881  * success and negative errno otherwise.
2882  */
2883 int usb4_pci_port_set_ext_encapsulation(struct tb_port *port, bool enable)
2884 {
2885 	u32 val;
2886 	int ret;
2887 
2888 	if (!tb_port_is_pcie_up(port) && !tb_port_is_pcie_down(port))
2889 		return -EINVAL;
2890 
2891 	ret = tb_port_read(port, &val, TB_CFG_PORT,
2892 			   port->cap_adap + ADP_PCIE_CS_1, 1);
2893 	if (ret)
2894 		return ret;
2895 
2896 	if (enable)
2897 		val |= ADP_PCIE_CS_1_EE;
2898 	else
2899 		val &= ~ADP_PCIE_CS_1_EE;
2900 
2901 	return tb_port_write(port, &val, TB_CFG_PORT,
2902 			     port->cap_adap + ADP_PCIE_CS_1, 1);
2903 }
2904