1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * USB4 specific functionality 4 * 5 * Copyright (C) 2019, Intel Corporation 6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * Rajmohan Mani <rajmohan.mani@intel.com> 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/ktime.h> 12 13 #include "sb_regs.h" 14 #include "tb.h" 15 16 #define USB4_DATA_RETRIES 3 17 18 enum usb4_sb_target { 19 USB4_SB_TARGET_ROUTER, 20 USB4_SB_TARGET_PARTNER, 21 USB4_SB_TARGET_RETIMER, 22 }; 23 24 #define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2) 25 #define USB4_NVM_READ_OFFSET_SHIFT 2 26 #define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24) 27 #define USB4_NVM_READ_LENGTH_SHIFT 24 28 29 #define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK 30 #define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT 31 32 #define USB4_DROM_ADDRESS_MASK GENMASK(14, 2) 33 #define USB4_DROM_ADDRESS_SHIFT 2 34 #define USB4_DROM_SIZE_MASK GENMASK(19, 15) 35 #define USB4_DROM_SIZE_SHIFT 15 36 37 #define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0) 38 39 #define USB4_BA_LENGTH_MASK GENMASK(7, 0) 40 #define USB4_BA_INDEX_MASK GENMASK(15, 0) 41 42 enum usb4_ba_index { 43 USB4_BA_MAX_USB3 = 0x1, 44 USB4_BA_MIN_DP_AUX = 0x2, 45 USB4_BA_MIN_DP_MAIN = 0x3, 46 USB4_BA_MAX_PCIE = 0x4, 47 USB4_BA_MAX_HI = 0x5, 48 }; 49 50 #define USB4_BA_VALUE_MASK GENMASK(31, 16) 51 #define USB4_BA_VALUE_SHIFT 16 52 53 static int usb4_native_switch_op(struct tb_switch *sw, u16 opcode, 54 u32 *metadata, u8 *status, 55 const void *tx_data, size_t tx_dwords, 56 void *rx_data, size_t rx_dwords) 57 { 58 u32 val; 59 int ret; 60 61 if (metadata) { 62 ret = tb_sw_write(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1); 63 if (ret) 64 return ret; 65 } 66 if (tx_dwords) { 67 ret = tb_sw_write(sw, tx_data, TB_CFG_SWITCH, ROUTER_CS_9, 68 tx_dwords); 69 if (ret) 70 return ret; 71 } 72 73 val = opcode | ROUTER_CS_26_OV; 74 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); 75 if (ret) 76 return ret; 77 78 ret = tb_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500); 79 if (ret) 80 return ret; 81 82 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); 83 if (ret) 84 return ret; 85 86 if (val & ROUTER_CS_26_ONS) 87 return -EOPNOTSUPP; 88 89 if (status) 90 *status = (val & ROUTER_CS_26_STATUS_MASK) >> 91 ROUTER_CS_26_STATUS_SHIFT; 92 93 if (metadata) { 94 ret = tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1); 95 if (ret) 96 return ret; 97 } 98 if (rx_dwords) { 99 ret = tb_sw_read(sw, rx_data, TB_CFG_SWITCH, ROUTER_CS_9, 100 rx_dwords); 101 if (ret) 102 return ret; 103 } 104 105 return 0; 106 } 107 108 static int __usb4_switch_op(struct tb_switch *sw, u16 opcode, u32 *metadata, 109 u8 *status, const void *tx_data, size_t tx_dwords, 110 void *rx_data, size_t rx_dwords) 111 { 112 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops; 113 114 if (tx_dwords > NVM_DATA_DWORDS || rx_dwords > NVM_DATA_DWORDS) 115 return -EINVAL; 116 117 /* 118 * If the connection manager implementation provides USB4 router 119 * operation proxy callback, call it here instead of running the 120 * operation natively. 121 */ 122 if (cm_ops->usb4_switch_op) { 123 int ret; 124 125 ret = cm_ops->usb4_switch_op(sw, opcode, metadata, status, 126 tx_data, tx_dwords, rx_data, 127 rx_dwords); 128 if (ret != -EOPNOTSUPP) 129 return ret; 130 131 /* 132 * If the proxy was not supported then run the native 133 * router operation instead. 134 */ 135 } 136 137 return usb4_native_switch_op(sw, opcode, metadata, status, tx_data, 138 tx_dwords, rx_data, rx_dwords); 139 } 140 141 static inline int usb4_switch_op(struct tb_switch *sw, u16 opcode, 142 u32 *metadata, u8 *status) 143 { 144 return __usb4_switch_op(sw, opcode, metadata, status, NULL, 0, NULL, 0); 145 } 146 147 static inline int usb4_switch_op_data(struct tb_switch *sw, u16 opcode, 148 u32 *metadata, u8 *status, 149 const void *tx_data, size_t tx_dwords, 150 void *rx_data, size_t rx_dwords) 151 { 152 return __usb4_switch_op(sw, opcode, metadata, status, tx_data, 153 tx_dwords, rx_data, rx_dwords); 154 } 155 156 static void usb4_switch_check_wakes(struct tb_switch *sw) 157 { 158 struct tb_port *port; 159 bool wakeup = false; 160 u32 val; 161 162 if (!device_may_wakeup(&sw->dev)) 163 return; 164 165 if (tb_route(sw)) { 166 if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1)) 167 return; 168 169 tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n", 170 (val & ROUTER_CS_6_WOPS) ? "yes" : "no", 171 (val & ROUTER_CS_6_WOUS) ? "yes" : "no"); 172 173 wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS); 174 } 175 176 /* Check for any connected downstream ports for USB4 wake */ 177 tb_switch_for_each_port(sw, port) { 178 if (!tb_port_has_remote(port)) 179 continue; 180 181 if (tb_port_read(port, &val, TB_CFG_PORT, 182 port->cap_usb4 + PORT_CS_18, 1)) 183 break; 184 185 tb_port_dbg(port, "USB4 wake: %s\n", 186 (val & PORT_CS_18_WOU4S) ? "yes" : "no"); 187 188 if (val & PORT_CS_18_WOU4S) 189 wakeup = true; 190 } 191 192 if (wakeup) 193 pm_wakeup_event(&sw->dev, 0); 194 } 195 196 static bool link_is_usb4(struct tb_port *port) 197 { 198 u32 val; 199 200 if (!port->cap_usb4) 201 return false; 202 203 if (tb_port_read(port, &val, TB_CFG_PORT, 204 port->cap_usb4 + PORT_CS_18, 1)) 205 return false; 206 207 return !(val & PORT_CS_18_TCM); 208 } 209 210 /** 211 * usb4_switch_setup() - Additional setup for USB4 device 212 * @sw: USB4 router to setup 213 * 214 * USB4 routers need additional settings in order to enable all the 215 * tunneling. This function enables USB and PCIe tunneling if it can be 216 * enabled (e.g the parent switch also supports them). If USB tunneling 217 * is not available for some reason (like that there is Thunderbolt 3 218 * switch upstream) then the internal xHCI controller is enabled 219 * instead. 220 */ 221 int usb4_switch_setup(struct tb_switch *sw) 222 { 223 struct tb_port *downstream_port; 224 struct tb_switch *parent; 225 bool tbt3, xhci; 226 u32 val = 0; 227 int ret; 228 229 usb4_switch_check_wakes(sw); 230 231 if (!tb_route(sw)) 232 return 0; 233 234 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1); 235 if (ret) 236 return ret; 237 238 parent = tb_switch_parent(sw); 239 downstream_port = tb_port_at(tb_route(sw), parent); 240 sw->link_usb4 = link_is_usb4(downstream_port); 241 tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT"); 242 243 xhci = val & ROUTER_CS_6_HCI; 244 tbt3 = !(val & ROUTER_CS_6_TNS); 245 246 tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n", 247 tbt3 ? "yes" : "no", xhci ? "yes" : "no"); 248 249 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 250 if (ret) 251 return ret; 252 253 if (tb_acpi_may_tunnel_usb3() && sw->link_usb4 && 254 tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) { 255 val |= ROUTER_CS_5_UTO; 256 xhci = false; 257 } 258 259 /* 260 * Only enable PCIe tunneling if the parent router supports it 261 * and it is not disabled. 262 */ 263 if (tb_acpi_may_tunnel_pcie() && 264 tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) { 265 val |= ROUTER_CS_5_PTO; 266 /* 267 * xHCI can be enabled if PCIe tunneling is supported 268 * and the parent does not have any USB3 dowstream 269 * adapters (so we cannot do USB 3.x tunneling). 270 */ 271 if (xhci) 272 val |= ROUTER_CS_5_HCO; 273 } 274 275 /* TBT3 supported by the CM */ 276 val |= ROUTER_CS_5_C3S; 277 /* Tunneling configuration is ready now */ 278 val |= ROUTER_CS_5_CV; 279 280 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 281 if (ret) 282 return ret; 283 284 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR, 285 ROUTER_CS_6_CR, 50); 286 } 287 288 /** 289 * usb4_switch_read_uid() - Read UID from USB4 router 290 * @sw: USB4 router 291 * @uid: UID is stored here 292 * 293 * Reads 64-bit UID from USB4 router config space. 294 */ 295 int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid) 296 { 297 return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2); 298 } 299 300 static int usb4_switch_drom_read_block(void *data, 301 unsigned int dwaddress, void *buf, 302 size_t dwords) 303 { 304 struct tb_switch *sw = data; 305 u8 status = 0; 306 u32 metadata; 307 int ret; 308 309 metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK; 310 metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) & 311 USB4_DROM_ADDRESS_MASK; 312 313 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_DROM_READ, &metadata, 314 &status, NULL, 0, buf, dwords); 315 if (ret) 316 return ret; 317 318 return status ? -EIO : 0; 319 } 320 321 /** 322 * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM 323 * @sw: USB4 router 324 * @address: Byte address inside DROM to start reading 325 * @buf: Buffer where the DROM content is stored 326 * @size: Number of bytes to read from DROM 327 * 328 * Uses USB4 router operations to read router DROM. For devices this 329 * should always work but for hosts it may return %-EOPNOTSUPP in which 330 * case the host router does not have DROM. 331 */ 332 int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf, 333 size_t size) 334 { 335 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES, 336 usb4_switch_drom_read_block, sw); 337 } 338 339 /** 340 * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding 341 * @sw: USB4 router 342 * 343 * Checks whether conditions are met so that lane bonding can be 344 * established with the upstream router. Call only for device routers. 345 */ 346 bool usb4_switch_lane_bonding_possible(struct tb_switch *sw) 347 { 348 struct tb_port *up; 349 int ret; 350 u32 val; 351 352 up = tb_upstream_port(sw); 353 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1); 354 if (ret) 355 return false; 356 357 return !!(val & PORT_CS_18_BE); 358 } 359 360 /** 361 * usb4_switch_set_wake() - Enabled/disable wake 362 * @sw: USB4 router 363 * @flags: Wakeup flags (%0 to disable) 364 * 365 * Enables/disables router to wake up from sleep. 366 */ 367 int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags) 368 { 369 struct tb_port *port; 370 u64 route = tb_route(sw); 371 u32 val; 372 int ret; 373 374 /* 375 * Enable wakes coming from all USB4 downstream ports (from 376 * child routers). For device routers do this also for the 377 * upstream USB4 port. 378 */ 379 tb_switch_for_each_port(sw, port) { 380 if (!tb_port_is_null(port)) 381 continue; 382 if (!route && tb_is_upstream_port(port)) 383 continue; 384 if (!port->cap_usb4) 385 continue; 386 387 ret = tb_port_read(port, &val, TB_CFG_PORT, 388 port->cap_usb4 + PORT_CS_19, 1); 389 if (ret) 390 return ret; 391 392 val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4); 393 394 if (tb_is_upstream_port(port)) { 395 val |= PORT_CS_19_WOU4; 396 } else { 397 bool configured = val & PORT_CS_19_PC; 398 399 if ((flags & TB_WAKE_ON_CONNECT) && !configured) 400 val |= PORT_CS_19_WOC; 401 if ((flags & TB_WAKE_ON_DISCONNECT) && configured) 402 val |= PORT_CS_19_WOD; 403 if ((flags & TB_WAKE_ON_USB4) && configured) 404 val |= PORT_CS_19_WOU4; 405 } 406 407 ret = tb_port_write(port, &val, TB_CFG_PORT, 408 port->cap_usb4 + PORT_CS_19, 1); 409 if (ret) 410 return ret; 411 } 412 413 /* 414 * Enable wakes from PCIe, USB 3.x and DP on this router. Only 415 * needed for device routers. 416 */ 417 if (route) { 418 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 419 if (ret) 420 return ret; 421 422 val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU | ROUTER_CS_5_WOD); 423 if (flags & TB_WAKE_ON_USB3) 424 val |= ROUTER_CS_5_WOU; 425 if (flags & TB_WAKE_ON_PCIE) 426 val |= ROUTER_CS_5_WOP; 427 if (flags & TB_WAKE_ON_DP) 428 val |= ROUTER_CS_5_WOD; 429 430 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 431 if (ret) 432 return ret; 433 } 434 435 return 0; 436 } 437 438 /** 439 * usb4_switch_set_sleep() - Prepare the router to enter sleep 440 * @sw: USB4 router 441 * 442 * Sets sleep bit for the router. Returns when the router sleep ready 443 * bit has been asserted. 444 */ 445 int usb4_switch_set_sleep(struct tb_switch *sw) 446 { 447 int ret; 448 u32 val; 449 450 /* Set sleep bit and wait for sleep ready to be asserted */ 451 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 452 if (ret) 453 return ret; 454 455 val |= ROUTER_CS_5_SLP; 456 457 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 458 if (ret) 459 return ret; 460 461 return tb_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR, 462 ROUTER_CS_6_SLPR, 500); 463 } 464 465 /** 466 * usb4_switch_nvm_sector_size() - Return router NVM sector size 467 * @sw: USB4 router 468 * 469 * If the router supports NVM operations this function returns the NVM 470 * sector size in bytes. If NVM operations are not supported returns 471 * %-EOPNOTSUPP. 472 */ 473 int usb4_switch_nvm_sector_size(struct tb_switch *sw) 474 { 475 u32 metadata; 476 u8 status; 477 int ret; 478 479 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &metadata, 480 &status); 481 if (ret) 482 return ret; 483 484 if (status) 485 return status == 0x2 ? -EOPNOTSUPP : -EIO; 486 487 return metadata & USB4_NVM_SECTOR_SIZE_MASK; 488 } 489 490 static int usb4_switch_nvm_read_block(void *data, 491 unsigned int dwaddress, void *buf, size_t dwords) 492 { 493 struct tb_switch *sw = data; 494 u8 status = 0; 495 u32 metadata; 496 int ret; 497 498 metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) & 499 USB4_NVM_READ_LENGTH_MASK; 500 metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) & 501 USB4_NVM_READ_OFFSET_MASK; 502 503 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_READ, &metadata, 504 &status, NULL, 0, buf, dwords); 505 if (ret) 506 return ret; 507 508 return status ? -EIO : 0; 509 } 510 511 /** 512 * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM 513 * @sw: USB4 router 514 * @address: Starting address in bytes 515 * @buf: Read data is placed here 516 * @size: How many bytes to read 517 * 518 * Reads NVM contents of the router. If NVM is not supported returns 519 * %-EOPNOTSUPP. 520 */ 521 int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf, 522 size_t size) 523 { 524 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES, 525 usb4_switch_nvm_read_block, sw); 526 } 527 528 /** 529 * usb4_switch_nvm_set_offset() - Set NVM write offset 530 * @sw: USB4 router 531 * @address: Start offset 532 * 533 * Explicitly sets NVM write offset. Normally when writing to NVM this 534 * is done automatically by usb4_switch_nvm_write(). 535 * 536 * Returns %0 in success and negative errno if there was a failure. 537 */ 538 int usb4_switch_nvm_set_offset(struct tb_switch *sw, unsigned int address) 539 { 540 u32 metadata, dwaddress; 541 u8 status = 0; 542 int ret; 543 544 dwaddress = address / 4; 545 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) & 546 USB4_NVM_SET_OFFSET_MASK; 547 548 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &metadata, 549 &status); 550 if (ret) 551 return ret; 552 553 return status ? -EIO : 0; 554 } 555 556 static int usb4_switch_nvm_write_next_block(void *data, unsigned int dwaddress, 557 const void *buf, size_t dwords) 558 { 559 struct tb_switch *sw = data; 560 u8 status; 561 int ret; 562 563 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_WRITE, NULL, &status, 564 buf, dwords, NULL, 0); 565 if (ret) 566 return ret; 567 568 return status ? -EIO : 0; 569 } 570 571 /** 572 * usb4_switch_nvm_write() - Write to the router NVM 573 * @sw: USB4 router 574 * @address: Start address where to write in bytes 575 * @buf: Pointer to the data to write 576 * @size: Size of @buf in bytes 577 * 578 * Writes @buf to the router NVM using USB4 router operations. If NVM 579 * write is not supported returns %-EOPNOTSUPP. 580 */ 581 int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address, 582 const void *buf, size_t size) 583 { 584 int ret; 585 586 ret = usb4_switch_nvm_set_offset(sw, address); 587 if (ret) 588 return ret; 589 590 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES, 591 usb4_switch_nvm_write_next_block, sw); 592 } 593 594 /** 595 * usb4_switch_nvm_authenticate() - Authenticate new NVM 596 * @sw: USB4 router 597 * 598 * After the new NVM has been written via usb4_switch_nvm_write(), this 599 * function triggers NVM authentication process. The router gets power 600 * cycled and if the authentication is successful the new NVM starts 601 * running. In case of failure returns negative errno. 602 * 603 * The caller should call usb4_switch_nvm_authenticate_status() to read 604 * the status of the authentication after power cycle. It should be the 605 * first router operation to avoid the status being lost. 606 */ 607 int usb4_switch_nvm_authenticate(struct tb_switch *sw) 608 { 609 int ret; 610 611 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, NULL, NULL); 612 switch (ret) { 613 /* 614 * The router is power cycled once NVM_AUTH is started so it is 615 * expected to get any of the following errors back. 616 */ 617 case -EACCES: 618 case -ENOTCONN: 619 case -ETIMEDOUT: 620 return 0; 621 622 default: 623 return ret; 624 } 625 } 626 627 /** 628 * usb4_switch_nvm_authenticate_status() - Read status of last NVM authenticate 629 * @sw: USB4 router 630 * @status: Status code of the operation 631 * 632 * The function checks if there is status available from the last NVM 633 * authenticate router operation. If there is status then %0 is returned 634 * and the status code is placed in @status. Returns negative errno in case 635 * of failure. 636 * 637 * Must be called before any other router operation. 638 */ 639 int usb4_switch_nvm_authenticate_status(struct tb_switch *sw, u32 *status) 640 { 641 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops; 642 u16 opcode; 643 u32 val; 644 int ret; 645 646 if (cm_ops->usb4_switch_nvm_authenticate_status) { 647 ret = cm_ops->usb4_switch_nvm_authenticate_status(sw, status); 648 if (ret != -EOPNOTSUPP) 649 return ret; 650 } 651 652 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); 653 if (ret) 654 return ret; 655 656 /* Check that the opcode is correct */ 657 opcode = val & ROUTER_CS_26_OPCODE_MASK; 658 if (opcode == USB4_SWITCH_OP_NVM_AUTH) { 659 if (val & ROUTER_CS_26_OV) 660 return -EBUSY; 661 if (val & ROUTER_CS_26_ONS) 662 return -EOPNOTSUPP; 663 664 *status = (val & ROUTER_CS_26_STATUS_MASK) >> 665 ROUTER_CS_26_STATUS_SHIFT; 666 } else { 667 *status = 0; 668 } 669 670 return 0; 671 } 672 673 /** 674 * usb4_switch_credits_init() - Read buffer allocation parameters 675 * @sw: USB4 router 676 * 677 * Reads @sw buffer allocation parameters and initializes @sw buffer 678 * allocation fields accordingly. Specifically @sw->credits_allocation 679 * is set to %true if these parameters can be used in tunneling. 680 * 681 * Returns %0 on success and negative errno otherwise. 682 */ 683 int usb4_switch_credits_init(struct tb_switch *sw) 684 { 685 int max_usb3, min_dp_aux, min_dp_main, max_pcie, max_dma; 686 int ret, length, i, nports; 687 const struct tb_port *port; 688 u32 data[NVM_DATA_DWORDS]; 689 u32 metadata = 0; 690 u8 status = 0; 691 692 memset(data, 0, sizeof(data)); 693 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_BUFFER_ALLOC, &metadata, 694 &status, NULL, 0, data, ARRAY_SIZE(data)); 695 if (ret) 696 return ret; 697 if (status) 698 return -EIO; 699 700 length = metadata & USB4_BA_LENGTH_MASK; 701 if (WARN_ON(length > ARRAY_SIZE(data))) 702 return -EMSGSIZE; 703 704 max_usb3 = -1; 705 min_dp_aux = -1; 706 min_dp_main = -1; 707 max_pcie = -1; 708 max_dma = -1; 709 710 tb_sw_dbg(sw, "credit allocation parameters:\n"); 711 712 for (i = 0; i < length; i++) { 713 u16 index, value; 714 715 index = data[i] & USB4_BA_INDEX_MASK; 716 value = (data[i] & USB4_BA_VALUE_MASK) >> USB4_BA_VALUE_SHIFT; 717 718 switch (index) { 719 case USB4_BA_MAX_USB3: 720 tb_sw_dbg(sw, " USB3: %u\n", value); 721 max_usb3 = value; 722 break; 723 case USB4_BA_MIN_DP_AUX: 724 tb_sw_dbg(sw, " DP AUX: %u\n", value); 725 min_dp_aux = value; 726 break; 727 case USB4_BA_MIN_DP_MAIN: 728 tb_sw_dbg(sw, " DP main: %u\n", value); 729 min_dp_main = value; 730 break; 731 case USB4_BA_MAX_PCIE: 732 tb_sw_dbg(sw, " PCIe: %u\n", value); 733 max_pcie = value; 734 break; 735 case USB4_BA_MAX_HI: 736 tb_sw_dbg(sw, " DMA: %u\n", value); 737 max_dma = value; 738 break; 739 default: 740 tb_sw_dbg(sw, " unknown credit allocation index %#x, skipping\n", 741 index); 742 break; 743 } 744 } 745 746 /* 747 * Validate the buffer allocation preferences. If we find 748 * issues, log a warning and fall back using the hard-coded 749 * values. 750 */ 751 752 /* Host router must report baMaxHI */ 753 if (!tb_route(sw) && max_dma < 0) { 754 tb_sw_warn(sw, "host router is missing baMaxHI\n"); 755 goto err_invalid; 756 } 757 758 nports = 0; 759 tb_switch_for_each_port(sw, port) { 760 if (tb_port_is_null(port)) 761 nports++; 762 } 763 764 /* Must have DP buffer allocation (multiple USB4 ports) */ 765 if (nports > 2 && (min_dp_aux < 0 || min_dp_main < 0)) { 766 tb_sw_warn(sw, "multiple USB4 ports require baMinDPaux/baMinDPmain\n"); 767 goto err_invalid; 768 } 769 770 tb_switch_for_each_port(sw, port) { 771 if (tb_port_is_dpout(port) && min_dp_main < 0) { 772 tb_sw_warn(sw, "missing baMinDPmain"); 773 goto err_invalid; 774 } 775 if ((tb_port_is_dpin(port) || tb_port_is_dpout(port)) && 776 min_dp_aux < 0) { 777 tb_sw_warn(sw, "missing baMinDPaux"); 778 goto err_invalid; 779 } 780 if ((tb_port_is_usb3_down(port) || tb_port_is_usb3_up(port)) && 781 max_usb3 < 0) { 782 tb_sw_warn(sw, "missing baMaxUSB3"); 783 goto err_invalid; 784 } 785 if ((tb_port_is_pcie_down(port) || tb_port_is_pcie_up(port)) && 786 max_pcie < 0) { 787 tb_sw_warn(sw, "missing baMaxPCIe"); 788 goto err_invalid; 789 } 790 } 791 792 /* 793 * Buffer allocation passed the validation so we can use it in 794 * path creation. 795 */ 796 sw->credit_allocation = true; 797 if (max_usb3 > 0) 798 sw->max_usb3_credits = max_usb3; 799 if (min_dp_aux > 0) 800 sw->min_dp_aux_credits = min_dp_aux; 801 if (min_dp_main > 0) 802 sw->min_dp_main_credits = min_dp_main; 803 if (max_pcie > 0) 804 sw->max_pcie_credits = max_pcie; 805 if (max_dma > 0) 806 sw->max_dma_credits = max_dma; 807 808 return 0; 809 810 err_invalid: 811 return -EINVAL; 812 } 813 814 /** 815 * usb4_switch_query_dp_resource() - Query availability of DP IN resource 816 * @sw: USB4 router 817 * @in: DP IN adapter 818 * 819 * For DP tunneling this function can be used to query availability of 820 * DP IN resource. Returns true if the resource is available for DP 821 * tunneling, false otherwise. 822 */ 823 bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in) 824 { 825 u32 metadata = in->port; 826 u8 status; 827 int ret; 828 829 ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &metadata, 830 &status); 831 /* 832 * If DP resource allocation is not supported assume it is 833 * always available. 834 */ 835 if (ret == -EOPNOTSUPP) 836 return true; 837 else if (ret) 838 return false; 839 840 return !status; 841 } 842 843 /** 844 * usb4_switch_alloc_dp_resource() - Allocate DP IN resource 845 * @sw: USB4 router 846 * @in: DP IN adapter 847 * 848 * Allocates DP IN resource for DP tunneling using USB4 router 849 * operations. If the resource was allocated returns %0. Otherwise 850 * returns negative errno, in particular %-EBUSY if the resource is 851 * already allocated. 852 */ 853 int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in) 854 { 855 u32 metadata = in->port; 856 u8 status; 857 int ret; 858 859 ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &metadata, 860 &status); 861 if (ret == -EOPNOTSUPP) 862 return 0; 863 else if (ret) 864 return ret; 865 866 return status ? -EBUSY : 0; 867 } 868 869 /** 870 * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource 871 * @sw: USB4 router 872 * @in: DP IN adapter 873 * 874 * Releases the previously allocated DP IN resource. 875 */ 876 int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in) 877 { 878 u32 metadata = in->port; 879 u8 status; 880 int ret; 881 882 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &metadata, 883 &status); 884 if (ret == -EOPNOTSUPP) 885 return 0; 886 else if (ret) 887 return ret; 888 889 return status ? -EIO : 0; 890 } 891 892 static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port) 893 { 894 struct tb_port *p; 895 int usb4_idx = 0; 896 897 /* Assume port is primary */ 898 tb_switch_for_each_port(sw, p) { 899 if (!tb_port_is_null(p)) 900 continue; 901 if (tb_is_upstream_port(p)) 902 continue; 903 if (!p->link_nr) { 904 if (p == port) 905 break; 906 usb4_idx++; 907 } 908 } 909 910 return usb4_idx; 911 } 912 913 /** 914 * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter 915 * @sw: USB4 router 916 * @port: USB4 port 917 * 918 * USB4 routers have direct mapping between USB4 ports and PCIe 919 * downstream adapters where the PCIe topology is extended. This 920 * function returns the corresponding downstream PCIe adapter or %NULL 921 * if no such mapping was possible. 922 */ 923 struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw, 924 const struct tb_port *port) 925 { 926 int usb4_idx = usb4_port_idx(sw, port); 927 struct tb_port *p; 928 int pcie_idx = 0; 929 930 /* Find PCIe down port matching usb4_port */ 931 tb_switch_for_each_port(sw, p) { 932 if (!tb_port_is_pcie_down(p)) 933 continue; 934 935 if (pcie_idx == usb4_idx) 936 return p; 937 938 pcie_idx++; 939 } 940 941 return NULL; 942 } 943 944 /** 945 * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter 946 * @sw: USB4 router 947 * @port: USB4 port 948 * 949 * USB4 routers have direct mapping between USB4 ports and USB 3.x 950 * downstream adapters where the USB 3.x topology is extended. This 951 * function returns the corresponding downstream USB 3.x adapter or 952 * %NULL if no such mapping was possible. 953 */ 954 struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw, 955 const struct tb_port *port) 956 { 957 int usb4_idx = usb4_port_idx(sw, port); 958 struct tb_port *p; 959 int usb_idx = 0; 960 961 /* Find USB3 down port matching usb4_port */ 962 tb_switch_for_each_port(sw, p) { 963 if (!tb_port_is_usb3_down(p)) 964 continue; 965 966 if (usb_idx == usb4_idx) 967 return p; 968 969 usb_idx++; 970 } 971 972 return NULL; 973 } 974 975 /** 976 * usb4_switch_add_ports() - Add USB4 ports for this router 977 * @sw: USB4 router 978 * 979 * For USB4 router finds all USB4 ports and registers devices for each. 980 * Can be called to any router. 981 * 982 * Return %0 in case of success and negative errno in case of failure. 983 */ 984 int usb4_switch_add_ports(struct tb_switch *sw) 985 { 986 struct tb_port *port; 987 988 if (tb_switch_is_icm(sw) || !tb_switch_is_usb4(sw)) 989 return 0; 990 991 tb_switch_for_each_port(sw, port) { 992 struct usb4_port *usb4; 993 994 if (!tb_port_is_null(port)) 995 continue; 996 if (!port->cap_usb4) 997 continue; 998 999 usb4 = usb4_port_device_add(port); 1000 if (IS_ERR(usb4)) { 1001 usb4_switch_remove_ports(sw); 1002 return PTR_ERR(usb4); 1003 } 1004 1005 port->usb4 = usb4; 1006 } 1007 1008 return 0; 1009 } 1010 1011 /** 1012 * usb4_switch_remove_ports() - Removes USB4 ports from this router 1013 * @sw: USB4 router 1014 * 1015 * Unregisters previously registered USB4 ports. 1016 */ 1017 void usb4_switch_remove_ports(struct tb_switch *sw) 1018 { 1019 struct tb_port *port; 1020 1021 tb_switch_for_each_port(sw, port) { 1022 if (port->usb4) { 1023 usb4_port_device_remove(port->usb4); 1024 port->usb4 = NULL; 1025 } 1026 } 1027 } 1028 1029 /** 1030 * usb4_port_unlock() - Unlock USB4 downstream port 1031 * @port: USB4 port to unlock 1032 * 1033 * Unlocks USB4 downstream port so that the connection manager can 1034 * access the router below this port. 1035 */ 1036 int usb4_port_unlock(struct tb_port *port) 1037 { 1038 int ret; 1039 u32 val; 1040 1041 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1); 1042 if (ret) 1043 return ret; 1044 1045 val &= ~ADP_CS_4_LCK; 1046 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1); 1047 } 1048 1049 static int usb4_port_set_configured(struct tb_port *port, bool configured) 1050 { 1051 int ret; 1052 u32 val; 1053 1054 if (!port->cap_usb4) 1055 return -EINVAL; 1056 1057 ret = tb_port_read(port, &val, TB_CFG_PORT, 1058 port->cap_usb4 + PORT_CS_19, 1); 1059 if (ret) 1060 return ret; 1061 1062 if (configured) 1063 val |= PORT_CS_19_PC; 1064 else 1065 val &= ~PORT_CS_19_PC; 1066 1067 return tb_port_write(port, &val, TB_CFG_PORT, 1068 port->cap_usb4 + PORT_CS_19, 1); 1069 } 1070 1071 /** 1072 * usb4_port_configure() - Set USB4 port configured 1073 * @port: USB4 router 1074 * 1075 * Sets the USB4 link to be configured for power management purposes. 1076 */ 1077 int usb4_port_configure(struct tb_port *port) 1078 { 1079 return usb4_port_set_configured(port, true); 1080 } 1081 1082 /** 1083 * usb4_port_unconfigure() - Set USB4 port unconfigured 1084 * @port: USB4 router 1085 * 1086 * Sets the USB4 link to be unconfigured for power management purposes. 1087 */ 1088 void usb4_port_unconfigure(struct tb_port *port) 1089 { 1090 usb4_port_set_configured(port, false); 1091 } 1092 1093 static int usb4_set_xdomain_configured(struct tb_port *port, bool configured) 1094 { 1095 int ret; 1096 u32 val; 1097 1098 if (!port->cap_usb4) 1099 return -EINVAL; 1100 1101 ret = tb_port_read(port, &val, TB_CFG_PORT, 1102 port->cap_usb4 + PORT_CS_19, 1); 1103 if (ret) 1104 return ret; 1105 1106 if (configured) 1107 val |= PORT_CS_19_PID; 1108 else 1109 val &= ~PORT_CS_19_PID; 1110 1111 return tb_port_write(port, &val, TB_CFG_PORT, 1112 port->cap_usb4 + PORT_CS_19, 1); 1113 } 1114 1115 /** 1116 * usb4_port_configure_xdomain() - Configure port for XDomain 1117 * @port: USB4 port connected to another host 1118 * @xd: XDomain that is connected to the port 1119 * 1120 * Marks the USB4 port as being connected to another host and updates 1121 * the link type. Returns %0 in success and negative errno in failure. 1122 */ 1123 int usb4_port_configure_xdomain(struct tb_port *port, struct tb_xdomain *xd) 1124 { 1125 xd->link_usb4 = link_is_usb4(port); 1126 return usb4_set_xdomain_configured(port, true); 1127 } 1128 1129 /** 1130 * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain 1131 * @port: USB4 port that was connected to another host 1132 * 1133 * Clears USB4 port from being marked as XDomain. 1134 */ 1135 void usb4_port_unconfigure_xdomain(struct tb_port *port) 1136 { 1137 usb4_set_xdomain_configured(port, false); 1138 } 1139 1140 static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit, 1141 u32 value, int timeout_msec) 1142 { 1143 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec); 1144 1145 do { 1146 u32 val; 1147 int ret; 1148 1149 ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1); 1150 if (ret) 1151 return ret; 1152 1153 if ((val & bit) == value) 1154 return 0; 1155 1156 usleep_range(50, 100); 1157 } while (ktime_before(ktime_get(), timeout)); 1158 1159 return -ETIMEDOUT; 1160 } 1161 1162 static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords) 1163 { 1164 if (dwords > NVM_DATA_DWORDS) 1165 return -EINVAL; 1166 1167 return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2, 1168 dwords); 1169 } 1170 1171 static int usb4_port_write_data(struct tb_port *port, const void *data, 1172 size_t dwords) 1173 { 1174 if (dwords > NVM_DATA_DWORDS) 1175 return -EINVAL; 1176 1177 return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2, 1178 dwords); 1179 } 1180 1181 static int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target, 1182 u8 index, u8 reg, void *buf, u8 size) 1183 { 1184 size_t dwords = DIV_ROUND_UP(size, 4); 1185 int ret; 1186 u32 val; 1187 1188 if (!port->cap_usb4) 1189 return -EINVAL; 1190 1191 val = reg; 1192 val |= size << PORT_CS_1_LENGTH_SHIFT; 1193 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK; 1194 if (target == USB4_SB_TARGET_RETIMER) 1195 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT); 1196 val |= PORT_CS_1_PND; 1197 1198 ret = tb_port_write(port, &val, TB_CFG_PORT, 1199 port->cap_usb4 + PORT_CS_1, 1); 1200 if (ret) 1201 return ret; 1202 1203 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1, 1204 PORT_CS_1_PND, 0, 500); 1205 if (ret) 1206 return ret; 1207 1208 ret = tb_port_read(port, &val, TB_CFG_PORT, 1209 port->cap_usb4 + PORT_CS_1, 1); 1210 if (ret) 1211 return ret; 1212 1213 if (val & PORT_CS_1_NR) 1214 return -ENODEV; 1215 if (val & PORT_CS_1_RC) 1216 return -EIO; 1217 1218 return buf ? usb4_port_read_data(port, buf, dwords) : 0; 1219 } 1220 1221 static int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target, 1222 u8 index, u8 reg, const void *buf, u8 size) 1223 { 1224 size_t dwords = DIV_ROUND_UP(size, 4); 1225 int ret; 1226 u32 val; 1227 1228 if (!port->cap_usb4) 1229 return -EINVAL; 1230 1231 if (buf) { 1232 ret = usb4_port_write_data(port, buf, dwords); 1233 if (ret) 1234 return ret; 1235 } 1236 1237 val = reg; 1238 val |= size << PORT_CS_1_LENGTH_SHIFT; 1239 val |= PORT_CS_1_WNR_WRITE; 1240 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK; 1241 if (target == USB4_SB_TARGET_RETIMER) 1242 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT); 1243 val |= PORT_CS_1_PND; 1244 1245 ret = tb_port_write(port, &val, TB_CFG_PORT, 1246 port->cap_usb4 + PORT_CS_1, 1); 1247 if (ret) 1248 return ret; 1249 1250 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1, 1251 PORT_CS_1_PND, 0, 500); 1252 if (ret) 1253 return ret; 1254 1255 ret = tb_port_read(port, &val, TB_CFG_PORT, 1256 port->cap_usb4 + PORT_CS_1, 1); 1257 if (ret) 1258 return ret; 1259 1260 if (val & PORT_CS_1_NR) 1261 return -ENODEV; 1262 if (val & PORT_CS_1_RC) 1263 return -EIO; 1264 1265 return 0; 1266 } 1267 1268 static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target, 1269 u8 index, enum usb4_sb_opcode opcode, int timeout_msec) 1270 { 1271 ktime_t timeout; 1272 u32 val; 1273 int ret; 1274 1275 val = opcode; 1276 ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val, 1277 sizeof(val)); 1278 if (ret) 1279 return ret; 1280 1281 timeout = ktime_add_ms(ktime_get(), timeout_msec); 1282 1283 do { 1284 /* Check results */ 1285 ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE, 1286 &val, sizeof(val)); 1287 if (ret) 1288 return ret; 1289 1290 switch (val) { 1291 case 0: 1292 return 0; 1293 1294 case USB4_SB_OPCODE_ERR: 1295 return -EAGAIN; 1296 1297 case USB4_SB_OPCODE_ONS: 1298 return -EOPNOTSUPP; 1299 1300 default: 1301 if (val != opcode) 1302 return -EIO; 1303 break; 1304 } 1305 } while (ktime_before(ktime_get(), timeout)); 1306 1307 return -ETIMEDOUT; 1308 } 1309 1310 static int usb4_port_set_router_offline(struct tb_port *port, bool offline) 1311 { 1312 u32 val = !offline; 1313 int ret; 1314 1315 ret = usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0, 1316 USB4_SB_METADATA, &val, sizeof(val)); 1317 if (ret) 1318 return ret; 1319 1320 val = USB4_SB_OPCODE_ROUTER_OFFLINE; 1321 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0, 1322 USB4_SB_OPCODE, &val, sizeof(val)); 1323 } 1324 1325 /** 1326 * usb4_port_router_offline() - Put the USB4 port to offline mode 1327 * @port: USB4 port 1328 * 1329 * This function puts the USB4 port into offline mode. In this mode the 1330 * port does not react on hotplug events anymore. This needs to be 1331 * called before retimer access is done when the USB4 links is not up. 1332 * 1333 * Returns %0 in case of success and negative errno if there was an 1334 * error. 1335 */ 1336 int usb4_port_router_offline(struct tb_port *port) 1337 { 1338 return usb4_port_set_router_offline(port, true); 1339 } 1340 1341 /** 1342 * usb4_port_router_online() - Put the USB4 port back to online 1343 * @port: USB4 port 1344 * 1345 * Makes the USB4 port functional again. 1346 */ 1347 int usb4_port_router_online(struct tb_port *port) 1348 { 1349 return usb4_port_set_router_offline(port, false); 1350 } 1351 1352 /** 1353 * usb4_port_enumerate_retimers() - Send RT broadcast transaction 1354 * @port: USB4 port 1355 * 1356 * This forces the USB4 port to send broadcast RT transaction which 1357 * makes the retimers on the link to assign index to themselves. Returns 1358 * %0 in case of success and negative errno if there was an error. 1359 */ 1360 int usb4_port_enumerate_retimers(struct tb_port *port) 1361 { 1362 u32 val; 1363 1364 val = USB4_SB_OPCODE_ENUMERATE_RETIMERS; 1365 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0, 1366 USB4_SB_OPCODE, &val, sizeof(val)); 1367 } 1368 1369 /** 1370 * usb4_port_clx_supported() - Check if CLx is supported by the link 1371 * @port: Port to check for CLx support for 1372 * 1373 * PORT_CS_18_CPS bit reflects if the link supports CLx including 1374 * active cables (if connected on the link). 1375 */ 1376 bool usb4_port_clx_supported(struct tb_port *port) 1377 { 1378 int ret; 1379 u32 val; 1380 1381 ret = tb_port_read(port, &val, TB_CFG_PORT, 1382 port->cap_usb4 + PORT_CS_18, 1); 1383 if (ret) 1384 return false; 1385 1386 return !!(val & PORT_CS_18_CPS); 1387 } 1388 1389 static inline int usb4_port_retimer_op(struct tb_port *port, u8 index, 1390 enum usb4_sb_opcode opcode, 1391 int timeout_msec) 1392 { 1393 return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode, 1394 timeout_msec); 1395 } 1396 1397 /** 1398 * usb4_port_retimer_set_inbound_sbtx() - Enable sideband channel transactions 1399 * @port: USB4 port 1400 * @index: Retimer index 1401 * 1402 * Enables sideband channel transations on SBTX. Can be used when USB4 1403 * link does not go up, for example if there is no device connected. 1404 */ 1405 int usb4_port_retimer_set_inbound_sbtx(struct tb_port *port, u8 index) 1406 { 1407 int ret; 1408 1409 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX, 1410 500); 1411 1412 if (ret != -ENODEV) 1413 return ret; 1414 1415 /* 1416 * Per the USB4 retimer spec, the retimer is not required to 1417 * send an RT (Retimer Transaction) response for the first 1418 * SET_INBOUND_SBTX command 1419 */ 1420 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_SET_INBOUND_SBTX, 1421 500); 1422 } 1423 1424 /** 1425 * usb4_port_retimer_read() - Read from retimer sideband registers 1426 * @port: USB4 port 1427 * @index: Retimer index 1428 * @reg: Sideband register to read 1429 * @buf: Data from @reg is stored here 1430 * @size: Number of bytes to read 1431 * 1432 * Function reads retimer sideband registers starting from @reg. The 1433 * retimer is connected to @port at @index. Returns %0 in case of 1434 * success, and read data is copied to @buf. If there is no retimer 1435 * present at given @index returns %-ENODEV. In any other failure 1436 * returns negative errno. 1437 */ 1438 int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf, 1439 u8 size) 1440 { 1441 return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index, reg, buf, 1442 size); 1443 } 1444 1445 /** 1446 * usb4_port_retimer_write() - Write to retimer sideband registers 1447 * @port: USB4 port 1448 * @index: Retimer index 1449 * @reg: Sideband register to write 1450 * @buf: Data that is written starting from @reg 1451 * @size: Number of bytes to write 1452 * 1453 * Writes retimer sideband registers starting from @reg. The retimer is 1454 * connected to @port at @index. Returns %0 in case of success. If there 1455 * is no retimer present at given @index returns %-ENODEV. In any other 1456 * failure returns negative errno. 1457 */ 1458 int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg, 1459 const void *buf, u8 size) 1460 { 1461 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, reg, buf, 1462 size); 1463 } 1464 1465 /** 1466 * usb4_port_retimer_is_last() - Is the retimer last on-board retimer 1467 * @port: USB4 port 1468 * @index: Retimer index 1469 * 1470 * If the retimer at @index is last one (connected directly to the 1471 * Type-C port) this function returns %1. If it is not returns %0. If 1472 * the retimer is not present returns %-ENODEV. Otherwise returns 1473 * negative errno. 1474 */ 1475 int usb4_port_retimer_is_last(struct tb_port *port, u8 index) 1476 { 1477 u32 metadata; 1478 int ret; 1479 1480 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER, 1481 500); 1482 if (ret) 1483 return ret; 1484 1485 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata, 1486 sizeof(metadata)); 1487 return ret ? ret : metadata & 1; 1488 } 1489 1490 /** 1491 * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size 1492 * @port: USB4 port 1493 * @index: Retimer index 1494 * 1495 * Reads NVM sector size (in bytes) of a retimer at @index. This 1496 * operation can be used to determine whether the retimer supports NVM 1497 * upgrade for example. Returns sector size in bytes or negative errno 1498 * in case of error. Specifically returns %-ENODEV if there is no 1499 * retimer at @index. 1500 */ 1501 int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index) 1502 { 1503 u32 metadata; 1504 int ret; 1505 1506 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE, 1507 500); 1508 if (ret) 1509 return ret; 1510 1511 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata, 1512 sizeof(metadata)); 1513 return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK; 1514 } 1515 1516 /** 1517 * usb4_port_retimer_nvm_set_offset() - Set NVM write offset 1518 * @port: USB4 port 1519 * @index: Retimer index 1520 * @address: Start offset 1521 * 1522 * Exlicitly sets NVM write offset. Normally when writing to NVM this is 1523 * done automatically by usb4_port_retimer_nvm_write(). 1524 * 1525 * Returns %0 in success and negative errno if there was a failure. 1526 */ 1527 int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index, 1528 unsigned int address) 1529 { 1530 u32 metadata, dwaddress; 1531 int ret; 1532 1533 dwaddress = address / 4; 1534 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) & 1535 USB4_NVM_SET_OFFSET_MASK; 1536 1537 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata, 1538 sizeof(metadata)); 1539 if (ret) 1540 return ret; 1541 1542 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET, 1543 500); 1544 } 1545 1546 struct retimer_info { 1547 struct tb_port *port; 1548 u8 index; 1549 }; 1550 1551 static int usb4_port_retimer_nvm_write_next_block(void *data, 1552 unsigned int dwaddress, const void *buf, size_t dwords) 1553 1554 { 1555 const struct retimer_info *info = data; 1556 struct tb_port *port = info->port; 1557 u8 index = info->index; 1558 int ret; 1559 1560 ret = usb4_port_retimer_write(port, index, USB4_SB_DATA, 1561 buf, dwords * 4); 1562 if (ret) 1563 return ret; 1564 1565 return usb4_port_retimer_op(port, index, 1566 USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000); 1567 } 1568 1569 /** 1570 * usb4_port_retimer_nvm_write() - Write to retimer NVM 1571 * @port: USB4 port 1572 * @index: Retimer index 1573 * @address: Byte address where to start the write 1574 * @buf: Data to write 1575 * @size: Size in bytes how much to write 1576 * 1577 * Writes @size bytes from @buf to the retimer NVM. Used for NVM 1578 * upgrade. Returns %0 if the data was written successfully and negative 1579 * errno in case of failure. Specifically returns %-ENODEV if there is 1580 * no retimer at @index. 1581 */ 1582 int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address, 1583 const void *buf, size_t size) 1584 { 1585 struct retimer_info info = { .port = port, .index = index }; 1586 int ret; 1587 1588 ret = usb4_port_retimer_nvm_set_offset(port, index, address); 1589 if (ret) 1590 return ret; 1591 1592 return tb_nvm_write_data(address, buf, size, USB4_DATA_RETRIES, 1593 usb4_port_retimer_nvm_write_next_block, &info); 1594 } 1595 1596 /** 1597 * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade 1598 * @port: USB4 port 1599 * @index: Retimer index 1600 * 1601 * After the new NVM image has been written via usb4_port_retimer_nvm_write() 1602 * this function can be used to trigger the NVM upgrade process. If 1603 * successful the retimer restarts with the new NVM and may not have the 1604 * index set so one needs to call usb4_port_enumerate_retimers() to 1605 * force index to be assigned. 1606 */ 1607 int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index) 1608 { 1609 u32 val; 1610 1611 /* 1612 * We need to use the raw operation here because once the 1613 * authentication completes the retimer index is not set anymore 1614 * so we do not get back the status now. 1615 */ 1616 val = USB4_SB_OPCODE_NVM_AUTH_WRITE; 1617 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, 1618 USB4_SB_OPCODE, &val, sizeof(val)); 1619 } 1620 1621 /** 1622 * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade 1623 * @port: USB4 port 1624 * @index: Retimer index 1625 * @status: Raw status code read from metadata 1626 * 1627 * This can be called after usb4_port_retimer_nvm_authenticate() and 1628 * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade. 1629 * 1630 * Returns %0 if the authentication status was successfully read. The 1631 * completion metadata (the result) is then stored into @status. If 1632 * reading the status fails, returns negative errno. 1633 */ 1634 int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index, 1635 u32 *status) 1636 { 1637 u32 metadata, val; 1638 int ret; 1639 1640 ret = usb4_port_retimer_read(port, index, USB4_SB_OPCODE, &val, 1641 sizeof(val)); 1642 if (ret) 1643 return ret; 1644 1645 switch (val) { 1646 case 0: 1647 *status = 0; 1648 return 0; 1649 1650 case USB4_SB_OPCODE_ERR: 1651 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, 1652 &metadata, sizeof(metadata)); 1653 if (ret) 1654 return ret; 1655 1656 *status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK; 1657 return 0; 1658 1659 case USB4_SB_OPCODE_ONS: 1660 return -EOPNOTSUPP; 1661 1662 default: 1663 return -EIO; 1664 } 1665 } 1666 1667 static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress, 1668 void *buf, size_t dwords) 1669 { 1670 const struct retimer_info *info = data; 1671 struct tb_port *port = info->port; 1672 u8 index = info->index; 1673 u32 metadata; 1674 int ret; 1675 1676 metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT; 1677 if (dwords < NVM_DATA_DWORDS) 1678 metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT; 1679 1680 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata, 1681 sizeof(metadata)); 1682 if (ret) 1683 return ret; 1684 1685 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500); 1686 if (ret) 1687 return ret; 1688 1689 return usb4_port_retimer_read(port, index, USB4_SB_DATA, buf, 1690 dwords * 4); 1691 } 1692 1693 /** 1694 * usb4_port_retimer_nvm_read() - Read contents of retimer NVM 1695 * @port: USB4 port 1696 * @index: Retimer index 1697 * @address: NVM address (in bytes) to start reading 1698 * @buf: Data read from NVM is stored here 1699 * @size: Number of bytes to read 1700 * 1701 * Reads retimer NVM and copies the contents to @buf. Returns %0 if the 1702 * read was successful and negative errno in case of failure. 1703 * Specifically returns %-ENODEV if there is no retimer at @index. 1704 */ 1705 int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index, 1706 unsigned int address, void *buf, size_t size) 1707 { 1708 struct retimer_info info = { .port = port, .index = index }; 1709 1710 return tb_nvm_read_data(address, buf, size, USB4_DATA_RETRIES, 1711 usb4_port_retimer_nvm_read_block, &info); 1712 } 1713 1714 /** 1715 * usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate 1716 * @port: USB3 adapter port 1717 * 1718 * Return maximum supported link rate of a USB3 adapter in Mb/s. 1719 * Negative errno in case of error. 1720 */ 1721 int usb4_usb3_port_max_link_rate(struct tb_port *port) 1722 { 1723 int ret, lr; 1724 u32 val; 1725 1726 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port)) 1727 return -EINVAL; 1728 1729 ret = tb_port_read(port, &val, TB_CFG_PORT, 1730 port->cap_adap + ADP_USB3_CS_4, 1); 1731 if (ret) 1732 return ret; 1733 1734 lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT; 1735 return lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000; 1736 } 1737 1738 /** 1739 * usb4_usb3_port_actual_link_rate() - Established USB3 link rate 1740 * @port: USB3 adapter port 1741 * 1742 * Return actual established link rate of a USB3 adapter in Mb/s. If the 1743 * link is not up returns %0 and negative errno in case of failure. 1744 */ 1745 int usb4_usb3_port_actual_link_rate(struct tb_port *port) 1746 { 1747 int ret, lr; 1748 u32 val; 1749 1750 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port)) 1751 return -EINVAL; 1752 1753 ret = tb_port_read(port, &val, TB_CFG_PORT, 1754 port->cap_adap + ADP_USB3_CS_4, 1); 1755 if (ret) 1756 return ret; 1757 1758 if (!(val & ADP_USB3_CS_4_ULV)) 1759 return 0; 1760 1761 lr = val & ADP_USB3_CS_4_ALR_MASK; 1762 return lr == ADP_USB3_CS_4_ALR_20G ? 20000 : 10000; 1763 } 1764 1765 static int usb4_usb3_port_cm_request(struct tb_port *port, bool request) 1766 { 1767 int ret; 1768 u32 val; 1769 1770 if (!tb_port_is_usb3_down(port)) 1771 return -EINVAL; 1772 if (tb_route(port->sw)) 1773 return -EINVAL; 1774 1775 ret = tb_port_read(port, &val, TB_CFG_PORT, 1776 port->cap_adap + ADP_USB3_CS_2, 1); 1777 if (ret) 1778 return ret; 1779 1780 if (request) 1781 val |= ADP_USB3_CS_2_CMR; 1782 else 1783 val &= ~ADP_USB3_CS_2_CMR; 1784 1785 ret = tb_port_write(port, &val, TB_CFG_PORT, 1786 port->cap_adap + ADP_USB3_CS_2, 1); 1787 if (ret) 1788 return ret; 1789 1790 /* 1791 * We can use val here directly as the CMR bit is in the same place 1792 * as HCA. Just mask out others. 1793 */ 1794 val &= ADP_USB3_CS_2_CMR; 1795 return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1, 1796 ADP_USB3_CS_1_HCA, val, 1500); 1797 } 1798 1799 static inline int usb4_usb3_port_set_cm_request(struct tb_port *port) 1800 { 1801 return usb4_usb3_port_cm_request(port, true); 1802 } 1803 1804 static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port) 1805 { 1806 return usb4_usb3_port_cm_request(port, false); 1807 } 1808 1809 static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale) 1810 { 1811 unsigned long uframes; 1812 1813 uframes = bw * 512UL << scale; 1814 return DIV_ROUND_CLOSEST(uframes * 8000, 1000 * 1000); 1815 } 1816 1817 static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale) 1818 { 1819 unsigned long uframes; 1820 1821 /* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */ 1822 uframes = ((unsigned long)mbps * 1000 * 1000) / 8000; 1823 return DIV_ROUND_UP(uframes, 512UL << scale); 1824 } 1825 1826 static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port, 1827 int *upstream_bw, 1828 int *downstream_bw) 1829 { 1830 u32 val, bw, scale; 1831 int ret; 1832 1833 ret = tb_port_read(port, &val, TB_CFG_PORT, 1834 port->cap_adap + ADP_USB3_CS_2, 1); 1835 if (ret) 1836 return ret; 1837 1838 ret = tb_port_read(port, &scale, TB_CFG_PORT, 1839 port->cap_adap + ADP_USB3_CS_3, 1); 1840 if (ret) 1841 return ret; 1842 1843 scale &= ADP_USB3_CS_3_SCALE_MASK; 1844 1845 bw = val & ADP_USB3_CS_2_AUBW_MASK; 1846 *upstream_bw = usb3_bw_to_mbps(bw, scale); 1847 1848 bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT; 1849 *downstream_bw = usb3_bw_to_mbps(bw, scale); 1850 1851 return 0; 1852 } 1853 1854 /** 1855 * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3 1856 * @port: USB3 adapter port 1857 * @upstream_bw: Allocated upstream bandwidth is stored here 1858 * @downstream_bw: Allocated downstream bandwidth is stored here 1859 * 1860 * Stores currently allocated USB3 bandwidth into @upstream_bw and 1861 * @downstream_bw in Mb/s. Returns %0 in case of success and negative 1862 * errno in failure. 1863 */ 1864 int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw, 1865 int *downstream_bw) 1866 { 1867 int ret; 1868 1869 ret = usb4_usb3_port_set_cm_request(port); 1870 if (ret) 1871 return ret; 1872 1873 ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw, 1874 downstream_bw); 1875 usb4_usb3_port_clear_cm_request(port); 1876 1877 return ret; 1878 } 1879 1880 static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port, 1881 int *upstream_bw, 1882 int *downstream_bw) 1883 { 1884 u32 val, bw, scale; 1885 int ret; 1886 1887 ret = tb_port_read(port, &val, TB_CFG_PORT, 1888 port->cap_adap + ADP_USB3_CS_1, 1); 1889 if (ret) 1890 return ret; 1891 1892 ret = tb_port_read(port, &scale, TB_CFG_PORT, 1893 port->cap_adap + ADP_USB3_CS_3, 1); 1894 if (ret) 1895 return ret; 1896 1897 scale &= ADP_USB3_CS_3_SCALE_MASK; 1898 1899 bw = val & ADP_USB3_CS_1_CUBW_MASK; 1900 *upstream_bw = usb3_bw_to_mbps(bw, scale); 1901 1902 bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT; 1903 *downstream_bw = usb3_bw_to_mbps(bw, scale); 1904 1905 return 0; 1906 } 1907 1908 static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port, 1909 int upstream_bw, 1910 int downstream_bw) 1911 { 1912 u32 val, ubw, dbw, scale; 1913 int ret; 1914 1915 /* Read the used scale, hardware default is 0 */ 1916 ret = tb_port_read(port, &scale, TB_CFG_PORT, 1917 port->cap_adap + ADP_USB3_CS_3, 1); 1918 if (ret) 1919 return ret; 1920 1921 scale &= ADP_USB3_CS_3_SCALE_MASK; 1922 ubw = mbps_to_usb3_bw(upstream_bw, scale); 1923 dbw = mbps_to_usb3_bw(downstream_bw, scale); 1924 1925 ret = tb_port_read(port, &val, TB_CFG_PORT, 1926 port->cap_adap + ADP_USB3_CS_2, 1); 1927 if (ret) 1928 return ret; 1929 1930 val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK); 1931 val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT; 1932 val |= ubw; 1933 1934 return tb_port_write(port, &val, TB_CFG_PORT, 1935 port->cap_adap + ADP_USB3_CS_2, 1); 1936 } 1937 1938 /** 1939 * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3 1940 * @port: USB3 adapter port 1941 * @upstream_bw: New upstream bandwidth 1942 * @downstream_bw: New downstream bandwidth 1943 * 1944 * This can be used to set how much bandwidth is allocated for the USB3 1945 * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the 1946 * new values programmed to the USB3 adapter allocation registers. If 1947 * the values are lower than what is currently consumed the allocation 1948 * is set to what is currently consumed instead (consumed bandwidth 1949 * cannot be taken away by CM). The actual new values are returned in 1950 * @upstream_bw and @downstream_bw. 1951 * 1952 * Returns %0 in case of success and negative errno if there was a 1953 * failure. 1954 */ 1955 int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw, 1956 int *downstream_bw) 1957 { 1958 int ret, consumed_up, consumed_down, allocate_up, allocate_down; 1959 1960 ret = usb4_usb3_port_set_cm_request(port); 1961 if (ret) 1962 return ret; 1963 1964 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up, 1965 &consumed_down); 1966 if (ret) 1967 goto err_request; 1968 1969 /* Don't allow it go lower than what is consumed */ 1970 allocate_up = max(*upstream_bw, consumed_up); 1971 allocate_down = max(*downstream_bw, consumed_down); 1972 1973 ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up, 1974 allocate_down); 1975 if (ret) 1976 goto err_request; 1977 1978 *upstream_bw = allocate_up; 1979 *downstream_bw = allocate_down; 1980 1981 err_request: 1982 usb4_usb3_port_clear_cm_request(port); 1983 return ret; 1984 } 1985 1986 /** 1987 * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth 1988 * @port: USB3 adapter port 1989 * @upstream_bw: New allocated upstream bandwidth 1990 * @downstream_bw: New allocated downstream bandwidth 1991 * 1992 * Releases USB3 allocated bandwidth down to what is actually consumed. 1993 * The new bandwidth is returned in @upstream_bw and @downstream_bw. 1994 * 1995 * Returns 0% in success and negative errno in case of failure. 1996 */ 1997 int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw, 1998 int *downstream_bw) 1999 { 2000 int ret, consumed_up, consumed_down; 2001 2002 ret = usb4_usb3_port_set_cm_request(port); 2003 if (ret) 2004 return ret; 2005 2006 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up, 2007 &consumed_down); 2008 if (ret) 2009 goto err_request; 2010 2011 /* 2012 * Always keep 1000 Mb/s to make sure xHCI has at least some 2013 * bandwidth available for isochronous traffic. 2014 */ 2015 if (consumed_up < 1000) 2016 consumed_up = 1000; 2017 if (consumed_down < 1000) 2018 consumed_down = 1000; 2019 2020 ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up, 2021 consumed_down); 2022 if (ret) 2023 goto err_request; 2024 2025 *upstream_bw = consumed_up; 2026 *downstream_bw = consumed_down; 2027 2028 err_request: 2029 usb4_usb3_port_clear_cm_request(port); 2030 return ret; 2031 } 2032