1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * USB4 specific functionality 4 * 5 * Copyright (C) 2019, Intel Corporation 6 * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * Rajmohan Mani <rajmohan.mani@intel.com> 8 */ 9 10 #include <linux/delay.h> 11 #include <linux/ktime.h> 12 13 #include "sb_regs.h" 14 #include "tb.h" 15 16 #define USB4_DATA_DWORDS 16 17 #define USB4_DATA_RETRIES 3 18 19 enum usb4_sb_target { 20 USB4_SB_TARGET_ROUTER, 21 USB4_SB_TARGET_PARTNER, 22 USB4_SB_TARGET_RETIMER, 23 }; 24 25 #define USB4_NVM_READ_OFFSET_MASK GENMASK(23, 2) 26 #define USB4_NVM_READ_OFFSET_SHIFT 2 27 #define USB4_NVM_READ_LENGTH_MASK GENMASK(27, 24) 28 #define USB4_NVM_READ_LENGTH_SHIFT 24 29 30 #define USB4_NVM_SET_OFFSET_MASK USB4_NVM_READ_OFFSET_MASK 31 #define USB4_NVM_SET_OFFSET_SHIFT USB4_NVM_READ_OFFSET_SHIFT 32 33 #define USB4_DROM_ADDRESS_MASK GENMASK(14, 2) 34 #define USB4_DROM_ADDRESS_SHIFT 2 35 #define USB4_DROM_SIZE_MASK GENMASK(19, 15) 36 #define USB4_DROM_SIZE_SHIFT 15 37 38 #define USB4_NVM_SECTOR_SIZE_MASK GENMASK(23, 0) 39 40 typedef int (*read_block_fn)(void *, unsigned int, void *, size_t); 41 typedef int (*write_block_fn)(void *, const void *, size_t); 42 43 static int usb4_switch_wait_for_bit(struct tb_switch *sw, u32 offset, u32 bit, 44 u32 value, int timeout_msec) 45 { 46 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec); 47 48 do { 49 u32 val; 50 int ret; 51 52 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1); 53 if (ret) 54 return ret; 55 56 if ((val & bit) == value) 57 return 0; 58 59 usleep_range(50, 100); 60 } while (ktime_before(ktime_get(), timeout)); 61 62 return -ETIMEDOUT; 63 } 64 65 static int usb4_do_read_data(u16 address, void *buf, size_t size, 66 read_block_fn read_block, void *read_block_data) 67 { 68 unsigned int retries = USB4_DATA_RETRIES; 69 unsigned int offset; 70 71 do { 72 unsigned int dwaddress, dwords; 73 u8 data[USB4_DATA_DWORDS * 4]; 74 size_t nbytes; 75 int ret; 76 77 offset = address & 3; 78 nbytes = min_t(size_t, size + offset, USB4_DATA_DWORDS * 4); 79 80 dwaddress = address / 4; 81 dwords = ALIGN(nbytes, 4) / 4; 82 83 ret = read_block(read_block_data, dwaddress, data, dwords); 84 if (ret) { 85 if (ret != -ENODEV && retries--) 86 continue; 87 return ret; 88 } 89 90 nbytes -= offset; 91 memcpy(buf, data + offset, nbytes); 92 93 size -= nbytes; 94 address += nbytes; 95 buf += nbytes; 96 } while (size > 0); 97 98 return 0; 99 } 100 101 static int usb4_do_write_data(unsigned int address, const void *buf, size_t size, 102 write_block_fn write_next_block, void *write_block_data) 103 { 104 unsigned int retries = USB4_DATA_RETRIES; 105 unsigned int offset; 106 107 offset = address & 3; 108 address = address & ~3; 109 110 do { 111 u32 nbytes = min_t(u32, size, USB4_DATA_DWORDS * 4); 112 u8 data[USB4_DATA_DWORDS * 4]; 113 int ret; 114 115 memcpy(data + offset, buf, nbytes); 116 117 ret = write_next_block(write_block_data, data, nbytes / 4); 118 if (ret) { 119 if (ret == -ETIMEDOUT) { 120 if (retries--) 121 continue; 122 ret = -EIO; 123 } 124 return ret; 125 } 126 127 size -= nbytes; 128 address += nbytes; 129 buf += nbytes; 130 } while (size > 0); 131 132 return 0; 133 } 134 135 static int usb4_native_switch_op(struct tb_switch *sw, u16 opcode, 136 u32 *metadata, u8 *status, 137 const void *tx_data, size_t tx_dwords, 138 void *rx_data, size_t rx_dwords) 139 { 140 u32 val; 141 int ret; 142 143 if (metadata) { 144 ret = tb_sw_write(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1); 145 if (ret) 146 return ret; 147 } 148 if (tx_dwords) { 149 ret = tb_sw_write(sw, tx_data, TB_CFG_SWITCH, ROUTER_CS_9, 150 tx_dwords); 151 if (ret) 152 return ret; 153 } 154 155 val = opcode | ROUTER_CS_26_OV; 156 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); 157 if (ret) 158 return ret; 159 160 ret = usb4_switch_wait_for_bit(sw, ROUTER_CS_26, ROUTER_CS_26_OV, 0, 500); 161 if (ret) 162 return ret; 163 164 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); 165 if (ret) 166 return ret; 167 168 if (val & ROUTER_CS_26_ONS) 169 return -EOPNOTSUPP; 170 171 if (status) 172 *status = (val & ROUTER_CS_26_STATUS_MASK) >> 173 ROUTER_CS_26_STATUS_SHIFT; 174 175 if (metadata) { 176 ret = tb_sw_read(sw, metadata, TB_CFG_SWITCH, ROUTER_CS_25, 1); 177 if (ret) 178 return ret; 179 } 180 if (rx_dwords) { 181 ret = tb_sw_read(sw, rx_data, TB_CFG_SWITCH, ROUTER_CS_9, 182 rx_dwords); 183 if (ret) 184 return ret; 185 } 186 187 return 0; 188 } 189 190 static int __usb4_switch_op(struct tb_switch *sw, u16 opcode, u32 *metadata, 191 u8 *status, const void *tx_data, size_t tx_dwords, 192 void *rx_data, size_t rx_dwords) 193 { 194 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops; 195 196 if (tx_dwords > USB4_DATA_DWORDS || rx_dwords > USB4_DATA_DWORDS) 197 return -EINVAL; 198 199 /* 200 * If the connection manager implementation provides USB4 router 201 * operation proxy callback, call it here instead of running the 202 * operation natively. 203 */ 204 if (cm_ops->usb4_switch_op) { 205 int ret; 206 207 ret = cm_ops->usb4_switch_op(sw, opcode, metadata, status, 208 tx_data, tx_dwords, rx_data, 209 rx_dwords); 210 if (ret != -EOPNOTSUPP) 211 return ret; 212 213 /* 214 * If the proxy was not supported then run the native 215 * router operation instead. 216 */ 217 } 218 219 return usb4_native_switch_op(sw, opcode, metadata, status, tx_data, 220 tx_dwords, rx_data, rx_dwords); 221 } 222 223 static inline int usb4_switch_op(struct tb_switch *sw, u16 opcode, 224 u32 *metadata, u8 *status) 225 { 226 return __usb4_switch_op(sw, opcode, metadata, status, NULL, 0, NULL, 0); 227 } 228 229 static inline int usb4_switch_op_data(struct tb_switch *sw, u16 opcode, 230 u32 *metadata, u8 *status, 231 const void *tx_data, size_t tx_dwords, 232 void *rx_data, size_t rx_dwords) 233 { 234 return __usb4_switch_op(sw, opcode, metadata, status, tx_data, 235 tx_dwords, rx_data, rx_dwords); 236 } 237 238 static void usb4_switch_check_wakes(struct tb_switch *sw) 239 { 240 struct tb_port *port; 241 bool wakeup = false; 242 u32 val; 243 244 if (!device_may_wakeup(&sw->dev)) 245 return; 246 247 if (tb_route(sw)) { 248 if (tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1)) 249 return; 250 251 tb_sw_dbg(sw, "PCIe wake: %s, USB3 wake: %s\n", 252 (val & ROUTER_CS_6_WOPS) ? "yes" : "no", 253 (val & ROUTER_CS_6_WOUS) ? "yes" : "no"); 254 255 wakeup = val & (ROUTER_CS_6_WOPS | ROUTER_CS_6_WOUS); 256 } 257 258 /* Check for any connected downstream ports for USB4 wake */ 259 tb_switch_for_each_port(sw, port) { 260 if (!tb_port_has_remote(port)) 261 continue; 262 263 if (tb_port_read(port, &val, TB_CFG_PORT, 264 port->cap_usb4 + PORT_CS_18, 1)) 265 break; 266 267 tb_port_dbg(port, "USB4 wake: %s\n", 268 (val & PORT_CS_18_WOU4S) ? "yes" : "no"); 269 270 if (val & PORT_CS_18_WOU4S) 271 wakeup = true; 272 } 273 274 if (wakeup) 275 pm_wakeup_event(&sw->dev, 0); 276 } 277 278 static bool link_is_usb4(struct tb_port *port) 279 { 280 u32 val; 281 282 if (!port->cap_usb4) 283 return false; 284 285 if (tb_port_read(port, &val, TB_CFG_PORT, 286 port->cap_usb4 + PORT_CS_18, 1)) 287 return false; 288 289 return !(val & PORT_CS_18_TCM); 290 } 291 292 /** 293 * usb4_switch_setup() - Additional setup for USB4 device 294 * @sw: USB4 router to setup 295 * 296 * USB4 routers need additional settings in order to enable all the 297 * tunneling. This function enables USB and PCIe tunneling if it can be 298 * enabled (e.g the parent switch also supports them). If USB tunneling 299 * is not available for some reason (like that there is Thunderbolt 3 300 * switch upstream) then the internal xHCI controller is enabled 301 * instead. 302 */ 303 int usb4_switch_setup(struct tb_switch *sw) 304 { 305 struct tb_port *downstream_port; 306 struct tb_switch *parent; 307 bool tbt3, xhci; 308 u32 val = 0; 309 int ret; 310 311 usb4_switch_check_wakes(sw); 312 313 if (!tb_route(sw)) 314 return 0; 315 316 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_6, 1); 317 if (ret) 318 return ret; 319 320 parent = tb_switch_parent(sw); 321 downstream_port = tb_port_at(tb_route(sw), parent); 322 sw->link_usb4 = link_is_usb4(downstream_port); 323 tb_sw_dbg(sw, "link: %s\n", sw->link_usb4 ? "USB4" : "TBT3"); 324 325 xhci = val & ROUTER_CS_6_HCI; 326 tbt3 = !(val & ROUTER_CS_6_TNS); 327 328 tb_sw_dbg(sw, "TBT3 support: %s, xHCI: %s\n", 329 tbt3 ? "yes" : "no", xhci ? "yes" : "no"); 330 331 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 332 if (ret) 333 return ret; 334 335 if (tb_acpi_may_tunnel_usb3() && sw->link_usb4 && 336 tb_switch_find_port(parent, TB_TYPE_USB3_DOWN)) { 337 val |= ROUTER_CS_5_UTO; 338 xhci = false; 339 } 340 341 /* 342 * Only enable PCIe tunneling if the parent router supports it 343 * and it is not disabled. 344 */ 345 if (tb_acpi_may_tunnel_pcie() && 346 tb_switch_find_port(parent, TB_TYPE_PCIE_DOWN)) { 347 val |= ROUTER_CS_5_PTO; 348 /* 349 * xHCI can be enabled if PCIe tunneling is supported 350 * and the parent does not have any USB3 dowstream 351 * adapters (so we cannot do USB 3.x tunneling). 352 */ 353 if (xhci) 354 val |= ROUTER_CS_5_HCO; 355 } 356 357 /* TBT3 supported by the CM */ 358 val |= ROUTER_CS_5_C3S; 359 /* Tunneling configuration is ready now */ 360 val |= ROUTER_CS_5_CV; 361 362 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 363 if (ret) 364 return ret; 365 366 return usb4_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_CR, 367 ROUTER_CS_6_CR, 50); 368 } 369 370 /** 371 * usb4_switch_read_uid() - Read UID from USB4 router 372 * @sw: USB4 router 373 * @uid: UID is stored here 374 * 375 * Reads 64-bit UID from USB4 router config space. 376 */ 377 int usb4_switch_read_uid(struct tb_switch *sw, u64 *uid) 378 { 379 return tb_sw_read(sw, uid, TB_CFG_SWITCH, ROUTER_CS_7, 2); 380 } 381 382 static int usb4_switch_drom_read_block(void *data, 383 unsigned int dwaddress, void *buf, 384 size_t dwords) 385 { 386 struct tb_switch *sw = data; 387 u8 status = 0; 388 u32 metadata; 389 int ret; 390 391 metadata = (dwords << USB4_DROM_SIZE_SHIFT) & USB4_DROM_SIZE_MASK; 392 metadata |= (dwaddress << USB4_DROM_ADDRESS_SHIFT) & 393 USB4_DROM_ADDRESS_MASK; 394 395 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_DROM_READ, &metadata, 396 &status, NULL, 0, buf, dwords); 397 if (ret) 398 return ret; 399 400 return status ? -EIO : 0; 401 } 402 403 /** 404 * usb4_switch_drom_read() - Read arbitrary bytes from USB4 router DROM 405 * @sw: USB4 router 406 * @address: Byte address inside DROM to start reading 407 * @buf: Buffer where the DROM content is stored 408 * @size: Number of bytes to read from DROM 409 * 410 * Uses USB4 router operations to read router DROM. For devices this 411 * should always work but for hosts it may return %-EOPNOTSUPP in which 412 * case the host router does not have DROM. 413 */ 414 int usb4_switch_drom_read(struct tb_switch *sw, unsigned int address, void *buf, 415 size_t size) 416 { 417 return usb4_do_read_data(address, buf, size, 418 usb4_switch_drom_read_block, sw); 419 } 420 421 /** 422 * usb4_switch_lane_bonding_possible() - Are conditions met for lane bonding 423 * @sw: USB4 router 424 * 425 * Checks whether conditions are met so that lane bonding can be 426 * established with the upstream router. Call only for device routers. 427 */ 428 bool usb4_switch_lane_bonding_possible(struct tb_switch *sw) 429 { 430 struct tb_port *up; 431 int ret; 432 u32 val; 433 434 up = tb_upstream_port(sw); 435 ret = tb_port_read(up, &val, TB_CFG_PORT, up->cap_usb4 + PORT_CS_18, 1); 436 if (ret) 437 return false; 438 439 return !!(val & PORT_CS_18_BE); 440 } 441 442 /** 443 * usb4_switch_set_wake() - Enabled/disable wake 444 * @sw: USB4 router 445 * @flags: Wakeup flags (%0 to disable) 446 * 447 * Enables/disables router to wake up from sleep. 448 */ 449 int usb4_switch_set_wake(struct tb_switch *sw, unsigned int flags) 450 { 451 struct tb_port *port; 452 u64 route = tb_route(sw); 453 u32 val; 454 int ret; 455 456 /* 457 * Enable wakes coming from all USB4 downstream ports (from 458 * child routers). For device routers do this also for the 459 * upstream USB4 port. 460 */ 461 tb_switch_for_each_port(sw, port) { 462 if (!tb_port_is_null(port)) 463 continue; 464 if (!route && tb_is_upstream_port(port)) 465 continue; 466 if (!port->cap_usb4) 467 continue; 468 469 ret = tb_port_read(port, &val, TB_CFG_PORT, 470 port->cap_usb4 + PORT_CS_19, 1); 471 if (ret) 472 return ret; 473 474 val &= ~(PORT_CS_19_WOC | PORT_CS_19_WOD | PORT_CS_19_WOU4); 475 476 if (flags & TB_WAKE_ON_CONNECT) 477 val |= PORT_CS_19_WOC; 478 if (flags & TB_WAKE_ON_DISCONNECT) 479 val |= PORT_CS_19_WOD; 480 if (flags & TB_WAKE_ON_USB4) 481 val |= PORT_CS_19_WOU4; 482 483 ret = tb_port_write(port, &val, TB_CFG_PORT, 484 port->cap_usb4 + PORT_CS_19, 1); 485 if (ret) 486 return ret; 487 } 488 489 /* 490 * Enable wakes from PCIe and USB 3.x on this router. Only 491 * needed for device routers. 492 */ 493 if (route) { 494 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 495 if (ret) 496 return ret; 497 498 val &= ~(ROUTER_CS_5_WOP | ROUTER_CS_5_WOU); 499 if (flags & TB_WAKE_ON_USB3) 500 val |= ROUTER_CS_5_WOU; 501 if (flags & TB_WAKE_ON_PCIE) 502 val |= ROUTER_CS_5_WOP; 503 504 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 505 if (ret) 506 return ret; 507 } 508 509 return 0; 510 } 511 512 /** 513 * usb4_switch_set_sleep() - Prepare the router to enter sleep 514 * @sw: USB4 router 515 * 516 * Sets sleep bit for the router. Returns when the router sleep ready 517 * bit has been asserted. 518 */ 519 int usb4_switch_set_sleep(struct tb_switch *sw) 520 { 521 int ret; 522 u32 val; 523 524 /* Set sleep bit and wait for sleep ready to be asserted */ 525 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 526 if (ret) 527 return ret; 528 529 val |= ROUTER_CS_5_SLP; 530 531 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, ROUTER_CS_5, 1); 532 if (ret) 533 return ret; 534 535 return usb4_switch_wait_for_bit(sw, ROUTER_CS_6, ROUTER_CS_6_SLPR, 536 ROUTER_CS_6_SLPR, 500); 537 } 538 539 /** 540 * usb4_switch_nvm_sector_size() - Return router NVM sector size 541 * @sw: USB4 router 542 * 543 * If the router supports NVM operations this function returns the NVM 544 * sector size in bytes. If NVM operations are not supported returns 545 * %-EOPNOTSUPP. 546 */ 547 int usb4_switch_nvm_sector_size(struct tb_switch *sw) 548 { 549 u32 metadata; 550 u8 status; 551 int ret; 552 553 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SECTOR_SIZE, &metadata, 554 &status); 555 if (ret) 556 return ret; 557 558 if (status) 559 return status == 0x2 ? -EOPNOTSUPP : -EIO; 560 561 return metadata & USB4_NVM_SECTOR_SIZE_MASK; 562 } 563 564 static int usb4_switch_nvm_read_block(void *data, 565 unsigned int dwaddress, void *buf, size_t dwords) 566 { 567 struct tb_switch *sw = data; 568 u8 status = 0; 569 u32 metadata; 570 int ret; 571 572 metadata = (dwords << USB4_NVM_READ_LENGTH_SHIFT) & 573 USB4_NVM_READ_LENGTH_MASK; 574 metadata |= (dwaddress << USB4_NVM_READ_OFFSET_SHIFT) & 575 USB4_NVM_READ_OFFSET_MASK; 576 577 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_READ, &metadata, 578 &status, NULL, 0, buf, dwords); 579 if (ret) 580 return ret; 581 582 return status ? -EIO : 0; 583 } 584 585 /** 586 * usb4_switch_nvm_read() - Read arbitrary bytes from router NVM 587 * @sw: USB4 router 588 * @address: Starting address in bytes 589 * @buf: Read data is placed here 590 * @size: How many bytes to read 591 * 592 * Reads NVM contents of the router. If NVM is not supported returns 593 * %-EOPNOTSUPP. 594 */ 595 int usb4_switch_nvm_read(struct tb_switch *sw, unsigned int address, void *buf, 596 size_t size) 597 { 598 return usb4_do_read_data(address, buf, size, 599 usb4_switch_nvm_read_block, sw); 600 } 601 602 static int usb4_switch_nvm_set_offset(struct tb_switch *sw, 603 unsigned int address) 604 { 605 u32 metadata, dwaddress; 606 u8 status = 0; 607 int ret; 608 609 dwaddress = address / 4; 610 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) & 611 USB4_NVM_SET_OFFSET_MASK; 612 613 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_SET_OFFSET, &metadata, 614 &status); 615 if (ret) 616 return ret; 617 618 return status ? -EIO : 0; 619 } 620 621 static int usb4_switch_nvm_write_next_block(void *data, const void *buf, 622 size_t dwords) 623 { 624 struct tb_switch *sw = data; 625 u8 status; 626 int ret; 627 628 ret = usb4_switch_op_data(sw, USB4_SWITCH_OP_NVM_WRITE, NULL, &status, 629 buf, dwords, NULL, 0); 630 if (ret) 631 return ret; 632 633 return status ? -EIO : 0; 634 } 635 636 /** 637 * usb4_switch_nvm_write() - Write to the router NVM 638 * @sw: USB4 router 639 * @address: Start address where to write in bytes 640 * @buf: Pointer to the data to write 641 * @size: Size of @buf in bytes 642 * 643 * Writes @buf to the router NVM using USB4 router operations. If NVM 644 * write is not supported returns %-EOPNOTSUPP. 645 */ 646 int usb4_switch_nvm_write(struct tb_switch *sw, unsigned int address, 647 const void *buf, size_t size) 648 { 649 int ret; 650 651 ret = usb4_switch_nvm_set_offset(sw, address); 652 if (ret) 653 return ret; 654 655 return usb4_do_write_data(address, buf, size, 656 usb4_switch_nvm_write_next_block, sw); 657 } 658 659 /** 660 * usb4_switch_nvm_authenticate() - Authenticate new NVM 661 * @sw: USB4 router 662 * 663 * After the new NVM has been written via usb4_switch_nvm_write(), this 664 * function triggers NVM authentication process. The router gets power 665 * cycled and if the authentication is successful the new NVM starts 666 * running. In case of failure returns negative errno. 667 * 668 * The caller should call usb4_switch_nvm_authenticate_status() to read 669 * the status of the authentication after power cycle. It should be the 670 * first router operation to avoid the status being lost. 671 */ 672 int usb4_switch_nvm_authenticate(struct tb_switch *sw) 673 { 674 int ret; 675 676 ret = usb4_switch_op(sw, USB4_SWITCH_OP_NVM_AUTH, NULL, NULL); 677 switch (ret) { 678 /* 679 * The router is power cycled once NVM_AUTH is started so it is 680 * expected to get any of the following errors back. 681 */ 682 case -EACCES: 683 case -ENOTCONN: 684 case -ETIMEDOUT: 685 return 0; 686 687 default: 688 return ret; 689 } 690 } 691 692 /** 693 * usb4_switch_nvm_authenticate_status() - Read status of last NVM authenticate 694 * @sw: USB4 router 695 * @status: Status code of the operation 696 * 697 * The function checks if there is status available from the last NVM 698 * authenticate router operation. If there is status then %0 is returned 699 * and the status code is placed in @status. Returns negative errno in case 700 * of failure. 701 * 702 * Must be called before any other router operation. 703 */ 704 int usb4_switch_nvm_authenticate_status(struct tb_switch *sw, u32 *status) 705 { 706 const struct tb_cm_ops *cm_ops = sw->tb->cm_ops; 707 u16 opcode; 708 u32 val; 709 int ret; 710 711 if (cm_ops->usb4_switch_nvm_authenticate_status) { 712 ret = cm_ops->usb4_switch_nvm_authenticate_status(sw, status); 713 if (ret != -EOPNOTSUPP) 714 return ret; 715 } 716 717 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, ROUTER_CS_26, 1); 718 if (ret) 719 return ret; 720 721 /* Check that the opcode is correct */ 722 opcode = val & ROUTER_CS_26_OPCODE_MASK; 723 if (opcode == USB4_SWITCH_OP_NVM_AUTH) { 724 if (val & ROUTER_CS_26_OV) 725 return -EBUSY; 726 if (val & ROUTER_CS_26_ONS) 727 return -EOPNOTSUPP; 728 729 *status = (val & ROUTER_CS_26_STATUS_MASK) >> 730 ROUTER_CS_26_STATUS_SHIFT; 731 } else { 732 *status = 0; 733 } 734 735 return 0; 736 } 737 738 /** 739 * usb4_switch_query_dp_resource() - Query availability of DP IN resource 740 * @sw: USB4 router 741 * @in: DP IN adapter 742 * 743 * For DP tunneling this function can be used to query availability of 744 * DP IN resource. Returns true if the resource is available for DP 745 * tunneling, false otherwise. 746 */ 747 bool usb4_switch_query_dp_resource(struct tb_switch *sw, struct tb_port *in) 748 { 749 u32 metadata = in->port; 750 u8 status; 751 int ret; 752 753 ret = usb4_switch_op(sw, USB4_SWITCH_OP_QUERY_DP_RESOURCE, &metadata, 754 &status); 755 /* 756 * If DP resource allocation is not supported assume it is 757 * always available. 758 */ 759 if (ret == -EOPNOTSUPP) 760 return true; 761 else if (ret) 762 return false; 763 764 return !status; 765 } 766 767 /** 768 * usb4_switch_alloc_dp_resource() - Allocate DP IN resource 769 * @sw: USB4 router 770 * @in: DP IN adapter 771 * 772 * Allocates DP IN resource for DP tunneling using USB4 router 773 * operations. If the resource was allocated returns %0. Otherwise 774 * returns negative errno, in particular %-EBUSY if the resource is 775 * already allocated. 776 */ 777 int usb4_switch_alloc_dp_resource(struct tb_switch *sw, struct tb_port *in) 778 { 779 u32 metadata = in->port; 780 u8 status; 781 int ret; 782 783 ret = usb4_switch_op(sw, USB4_SWITCH_OP_ALLOC_DP_RESOURCE, &metadata, 784 &status); 785 if (ret == -EOPNOTSUPP) 786 return 0; 787 else if (ret) 788 return ret; 789 790 return status ? -EBUSY : 0; 791 } 792 793 /** 794 * usb4_switch_dealloc_dp_resource() - Releases allocated DP IN resource 795 * @sw: USB4 router 796 * @in: DP IN adapter 797 * 798 * Releases the previously allocated DP IN resource. 799 */ 800 int usb4_switch_dealloc_dp_resource(struct tb_switch *sw, struct tb_port *in) 801 { 802 u32 metadata = in->port; 803 u8 status; 804 int ret; 805 806 ret = usb4_switch_op(sw, USB4_SWITCH_OP_DEALLOC_DP_RESOURCE, &metadata, 807 &status); 808 if (ret == -EOPNOTSUPP) 809 return 0; 810 else if (ret) 811 return ret; 812 813 return status ? -EIO : 0; 814 } 815 816 static int usb4_port_idx(const struct tb_switch *sw, const struct tb_port *port) 817 { 818 struct tb_port *p; 819 int usb4_idx = 0; 820 821 /* Assume port is primary */ 822 tb_switch_for_each_port(sw, p) { 823 if (!tb_port_is_null(p)) 824 continue; 825 if (tb_is_upstream_port(p)) 826 continue; 827 if (!p->link_nr) { 828 if (p == port) 829 break; 830 usb4_idx++; 831 } 832 } 833 834 return usb4_idx; 835 } 836 837 /** 838 * usb4_switch_map_pcie_down() - Map USB4 port to a PCIe downstream adapter 839 * @sw: USB4 router 840 * @port: USB4 port 841 * 842 * USB4 routers have direct mapping between USB4 ports and PCIe 843 * downstream adapters where the PCIe topology is extended. This 844 * function returns the corresponding downstream PCIe adapter or %NULL 845 * if no such mapping was possible. 846 */ 847 struct tb_port *usb4_switch_map_pcie_down(struct tb_switch *sw, 848 const struct tb_port *port) 849 { 850 int usb4_idx = usb4_port_idx(sw, port); 851 struct tb_port *p; 852 int pcie_idx = 0; 853 854 /* Find PCIe down port matching usb4_port */ 855 tb_switch_for_each_port(sw, p) { 856 if (!tb_port_is_pcie_down(p)) 857 continue; 858 859 if (pcie_idx == usb4_idx) 860 return p; 861 862 pcie_idx++; 863 } 864 865 return NULL; 866 } 867 868 /** 869 * usb4_switch_map_usb3_down() - Map USB4 port to a USB3 downstream adapter 870 * @sw: USB4 router 871 * @port: USB4 port 872 * 873 * USB4 routers have direct mapping between USB4 ports and USB 3.x 874 * downstream adapters where the USB 3.x topology is extended. This 875 * function returns the corresponding downstream USB 3.x adapter or 876 * %NULL if no such mapping was possible. 877 */ 878 struct tb_port *usb4_switch_map_usb3_down(struct tb_switch *sw, 879 const struct tb_port *port) 880 { 881 int usb4_idx = usb4_port_idx(sw, port); 882 struct tb_port *p; 883 int usb_idx = 0; 884 885 /* Find USB3 down port matching usb4_port */ 886 tb_switch_for_each_port(sw, p) { 887 if (!tb_port_is_usb3_down(p)) 888 continue; 889 890 if (usb_idx == usb4_idx) 891 return p; 892 893 usb_idx++; 894 } 895 896 return NULL; 897 } 898 899 /** 900 * usb4_port_unlock() - Unlock USB4 downstream port 901 * @port: USB4 port to unlock 902 * 903 * Unlocks USB4 downstream port so that the connection manager can 904 * access the router below this port. 905 */ 906 int usb4_port_unlock(struct tb_port *port) 907 { 908 int ret; 909 u32 val; 910 911 ret = tb_port_read(port, &val, TB_CFG_PORT, ADP_CS_4, 1); 912 if (ret) 913 return ret; 914 915 val &= ~ADP_CS_4_LCK; 916 return tb_port_write(port, &val, TB_CFG_PORT, ADP_CS_4, 1); 917 } 918 919 static int usb4_port_set_configured(struct tb_port *port, bool configured) 920 { 921 int ret; 922 u32 val; 923 924 if (!port->cap_usb4) 925 return -EINVAL; 926 927 ret = tb_port_read(port, &val, TB_CFG_PORT, 928 port->cap_usb4 + PORT_CS_19, 1); 929 if (ret) 930 return ret; 931 932 if (configured) 933 val |= PORT_CS_19_PC; 934 else 935 val &= ~PORT_CS_19_PC; 936 937 return tb_port_write(port, &val, TB_CFG_PORT, 938 port->cap_usb4 + PORT_CS_19, 1); 939 } 940 941 /** 942 * usb4_port_configure() - Set USB4 port configured 943 * @port: USB4 router 944 * 945 * Sets the USB4 link to be configured for power management purposes. 946 */ 947 int usb4_port_configure(struct tb_port *port) 948 { 949 return usb4_port_set_configured(port, true); 950 } 951 952 /** 953 * usb4_port_unconfigure() - Set USB4 port unconfigured 954 * @port: USB4 router 955 * 956 * Sets the USB4 link to be unconfigured for power management purposes. 957 */ 958 void usb4_port_unconfigure(struct tb_port *port) 959 { 960 usb4_port_set_configured(port, false); 961 } 962 963 static int usb4_set_xdomain_configured(struct tb_port *port, bool configured) 964 { 965 int ret; 966 u32 val; 967 968 if (!port->cap_usb4) 969 return -EINVAL; 970 971 ret = tb_port_read(port, &val, TB_CFG_PORT, 972 port->cap_usb4 + PORT_CS_19, 1); 973 if (ret) 974 return ret; 975 976 if (configured) 977 val |= PORT_CS_19_PID; 978 else 979 val &= ~PORT_CS_19_PID; 980 981 return tb_port_write(port, &val, TB_CFG_PORT, 982 port->cap_usb4 + PORT_CS_19, 1); 983 } 984 985 /** 986 * usb4_port_configure_xdomain() - Configure port for XDomain 987 * @port: USB4 port connected to another host 988 * 989 * Marks the USB4 port as being connected to another host. Returns %0 in 990 * success and negative errno in failure. 991 */ 992 int usb4_port_configure_xdomain(struct tb_port *port) 993 { 994 return usb4_set_xdomain_configured(port, true); 995 } 996 997 /** 998 * usb4_port_unconfigure_xdomain() - Unconfigure port for XDomain 999 * @port: USB4 port that was connected to another host 1000 * 1001 * Clears USB4 port from being marked as XDomain. 1002 */ 1003 void usb4_port_unconfigure_xdomain(struct tb_port *port) 1004 { 1005 usb4_set_xdomain_configured(port, false); 1006 } 1007 1008 static int usb4_port_wait_for_bit(struct tb_port *port, u32 offset, u32 bit, 1009 u32 value, int timeout_msec) 1010 { 1011 ktime_t timeout = ktime_add_ms(ktime_get(), timeout_msec); 1012 1013 do { 1014 u32 val; 1015 int ret; 1016 1017 ret = tb_port_read(port, &val, TB_CFG_PORT, offset, 1); 1018 if (ret) 1019 return ret; 1020 1021 if ((val & bit) == value) 1022 return 0; 1023 1024 usleep_range(50, 100); 1025 } while (ktime_before(ktime_get(), timeout)); 1026 1027 return -ETIMEDOUT; 1028 } 1029 1030 static int usb4_port_read_data(struct tb_port *port, void *data, size_t dwords) 1031 { 1032 if (dwords > USB4_DATA_DWORDS) 1033 return -EINVAL; 1034 1035 return tb_port_read(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2, 1036 dwords); 1037 } 1038 1039 static int usb4_port_write_data(struct tb_port *port, const void *data, 1040 size_t dwords) 1041 { 1042 if (dwords > USB4_DATA_DWORDS) 1043 return -EINVAL; 1044 1045 return tb_port_write(port, data, TB_CFG_PORT, port->cap_usb4 + PORT_CS_2, 1046 dwords); 1047 } 1048 1049 static int usb4_port_sb_read(struct tb_port *port, enum usb4_sb_target target, 1050 u8 index, u8 reg, void *buf, u8 size) 1051 { 1052 size_t dwords = DIV_ROUND_UP(size, 4); 1053 int ret; 1054 u32 val; 1055 1056 if (!port->cap_usb4) 1057 return -EINVAL; 1058 1059 val = reg; 1060 val |= size << PORT_CS_1_LENGTH_SHIFT; 1061 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK; 1062 if (target == USB4_SB_TARGET_RETIMER) 1063 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT); 1064 val |= PORT_CS_1_PND; 1065 1066 ret = tb_port_write(port, &val, TB_CFG_PORT, 1067 port->cap_usb4 + PORT_CS_1, 1); 1068 if (ret) 1069 return ret; 1070 1071 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1, 1072 PORT_CS_1_PND, 0, 500); 1073 if (ret) 1074 return ret; 1075 1076 ret = tb_port_read(port, &val, TB_CFG_PORT, 1077 port->cap_usb4 + PORT_CS_1, 1); 1078 if (ret) 1079 return ret; 1080 1081 if (val & PORT_CS_1_NR) 1082 return -ENODEV; 1083 if (val & PORT_CS_1_RC) 1084 return -EIO; 1085 1086 return buf ? usb4_port_read_data(port, buf, dwords) : 0; 1087 } 1088 1089 static int usb4_port_sb_write(struct tb_port *port, enum usb4_sb_target target, 1090 u8 index, u8 reg, const void *buf, u8 size) 1091 { 1092 size_t dwords = DIV_ROUND_UP(size, 4); 1093 int ret; 1094 u32 val; 1095 1096 if (!port->cap_usb4) 1097 return -EINVAL; 1098 1099 if (buf) { 1100 ret = usb4_port_write_data(port, buf, dwords); 1101 if (ret) 1102 return ret; 1103 } 1104 1105 val = reg; 1106 val |= size << PORT_CS_1_LENGTH_SHIFT; 1107 val |= PORT_CS_1_WNR_WRITE; 1108 val |= (target << PORT_CS_1_TARGET_SHIFT) & PORT_CS_1_TARGET_MASK; 1109 if (target == USB4_SB_TARGET_RETIMER) 1110 val |= (index << PORT_CS_1_RETIMER_INDEX_SHIFT); 1111 val |= PORT_CS_1_PND; 1112 1113 ret = tb_port_write(port, &val, TB_CFG_PORT, 1114 port->cap_usb4 + PORT_CS_1, 1); 1115 if (ret) 1116 return ret; 1117 1118 ret = usb4_port_wait_for_bit(port, port->cap_usb4 + PORT_CS_1, 1119 PORT_CS_1_PND, 0, 500); 1120 if (ret) 1121 return ret; 1122 1123 ret = tb_port_read(port, &val, TB_CFG_PORT, 1124 port->cap_usb4 + PORT_CS_1, 1); 1125 if (ret) 1126 return ret; 1127 1128 if (val & PORT_CS_1_NR) 1129 return -ENODEV; 1130 if (val & PORT_CS_1_RC) 1131 return -EIO; 1132 1133 return 0; 1134 } 1135 1136 static int usb4_port_sb_op(struct tb_port *port, enum usb4_sb_target target, 1137 u8 index, enum usb4_sb_opcode opcode, int timeout_msec) 1138 { 1139 ktime_t timeout; 1140 u32 val; 1141 int ret; 1142 1143 val = opcode; 1144 ret = usb4_port_sb_write(port, target, index, USB4_SB_OPCODE, &val, 1145 sizeof(val)); 1146 if (ret) 1147 return ret; 1148 1149 timeout = ktime_add_ms(ktime_get(), timeout_msec); 1150 1151 do { 1152 /* Check results */ 1153 ret = usb4_port_sb_read(port, target, index, USB4_SB_OPCODE, 1154 &val, sizeof(val)); 1155 if (ret) 1156 return ret; 1157 1158 switch (val) { 1159 case 0: 1160 return 0; 1161 1162 case USB4_SB_OPCODE_ERR: 1163 return -EAGAIN; 1164 1165 case USB4_SB_OPCODE_ONS: 1166 return -EOPNOTSUPP; 1167 1168 default: 1169 if (val != opcode) 1170 return -EIO; 1171 break; 1172 } 1173 } while (ktime_before(ktime_get(), timeout)); 1174 1175 return -ETIMEDOUT; 1176 } 1177 1178 /** 1179 * usb4_port_enumerate_retimers() - Send RT broadcast transaction 1180 * @port: USB4 port 1181 * 1182 * This forces the USB4 port to send broadcast RT transaction which 1183 * makes the retimers on the link to assign index to themselves. Returns 1184 * %0 in case of success and negative errno if there was an error. 1185 */ 1186 int usb4_port_enumerate_retimers(struct tb_port *port) 1187 { 1188 u32 val; 1189 1190 val = USB4_SB_OPCODE_ENUMERATE_RETIMERS; 1191 return usb4_port_sb_write(port, USB4_SB_TARGET_ROUTER, 0, 1192 USB4_SB_OPCODE, &val, sizeof(val)); 1193 } 1194 1195 static inline int usb4_port_retimer_op(struct tb_port *port, u8 index, 1196 enum usb4_sb_opcode opcode, 1197 int timeout_msec) 1198 { 1199 return usb4_port_sb_op(port, USB4_SB_TARGET_RETIMER, index, opcode, 1200 timeout_msec); 1201 } 1202 1203 /** 1204 * usb4_port_retimer_read() - Read from retimer sideband registers 1205 * @port: USB4 port 1206 * @index: Retimer index 1207 * @reg: Sideband register to read 1208 * @buf: Data from @reg is stored here 1209 * @size: Number of bytes to read 1210 * 1211 * Function reads retimer sideband registers starting from @reg. The 1212 * retimer is connected to @port at @index. Returns %0 in case of 1213 * success, and read data is copied to @buf. If there is no retimer 1214 * present at given @index returns %-ENODEV. In any other failure 1215 * returns negative errno. 1216 */ 1217 int usb4_port_retimer_read(struct tb_port *port, u8 index, u8 reg, void *buf, 1218 u8 size) 1219 { 1220 return usb4_port_sb_read(port, USB4_SB_TARGET_RETIMER, index, reg, buf, 1221 size); 1222 } 1223 1224 /** 1225 * usb4_port_retimer_write() - Write to retimer sideband registers 1226 * @port: USB4 port 1227 * @index: Retimer index 1228 * @reg: Sideband register to write 1229 * @buf: Data that is written starting from @reg 1230 * @size: Number of bytes to write 1231 * 1232 * Writes retimer sideband registers starting from @reg. The retimer is 1233 * connected to @port at @index. Returns %0 in case of success. If there 1234 * is no retimer present at given @index returns %-ENODEV. In any other 1235 * failure returns negative errno. 1236 */ 1237 int usb4_port_retimer_write(struct tb_port *port, u8 index, u8 reg, 1238 const void *buf, u8 size) 1239 { 1240 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, reg, buf, 1241 size); 1242 } 1243 1244 /** 1245 * usb4_port_retimer_is_last() - Is the retimer last on-board retimer 1246 * @port: USB4 port 1247 * @index: Retimer index 1248 * 1249 * If the retimer at @index is last one (connected directly to the 1250 * Type-C port) this function returns %1. If it is not returns %0. If 1251 * the retimer is not present returns %-ENODEV. Otherwise returns 1252 * negative errno. 1253 */ 1254 int usb4_port_retimer_is_last(struct tb_port *port, u8 index) 1255 { 1256 u32 metadata; 1257 int ret; 1258 1259 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_QUERY_LAST_RETIMER, 1260 500); 1261 if (ret) 1262 return ret; 1263 1264 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata, 1265 sizeof(metadata)); 1266 return ret ? ret : metadata & 1; 1267 } 1268 1269 /** 1270 * usb4_port_retimer_nvm_sector_size() - Read retimer NVM sector size 1271 * @port: USB4 port 1272 * @index: Retimer index 1273 * 1274 * Reads NVM sector size (in bytes) of a retimer at @index. This 1275 * operation can be used to determine whether the retimer supports NVM 1276 * upgrade for example. Returns sector size in bytes or negative errno 1277 * in case of error. Specifically returns %-ENODEV if there is no 1278 * retimer at @index. 1279 */ 1280 int usb4_port_retimer_nvm_sector_size(struct tb_port *port, u8 index) 1281 { 1282 u32 metadata; 1283 int ret; 1284 1285 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE, 1286 500); 1287 if (ret) 1288 return ret; 1289 1290 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, &metadata, 1291 sizeof(metadata)); 1292 return ret ? ret : metadata & USB4_NVM_SECTOR_SIZE_MASK; 1293 } 1294 1295 static int usb4_port_retimer_nvm_set_offset(struct tb_port *port, u8 index, 1296 unsigned int address) 1297 { 1298 u32 metadata, dwaddress; 1299 int ret; 1300 1301 dwaddress = address / 4; 1302 metadata = (dwaddress << USB4_NVM_SET_OFFSET_SHIFT) & 1303 USB4_NVM_SET_OFFSET_MASK; 1304 1305 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata, 1306 sizeof(metadata)); 1307 if (ret) 1308 return ret; 1309 1310 return usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_SET_OFFSET, 1311 500); 1312 } 1313 1314 struct retimer_info { 1315 struct tb_port *port; 1316 u8 index; 1317 }; 1318 1319 static int usb4_port_retimer_nvm_write_next_block(void *data, const void *buf, 1320 size_t dwords) 1321 1322 { 1323 const struct retimer_info *info = data; 1324 struct tb_port *port = info->port; 1325 u8 index = info->index; 1326 int ret; 1327 1328 ret = usb4_port_retimer_write(port, index, USB4_SB_DATA, 1329 buf, dwords * 4); 1330 if (ret) 1331 return ret; 1332 1333 return usb4_port_retimer_op(port, index, 1334 USB4_SB_OPCODE_NVM_BLOCK_WRITE, 1000); 1335 } 1336 1337 /** 1338 * usb4_port_retimer_nvm_write() - Write to retimer NVM 1339 * @port: USB4 port 1340 * @index: Retimer index 1341 * @address: Byte address where to start the write 1342 * @buf: Data to write 1343 * @size: Size in bytes how much to write 1344 * 1345 * Writes @size bytes from @buf to the retimer NVM. Used for NVM 1346 * upgrade. Returns %0 if the data was written successfully and negative 1347 * errno in case of failure. Specifically returns %-ENODEV if there is 1348 * no retimer at @index. 1349 */ 1350 int usb4_port_retimer_nvm_write(struct tb_port *port, u8 index, unsigned int address, 1351 const void *buf, size_t size) 1352 { 1353 struct retimer_info info = { .port = port, .index = index }; 1354 int ret; 1355 1356 ret = usb4_port_retimer_nvm_set_offset(port, index, address); 1357 if (ret) 1358 return ret; 1359 1360 return usb4_do_write_data(address, buf, size, 1361 usb4_port_retimer_nvm_write_next_block, &info); 1362 } 1363 1364 /** 1365 * usb4_port_retimer_nvm_authenticate() - Start retimer NVM upgrade 1366 * @port: USB4 port 1367 * @index: Retimer index 1368 * 1369 * After the new NVM image has been written via usb4_port_retimer_nvm_write() 1370 * this function can be used to trigger the NVM upgrade process. If 1371 * successful the retimer restarts with the new NVM and may not have the 1372 * index set so one needs to call usb4_port_enumerate_retimers() to 1373 * force index to be assigned. 1374 */ 1375 int usb4_port_retimer_nvm_authenticate(struct tb_port *port, u8 index) 1376 { 1377 u32 val; 1378 1379 /* 1380 * We need to use the raw operation here because once the 1381 * authentication completes the retimer index is not set anymore 1382 * so we do not get back the status now. 1383 */ 1384 val = USB4_SB_OPCODE_NVM_AUTH_WRITE; 1385 return usb4_port_sb_write(port, USB4_SB_TARGET_RETIMER, index, 1386 USB4_SB_OPCODE, &val, sizeof(val)); 1387 } 1388 1389 /** 1390 * usb4_port_retimer_nvm_authenticate_status() - Read status of NVM upgrade 1391 * @port: USB4 port 1392 * @index: Retimer index 1393 * @status: Raw status code read from metadata 1394 * 1395 * This can be called after usb4_port_retimer_nvm_authenticate() and 1396 * usb4_port_enumerate_retimers() to fetch status of the NVM upgrade. 1397 * 1398 * Returns %0 if the authentication status was successfully read. The 1399 * completion metadata (the result) is then stored into @status. If 1400 * reading the status fails, returns negative errno. 1401 */ 1402 int usb4_port_retimer_nvm_authenticate_status(struct tb_port *port, u8 index, 1403 u32 *status) 1404 { 1405 u32 metadata, val; 1406 int ret; 1407 1408 ret = usb4_port_retimer_read(port, index, USB4_SB_OPCODE, &val, 1409 sizeof(val)); 1410 if (ret) 1411 return ret; 1412 1413 switch (val) { 1414 case 0: 1415 *status = 0; 1416 return 0; 1417 1418 case USB4_SB_OPCODE_ERR: 1419 ret = usb4_port_retimer_read(port, index, USB4_SB_METADATA, 1420 &metadata, sizeof(metadata)); 1421 if (ret) 1422 return ret; 1423 1424 *status = metadata & USB4_SB_METADATA_NVM_AUTH_WRITE_MASK; 1425 return 0; 1426 1427 case USB4_SB_OPCODE_ONS: 1428 return -EOPNOTSUPP; 1429 1430 default: 1431 return -EIO; 1432 } 1433 } 1434 1435 static int usb4_port_retimer_nvm_read_block(void *data, unsigned int dwaddress, 1436 void *buf, size_t dwords) 1437 { 1438 const struct retimer_info *info = data; 1439 struct tb_port *port = info->port; 1440 u8 index = info->index; 1441 u32 metadata; 1442 int ret; 1443 1444 metadata = dwaddress << USB4_NVM_READ_OFFSET_SHIFT; 1445 if (dwords < USB4_DATA_DWORDS) 1446 metadata |= dwords << USB4_NVM_READ_LENGTH_SHIFT; 1447 1448 ret = usb4_port_retimer_write(port, index, USB4_SB_METADATA, &metadata, 1449 sizeof(metadata)); 1450 if (ret) 1451 return ret; 1452 1453 ret = usb4_port_retimer_op(port, index, USB4_SB_OPCODE_NVM_READ, 500); 1454 if (ret) 1455 return ret; 1456 1457 return usb4_port_retimer_read(port, index, USB4_SB_DATA, buf, 1458 dwords * 4); 1459 } 1460 1461 /** 1462 * usb4_port_retimer_nvm_read() - Read contents of retimer NVM 1463 * @port: USB4 port 1464 * @index: Retimer index 1465 * @address: NVM address (in bytes) to start reading 1466 * @buf: Data read from NVM is stored here 1467 * @size: Number of bytes to read 1468 * 1469 * Reads retimer NVM and copies the contents to @buf. Returns %0 if the 1470 * read was successful and negative errno in case of failure. 1471 * Specifically returns %-ENODEV if there is no retimer at @index. 1472 */ 1473 int usb4_port_retimer_nvm_read(struct tb_port *port, u8 index, 1474 unsigned int address, void *buf, size_t size) 1475 { 1476 struct retimer_info info = { .port = port, .index = index }; 1477 1478 return usb4_do_read_data(address, buf, size, 1479 usb4_port_retimer_nvm_read_block, &info); 1480 } 1481 1482 /** 1483 * usb4_usb3_port_max_link_rate() - Maximum support USB3 link rate 1484 * @port: USB3 adapter port 1485 * 1486 * Return maximum supported link rate of a USB3 adapter in Mb/s. 1487 * Negative errno in case of error. 1488 */ 1489 int usb4_usb3_port_max_link_rate(struct tb_port *port) 1490 { 1491 int ret, lr; 1492 u32 val; 1493 1494 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port)) 1495 return -EINVAL; 1496 1497 ret = tb_port_read(port, &val, TB_CFG_PORT, 1498 port->cap_adap + ADP_USB3_CS_4, 1); 1499 if (ret) 1500 return ret; 1501 1502 lr = (val & ADP_USB3_CS_4_MSLR_MASK) >> ADP_USB3_CS_4_MSLR_SHIFT; 1503 return lr == ADP_USB3_CS_4_MSLR_20G ? 20000 : 10000; 1504 } 1505 1506 /** 1507 * usb4_usb3_port_actual_link_rate() - Established USB3 link rate 1508 * @port: USB3 adapter port 1509 * 1510 * Return actual established link rate of a USB3 adapter in Mb/s. If the 1511 * link is not up returns %0 and negative errno in case of failure. 1512 */ 1513 int usb4_usb3_port_actual_link_rate(struct tb_port *port) 1514 { 1515 int ret, lr; 1516 u32 val; 1517 1518 if (!tb_port_is_usb3_down(port) && !tb_port_is_usb3_up(port)) 1519 return -EINVAL; 1520 1521 ret = tb_port_read(port, &val, TB_CFG_PORT, 1522 port->cap_adap + ADP_USB3_CS_4, 1); 1523 if (ret) 1524 return ret; 1525 1526 if (!(val & ADP_USB3_CS_4_ULV)) 1527 return 0; 1528 1529 lr = val & ADP_USB3_CS_4_ALR_MASK; 1530 return lr == ADP_USB3_CS_4_ALR_20G ? 20000 : 10000; 1531 } 1532 1533 static int usb4_usb3_port_cm_request(struct tb_port *port, bool request) 1534 { 1535 int ret; 1536 u32 val; 1537 1538 if (!tb_port_is_usb3_down(port)) 1539 return -EINVAL; 1540 if (tb_route(port->sw)) 1541 return -EINVAL; 1542 1543 ret = tb_port_read(port, &val, TB_CFG_PORT, 1544 port->cap_adap + ADP_USB3_CS_2, 1); 1545 if (ret) 1546 return ret; 1547 1548 if (request) 1549 val |= ADP_USB3_CS_2_CMR; 1550 else 1551 val &= ~ADP_USB3_CS_2_CMR; 1552 1553 ret = tb_port_write(port, &val, TB_CFG_PORT, 1554 port->cap_adap + ADP_USB3_CS_2, 1); 1555 if (ret) 1556 return ret; 1557 1558 /* 1559 * We can use val here directly as the CMR bit is in the same place 1560 * as HCA. Just mask out others. 1561 */ 1562 val &= ADP_USB3_CS_2_CMR; 1563 return usb4_port_wait_for_bit(port, port->cap_adap + ADP_USB3_CS_1, 1564 ADP_USB3_CS_1_HCA, val, 1500); 1565 } 1566 1567 static inline int usb4_usb3_port_set_cm_request(struct tb_port *port) 1568 { 1569 return usb4_usb3_port_cm_request(port, true); 1570 } 1571 1572 static inline int usb4_usb3_port_clear_cm_request(struct tb_port *port) 1573 { 1574 return usb4_usb3_port_cm_request(port, false); 1575 } 1576 1577 static unsigned int usb3_bw_to_mbps(u32 bw, u8 scale) 1578 { 1579 unsigned long uframes; 1580 1581 uframes = bw * 512UL << scale; 1582 return DIV_ROUND_CLOSEST(uframes * 8000, 1000 * 1000); 1583 } 1584 1585 static u32 mbps_to_usb3_bw(unsigned int mbps, u8 scale) 1586 { 1587 unsigned long uframes; 1588 1589 /* 1 uframe is 1/8 ms (125 us) -> 1 / 8000 s */ 1590 uframes = ((unsigned long)mbps * 1000 * 1000) / 8000; 1591 return DIV_ROUND_UP(uframes, 512UL << scale); 1592 } 1593 1594 static int usb4_usb3_port_read_allocated_bandwidth(struct tb_port *port, 1595 int *upstream_bw, 1596 int *downstream_bw) 1597 { 1598 u32 val, bw, scale; 1599 int ret; 1600 1601 ret = tb_port_read(port, &val, TB_CFG_PORT, 1602 port->cap_adap + ADP_USB3_CS_2, 1); 1603 if (ret) 1604 return ret; 1605 1606 ret = tb_port_read(port, &scale, TB_CFG_PORT, 1607 port->cap_adap + ADP_USB3_CS_3, 1); 1608 if (ret) 1609 return ret; 1610 1611 scale &= ADP_USB3_CS_3_SCALE_MASK; 1612 1613 bw = val & ADP_USB3_CS_2_AUBW_MASK; 1614 *upstream_bw = usb3_bw_to_mbps(bw, scale); 1615 1616 bw = (val & ADP_USB3_CS_2_ADBW_MASK) >> ADP_USB3_CS_2_ADBW_SHIFT; 1617 *downstream_bw = usb3_bw_to_mbps(bw, scale); 1618 1619 return 0; 1620 } 1621 1622 /** 1623 * usb4_usb3_port_allocated_bandwidth() - Bandwidth allocated for USB3 1624 * @port: USB3 adapter port 1625 * @upstream_bw: Allocated upstream bandwidth is stored here 1626 * @downstream_bw: Allocated downstream bandwidth is stored here 1627 * 1628 * Stores currently allocated USB3 bandwidth into @upstream_bw and 1629 * @downstream_bw in Mb/s. Returns %0 in case of success and negative 1630 * errno in failure. 1631 */ 1632 int usb4_usb3_port_allocated_bandwidth(struct tb_port *port, int *upstream_bw, 1633 int *downstream_bw) 1634 { 1635 int ret; 1636 1637 ret = usb4_usb3_port_set_cm_request(port); 1638 if (ret) 1639 return ret; 1640 1641 ret = usb4_usb3_port_read_allocated_bandwidth(port, upstream_bw, 1642 downstream_bw); 1643 usb4_usb3_port_clear_cm_request(port); 1644 1645 return ret; 1646 } 1647 1648 static int usb4_usb3_port_read_consumed_bandwidth(struct tb_port *port, 1649 int *upstream_bw, 1650 int *downstream_bw) 1651 { 1652 u32 val, bw, scale; 1653 int ret; 1654 1655 ret = tb_port_read(port, &val, TB_CFG_PORT, 1656 port->cap_adap + ADP_USB3_CS_1, 1); 1657 if (ret) 1658 return ret; 1659 1660 ret = tb_port_read(port, &scale, TB_CFG_PORT, 1661 port->cap_adap + ADP_USB3_CS_3, 1); 1662 if (ret) 1663 return ret; 1664 1665 scale &= ADP_USB3_CS_3_SCALE_MASK; 1666 1667 bw = val & ADP_USB3_CS_1_CUBW_MASK; 1668 *upstream_bw = usb3_bw_to_mbps(bw, scale); 1669 1670 bw = (val & ADP_USB3_CS_1_CDBW_MASK) >> ADP_USB3_CS_1_CDBW_SHIFT; 1671 *downstream_bw = usb3_bw_to_mbps(bw, scale); 1672 1673 return 0; 1674 } 1675 1676 static int usb4_usb3_port_write_allocated_bandwidth(struct tb_port *port, 1677 int upstream_bw, 1678 int downstream_bw) 1679 { 1680 u32 val, ubw, dbw, scale; 1681 int ret; 1682 1683 /* Read the used scale, hardware default is 0 */ 1684 ret = tb_port_read(port, &scale, TB_CFG_PORT, 1685 port->cap_adap + ADP_USB3_CS_3, 1); 1686 if (ret) 1687 return ret; 1688 1689 scale &= ADP_USB3_CS_3_SCALE_MASK; 1690 ubw = mbps_to_usb3_bw(upstream_bw, scale); 1691 dbw = mbps_to_usb3_bw(downstream_bw, scale); 1692 1693 ret = tb_port_read(port, &val, TB_CFG_PORT, 1694 port->cap_adap + ADP_USB3_CS_2, 1); 1695 if (ret) 1696 return ret; 1697 1698 val &= ~(ADP_USB3_CS_2_AUBW_MASK | ADP_USB3_CS_2_ADBW_MASK); 1699 val |= dbw << ADP_USB3_CS_2_ADBW_SHIFT; 1700 val |= ubw; 1701 1702 return tb_port_write(port, &val, TB_CFG_PORT, 1703 port->cap_adap + ADP_USB3_CS_2, 1); 1704 } 1705 1706 /** 1707 * usb4_usb3_port_allocate_bandwidth() - Allocate bandwidth for USB3 1708 * @port: USB3 adapter port 1709 * @upstream_bw: New upstream bandwidth 1710 * @downstream_bw: New downstream bandwidth 1711 * 1712 * This can be used to set how much bandwidth is allocated for the USB3 1713 * tunneled isochronous traffic. @upstream_bw and @downstream_bw are the 1714 * new values programmed to the USB3 adapter allocation registers. If 1715 * the values are lower than what is currently consumed the allocation 1716 * is set to what is currently consumed instead (consumed bandwidth 1717 * cannot be taken away by CM). The actual new values are returned in 1718 * @upstream_bw and @downstream_bw. 1719 * 1720 * Returns %0 in case of success and negative errno if there was a 1721 * failure. 1722 */ 1723 int usb4_usb3_port_allocate_bandwidth(struct tb_port *port, int *upstream_bw, 1724 int *downstream_bw) 1725 { 1726 int ret, consumed_up, consumed_down, allocate_up, allocate_down; 1727 1728 ret = usb4_usb3_port_set_cm_request(port); 1729 if (ret) 1730 return ret; 1731 1732 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up, 1733 &consumed_down); 1734 if (ret) 1735 goto err_request; 1736 1737 /* Don't allow it go lower than what is consumed */ 1738 allocate_up = max(*upstream_bw, consumed_up); 1739 allocate_down = max(*downstream_bw, consumed_down); 1740 1741 ret = usb4_usb3_port_write_allocated_bandwidth(port, allocate_up, 1742 allocate_down); 1743 if (ret) 1744 goto err_request; 1745 1746 *upstream_bw = allocate_up; 1747 *downstream_bw = allocate_down; 1748 1749 err_request: 1750 usb4_usb3_port_clear_cm_request(port); 1751 return ret; 1752 } 1753 1754 /** 1755 * usb4_usb3_port_release_bandwidth() - Release allocated USB3 bandwidth 1756 * @port: USB3 adapter port 1757 * @upstream_bw: New allocated upstream bandwidth 1758 * @downstream_bw: New allocated downstream bandwidth 1759 * 1760 * Releases USB3 allocated bandwidth down to what is actually consumed. 1761 * The new bandwidth is returned in @upstream_bw and @downstream_bw. 1762 * 1763 * Returns 0% in success and negative errno in case of failure. 1764 */ 1765 int usb4_usb3_port_release_bandwidth(struct tb_port *port, int *upstream_bw, 1766 int *downstream_bw) 1767 { 1768 int ret, consumed_up, consumed_down; 1769 1770 ret = usb4_usb3_port_set_cm_request(port); 1771 if (ret) 1772 return ret; 1773 1774 ret = usb4_usb3_port_read_consumed_bandwidth(port, &consumed_up, 1775 &consumed_down); 1776 if (ret) 1777 goto err_request; 1778 1779 /* 1780 * Always keep 1000 Mb/s to make sure xHCI has at least some 1781 * bandwidth available for isochronous traffic. 1782 */ 1783 if (consumed_up < 1000) 1784 consumed_up = 1000; 1785 if (consumed_down < 1000) 1786 consumed_down = 1000; 1787 1788 ret = usb4_usb3_port_write_allocated_bandwidth(port, consumed_up, 1789 consumed_down); 1790 if (ret) 1791 goto err_request; 1792 1793 *upstream_bw = consumed_up; 1794 *downstream_bw = consumed_down; 1795 1796 err_request: 1797 usb4_usb3_port_clear_cm_request(port); 1798 return ret; 1799 } 1800