1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Thunderbolt driver - Port/Switch config area registers 4 * 5 * Every thunderbolt device consists (logically) of a switch with multiple 6 * ports. Every port contains up to four config regions (HOPS, PORT, SWITCH, 7 * COUNTERS) which are used to configure the device. 8 * 9 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> 10 * Copyright (C) 2018, Intel Corporation 11 */ 12 13 #ifndef _TB_REGS 14 #define _TB_REGS 15 16 #include <linux/types.h> 17 18 19 #define TB_ROUTE_SHIFT 8 /* number of bits in a port entry of a route */ 20 21 22 /* 23 * TODO: should be 63? But we do not know how to receive frames larger than 256 24 * bytes at the frame level. (header + checksum = 16, 60*4 = 240) 25 */ 26 #define TB_MAX_CONFIG_RW_LENGTH 60 27 28 enum tb_switch_cap { 29 TB_SWITCH_CAP_TMU = 0x03, 30 TB_SWITCH_CAP_VSE = 0x05, 31 }; 32 33 enum tb_switch_vse_cap { 34 TB_VSE_CAP_PLUG_EVENTS = 0x01, /* also EEPROM */ 35 TB_VSE_CAP_TIME2 = 0x03, 36 TB_VSE_CAP_CP_LP = 0x04, 37 TB_VSE_CAP_LINK_CONTROLLER = 0x06, /* also IECS */ 38 }; 39 40 enum tb_port_cap { 41 TB_PORT_CAP_PHY = 0x01, 42 TB_PORT_CAP_POWER = 0x02, 43 TB_PORT_CAP_TIME1 = 0x03, 44 TB_PORT_CAP_ADAP = 0x04, 45 TB_PORT_CAP_VSE = 0x05, 46 TB_PORT_CAP_USB4 = 0x06, 47 }; 48 49 enum tb_port_state { 50 TB_PORT_DISABLED = 0, /* tb_cap_phy.disable == 1 */ 51 TB_PORT_CONNECTING = 1, /* retry */ 52 TB_PORT_UP = 2, 53 TB_PORT_UNPLUGGED = 7, 54 }; 55 56 /* capability headers */ 57 58 struct tb_cap_basic { 59 u8 next; 60 /* enum tb_cap cap:8; prevent "narrower than values of its type" */ 61 u8 cap; /* if cap == 0x05 then we have a extended capability */ 62 } __packed; 63 64 /** 65 * struct tb_cap_extended_short - Switch extended short capability 66 * @next: Pointer to the next capability. If @next and @length are zero 67 * then we have a long cap. 68 * @cap: Base capability ID (see &enum tb_switch_cap) 69 * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap) 70 * @length: Length of this capability 71 */ 72 struct tb_cap_extended_short { 73 u8 next; 74 u8 cap; 75 u8 vsec_id; 76 u8 length; 77 } __packed; 78 79 /** 80 * struct tb_cap_extended_long - Switch extended long capability 81 * @zero1: This field should be zero 82 * @cap: Base capability ID (see &enum tb_switch_cap) 83 * @vsec_id: Vendor specific capability ID (see &enum switch_vse_cap) 84 * @zero2: This field should be zero 85 * @next: Pointer to the next capability 86 * @length: Length of this capability 87 */ 88 struct tb_cap_extended_long { 89 u8 zero1; 90 u8 cap; 91 u8 vsec_id; 92 u8 zero2; 93 u16 next; 94 u16 length; 95 } __packed; 96 97 /** 98 * struct tb_cap_any - Structure capable of hold every capability 99 * @basic: Basic capability 100 * @extended_short: Vendor specific capability 101 * @extended_long: Vendor specific extended capability 102 */ 103 struct tb_cap_any { 104 union { 105 struct tb_cap_basic basic; 106 struct tb_cap_extended_short extended_short; 107 struct tb_cap_extended_long extended_long; 108 }; 109 } __packed; 110 111 /* capabilities */ 112 113 struct tb_cap_link_controller { 114 struct tb_cap_extended_long cap_header; 115 u32 count:4; /* number of link controllers */ 116 u32 unknown1:4; 117 u32 base_offset:8; /* 118 * offset (into this capability) of the configuration 119 * area of the first link controller 120 */ 121 u32 length:12; /* link controller configuration area length */ 122 u32 unknown2:4; /* TODO check that length is correct */ 123 } __packed; 124 125 struct tb_cap_phy { 126 struct tb_cap_basic cap_header; 127 u32 unknown1:16; 128 u32 unknown2:14; 129 bool disable:1; 130 u32 unknown3:11; 131 enum tb_port_state state:4; 132 u32 unknown4:2; 133 } __packed; 134 135 struct tb_eeprom_ctl { 136 bool fl_sk:1; /* send pulse to transfer one bit */ 137 bool fl_cs:1; /* set to 0 before access */ 138 bool fl_di:1; /* to eeprom */ 139 bool fl_do:1; /* from eeprom */ 140 bool bit_banging_enable:1; /* set to 1 before access */ 141 bool not_present:1; /* should be 0 */ 142 bool unknown1:1; 143 bool present:1; /* should be 1 */ 144 u32 unknown2:24; 145 } __packed; 146 147 struct tb_cap_plug_events { 148 struct tb_cap_extended_short cap_header; 149 u32 __unknown1:2; /* VSC_CS_1 */ 150 u32 plug_events:5; /* VSC_CS_1 */ 151 u32 __unknown2:25; /* VSC_CS_1 */ 152 u32 vsc_cs_2; 153 u32 vsc_cs_3; 154 struct tb_eeprom_ctl eeprom_ctl; 155 u32 __unknown5[7]; /* VSC_CS_5 -> VSC_CS_11 */ 156 u32 drom_offset; /* VSC_CS_12: 32 bit register, but eeprom addresses are 16 bit */ 157 } __packed; 158 159 /* device headers */ 160 161 /* Present on port 0 in TB_CFG_SWITCH at address zero. */ 162 struct tb_regs_switch_header { 163 /* DWORD 0 */ 164 u16 vendor_id; 165 u16 device_id; 166 /* DWORD 1 */ 167 u32 first_cap_offset:8; 168 u32 upstream_port_number:6; 169 u32 max_port_number:6; 170 u32 depth:3; 171 u32 __unknown1:1; 172 u32 revision:8; 173 /* DWORD 2 */ 174 u32 route_lo; 175 /* DWORD 3 */ 176 u32 route_hi:31; 177 bool enabled:1; 178 /* DWORD 4 */ 179 u32 plug_events_delay:8; /* 180 * RW, pause between plug events in 181 * milliseconds. Writing 0x00 is interpreted 182 * as 255ms. 183 */ 184 u32 cmuv:8; 185 u32 __unknown4:8; 186 u32 thunderbolt_version:8; 187 } __packed; 188 189 /* USB4 version 1.0 */ 190 #define USB4_VERSION_1_0 0x20 191 192 #define ROUTER_CS_1 0x01 193 #define ROUTER_CS_4 0x04 194 #define ROUTER_CS_5 0x05 195 #define ROUTER_CS_5_SLP BIT(0) 196 #define ROUTER_CS_5_WOP BIT(1) 197 #define ROUTER_CS_5_WOU BIT(2) 198 #define ROUTER_CS_5_WOD BIT(3) 199 #define ROUTER_CS_5_C3S BIT(23) 200 #define ROUTER_CS_5_PTO BIT(24) 201 #define ROUTER_CS_5_UTO BIT(25) 202 #define ROUTER_CS_5_HCO BIT(26) 203 #define ROUTER_CS_5_CV BIT(31) 204 #define ROUTER_CS_6 0x06 205 #define ROUTER_CS_6_SLPR BIT(0) 206 #define ROUTER_CS_6_TNS BIT(1) 207 #define ROUTER_CS_6_WOPS BIT(2) 208 #define ROUTER_CS_6_WOUS BIT(3) 209 #define ROUTER_CS_6_HCI BIT(18) 210 #define ROUTER_CS_6_CR BIT(25) 211 #define ROUTER_CS_7 0x07 212 #define ROUTER_CS_9 0x09 213 #define ROUTER_CS_25 0x19 214 #define ROUTER_CS_26 0x1a 215 #define ROUTER_CS_26_OPCODE_MASK GENMASK(15, 0) 216 #define ROUTER_CS_26_STATUS_MASK GENMASK(29, 24) 217 #define ROUTER_CS_26_STATUS_SHIFT 24 218 #define ROUTER_CS_26_ONS BIT(30) 219 #define ROUTER_CS_26_OV BIT(31) 220 221 /* USB4 router operations opcodes */ 222 enum usb4_switch_op { 223 USB4_SWITCH_OP_QUERY_DP_RESOURCE = 0x10, 224 USB4_SWITCH_OP_ALLOC_DP_RESOURCE = 0x11, 225 USB4_SWITCH_OP_DEALLOC_DP_RESOURCE = 0x12, 226 USB4_SWITCH_OP_NVM_WRITE = 0x20, 227 USB4_SWITCH_OP_NVM_AUTH = 0x21, 228 USB4_SWITCH_OP_NVM_READ = 0x22, 229 USB4_SWITCH_OP_NVM_SET_OFFSET = 0x23, 230 USB4_SWITCH_OP_DROM_READ = 0x24, 231 USB4_SWITCH_OP_NVM_SECTOR_SIZE = 0x25, 232 USB4_SWITCH_OP_BUFFER_ALLOC = 0x33, 233 }; 234 235 /* Router TMU configuration */ 236 #define TMU_RTR_CS_0 0x00 237 #define TMU_RTR_CS_0_TD BIT(27) 238 #define TMU_RTR_CS_0_UCAP BIT(30) 239 #define TMU_RTR_CS_1 0x01 240 #define TMU_RTR_CS_1_LOCAL_TIME_NS_MASK GENMASK(31, 16) 241 #define TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT 16 242 #define TMU_RTR_CS_2 0x02 243 #define TMU_RTR_CS_3 0x03 244 #define TMU_RTR_CS_3_LOCAL_TIME_NS_MASK GENMASK(15, 0) 245 #define TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK GENMASK(31, 16) 246 #define TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT 16 247 #define TMU_RTR_CS_22 0x16 248 #define TMU_RTR_CS_24 0x18 249 #define TMU_RTR_CS_25 0x19 250 251 enum tb_port_type { 252 TB_TYPE_INACTIVE = 0x000000, 253 TB_TYPE_PORT = 0x000001, 254 TB_TYPE_NHI = 0x000002, 255 /* TB_TYPE_ETHERNET = 0x020000, lower order bits are not known */ 256 /* TB_TYPE_SATA = 0x080000, lower order bits are not known */ 257 TB_TYPE_DP_HDMI_IN = 0x0e0101, 258 TB_TYPE_DP_HDMI_OUT = 0x0e0102, 259 TB_TYPE_PCIE_DOWN = 0x100101, 260 TB_TYPE_PCIE_UP = 0x100102, 261 TB_TYPE_USB3_DOWN = 0x200101, 262 TB_TYPE_USB3_UP = 0x200102, 263 }; 264 265 /* Present on every port in TB_CF_PORT at address zero. */ 266 struct tb_regs_port_header { 267 /* DWORD 0 */ 268 u16 vendor_id; 269 u16 device_id; 270 /* DWORD 1 */ 271 u32 first_cap_offset:8; 272 u32 max_counters:11; 273 u32 counters_support:1; 274 u32 __unknown1:4; 275 u32 revision:8; 276 /* DWORD 2 */ 277 enum tb_port_type type:24; 278 u32 thunderbolt_version:8; 279 /* DWORD 3 */ 280 u32 __unknown2:20; 281 u32 port_number:6; 282 u32 __unknown3:6; 283 /* DWORD 4 */ 284 u32 nfc_credits; 285 /* DWORD 5 */ 286 u32 max_in_hop_id:11; 287 u32 max_out_hop_id:11; 288 u32 __unknown4:10; 289 /* DWORD 6 */ 290 u32 __unknown5; 291 /* DWORD 7 */ 292 u32 __unknown6; 293 294 } __packed; 295 296 /* Basic adapter configuration registers */ 297 #define ADP_CS_4 0x04 298 #define ADP_CS_4_NFC_BUFFERS_MASK GENMASK(9, 0) 299 #define ADP_CS_4_TOTAL_BUFFERS_MASK GENMASK(29, 20) 300 #define ADP_CS_4_TOTAL_BUFFERS_SHIFT 20 301 #define ADP_CS_4_LCK BIT(31) 302 #define ADP_CS_5 0x05 303 #define ADP_CS_5_LCA_MASK GENMASK(28, 22) 304 #define ADP_CS_5_LCA_SHIFT 22 305 306 /* TMU adapter registers */ 307 #define TMU_ADP_CS_3 0x03 308 #define TMU_ADP_CS_3_UDM BIT(29) 309 #define TMU_ADP_CS_6 0x06 310 #define TMU_ADP_CS_6_DTS BIT(1) 311 312 /* Lane adapter registers */ 313 #define LANE_ADP_CS_0 0x00 314 #define LANE_ADP_CS_0_SUPPORTED_SPEED_MASK GENMASK(19, 16) 315 #define LANE_ADP_CS_0_SUPPORTED_SPEED_SHIFT 16 316 #define LANE_ADP_CS_0_SUPPORTED_WIDTH_MASK GENMASK(25, 20) 317 #define LANE_ADP_CS_0_SUPPORTED_WIDTH_SHIFT 20 318 #define LANE_ADP_CS_0_SUPPORTED_WIDTH_DUAL 0x2 319 #define LANE_ADP_CS_0_CL0S_SUPPORT BIT(26) 320 #define LANE_ADP_CS_0_CL1_SUPPORT BIT(27) 321 #define LANE_ADP_CS_1 0x01 322 #define LANE_ADP_CS_1_TARGET_SPEED_MASK GENMASK(3, 0) 323 #define LANE_ADP_CS_1_TARGET_SPEED_GEN3 0xc 324 #define LANE_ADP_CS_1_TARGET_WIDTH_MASK GENMASK(9, 4) 325 #define LANE_ADP_CS_1_TARGET_WIDTH_SHIFT 4 326 #define LANE_ADP_CS_1_TARGET_WIDTH_SINGLE 0x1 327 #define LANE_ADP_CS_1_TARGET_WIDTH_DUAL 0x3 328 #define LANE_ADP_CS_1_CL0S_ENABLE BIT(10) 329 #define LANE_ADP_CS_1_CL1_ENABLE BIT(11) 330 #define LANE_ADP_CS_1_LD BIT(14) 331 #define LANE_ADP_CS_1_LB BIT(15) 332 #define LANE_ADP_CS_1_CURRENT_SPEED_MASK GENMASK(19, 16) 333 #define LANE_ADP_CS_1_CURRENT_SPEED_SHIFT 16 334 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN2 0x8 335 #define LANE_ADP_CS_1_CURRENT_SPEED_GEN3 0x4 336 #define LANE_ADP_CS_1_CURRENT_WIDTH_MASK GENMASK(25, 20) 337 #define LANE_ADP_CS_1_CURRENT_WIDTH_SHIFT 20 338 #define LANE_ADP_CS_1_PMS BIT(30) 339 340 /* USB4 port registers */ 341 #define PORT_CS_1 0x01 342 #define PORT_CS_1_LENGTH_SHIFT 8 343 #define PORT_CS_1_TARGET_MASK GENMASK(18, 16) 344 #define PORT_CS_1_TARGET_SHIFT 16 345 #define PORT_CS_1_RETIMER_INDEX_SHIFT 20 346 #define PORT_CS_1_WNR_WRITE BIT(24) 347 #define PORT_CS_1_NR BIT(25) 348 #define PORT_CS_1_RC BIT(26) 349 #define PORT_CS_1_PND BIT(31) 350 #define PORT_CS_2 0x02 351 #define PORT_CS_18 0x12 352 #define PORT_CS_18_BE BIT(8) 353 #define PORT_CS_18_TCM BIT(9) 354 #define PORT_CS_18_CPS BIT(10) 355 #define PORT_CS_18_WOU4S BIT(18) 356 #define PORT_CS_19 0x13 357 #define PORT_CS_19_PC BIT(3) 358 #define PORT_CS_19_PID BIT(4) 359 #define PORT_CS_19_WOC BIT(16) 360 #define PORT_CS_19_WOD BIT(17) 361 #define PORT_CS_19_WOU4 BIT(18) 362 363 /* Display Port adapter registers */ 364 #define ADP_DP_CS_0 0x00 365 #define ADP_DP_CS_0_VIDEO_HOPID_MASK GENMASK(26, 16) 366 #define ADP_DP_CS_0_VIDEO_HOPID_SHIFT 16 367 #define ADP_DP_CS_0_AE BIT(30) 368 #define ADP_DP_CS_0_VE BIT(31) 369 #define ADP_DP_CS_1_AUX_TX_HOPID_MASK GENMASK(10, 0) 370 #define ADP_DP_CS_1_AUX_RX_HOPID_MASK GENMASK(21, 11) 371 #define ADP_DP_CS_1_AUX_RX_HOPID_SHIFT 11 372 #define ADP_DP_CS_2 0x02 373 #define ADP_DP_CS_2_HDP BIT(6) 374 #define ADP_DP_CS_3 0x03 375 #define ADP_DP_CS_3_HDPC BIT(9) 376 #define DP_LOCAL_CAP 0x04 377 #define DP_REMOTE_CAP 0x05 378 #define DP_STATUS_CTRL 0x06 379 #define DP_STATUS_CTRL_CMHS BIT(25) 380 #define DP_STATUS_CTRL_UF BIT(26) 381 #define DP_COMMON_CAP 0x07 382 /* 383 * DP_COMMON_CAP offsets work also for DP_LOCAL_CAP and DP_REMOTE_CAP 384 * with exception of DPRX done. 385 */ 386 #define DP_COMMON_CAP_RATE_MASK GENMASK(11, 8) 387 #define DP_COMMON_CAP_RATE_SHIFT 8 388 #define DP_COMMON_CAP_RATE_RBR 0x0 389 #define DP_COMMON_CAP_RATE_HBR 0x1 390 #define DP_COMMON_CAP_RATE_HBR2 0x2 391 #define DP_COMMON_CAP_RATE_HBR3 0x3 392 #define DP_COMMON_CAP_LANES_MASK GENMASK(14, 12) 393 #define DP_COMMON_CAP_LANES_SHIFT 12 394 #define DP_COMMON_CAP_1_LANE 0x0 395 #define DP_COMMON_CAP_2_LANES 0x1 396 #define DP_COMMON_CAP_4_LANES 0x2 397 #define DP_COMMON_CAP_LTTPR_NS BIT(27) 398 #define DP_COMMON_CAP_DPRX_DONE BIT(31) 399 400 /* PCIe adapter registers */ 401 #define ADP_PCIE_CS_0 0x00 402 #define ADP_PCIE_CS_0_PE BIT(31) 403 404 /* USB adapter registers */ 405 #define ADP_USB3_CS_0 0x00 406 #define ADP_USB3_CS_0_V BIT(30) 407 #define ADP_USB3_CS_0_PE BIT(31) 408 #define ADP_USB3_CS_1 0x01 409 #define ADP_USB3_CS_1_CUBW_MASK GENMASK(11, 0) 410 #define ADP_USB3_CS_1_CDBW_MASK GENMASK(23, 12) 411 #define ADP_USB3_CS_1_CDBW_SHIFT 12 412 #define ADP_USB3_CS_1_HCA BIT(31) 413 #define ADP_USB3_CS_2 0x02 414 #define ADP_USB3_CS_2_AUBW_MASK GENMASK(11, 0) 415 #define ADP_USB3_CS_2_ADBW_MASK GENMASK(23, 12) 416 #define ADP_USB3_CS_2_ADBW_SHIFT 12 417 #define ADP_USB3_CS_2_CMR BIT(31) 418 #define ADP_USB3_CS_3 0x03 419 #define ADP_USB3_CS_3_SCALE_MASK GENMASK(5, 0) 420 #define ADP_USB3_CS_4 0x04 421 #define ADP_USB3_CS_4_ALR_MASK GENMASK(6, 0) 422 #define ADP_USB3_CS_4_ALR_20G 0x1 423 #define ADP_USB3_CS_4_ULV BIT(7) 424 #define ADP_USB3_CS_4_MSLR_MASK GENMASK(18, 12) 425 #define ADP_USB3_CS_4_MSLR_SHIFT 12 426 #define ADP_USB3_CS_4_MSLR_20G 0x1 427 428 /* Hop register from TB_CFG_HOPS. 8 byte per entry. */ 429 struct tb_regs_hop { 430 /* DWORD 0 */ 431 u32 next_hop:11; /* 432 * hop to take after sending the packet through 433 * out_port (on the incoming port of the next switch) 434 */ 435 u32 out_port:6; /* next port of the path (on the same switch) */ 436 u32 initial_credits:8; 437 u32 unknown1:6; /* set to zero */ 438 bool enable:1; 439 440 /* DWORD 1 */ 441 u32 weight:4; 442 u32 unknown2:4; /* set to zero */ 443 u32 priority:3; 444 bool drop_packages:1; 445 u32 counter:11; /* index into TB_CFG_COUNTERS on this port */ 446 bool counter_enable:1; 447 bool ingress_fc:1; 448 bool egress_fc:1; 449 bool ingress_shared_buffer:1; 450 bool egress_shared_buffer:1; 451 bool pending:1; 452 u32 unknown3:3; /* set to zero */ 453 } __packed; 454 455 /* TMU Thunderbolt 3 registers */ 456 #define TB_TIME_VSEC_3_CS_9 0x9 457 #define TB_TIME_VSEC_3_CS_9_TMU_OBJ_MASK GENMASK(17, 16) 458 #define TB_TIME_VSEC_3_CS_26 0x1a 459 #define TB_TIME_VSEC_3_CS_26_TD BIT(22) 460 461 /* 462 * Used for Titan Ridge only. Bits are part of the same register: TMU_ADP_CS_6 463 * (see above) as in USB4 spec, but these specific bits used for Titan Ridge 464 * only and reserved in USB4 spec. 465 */ 466 #define TMU_ADP_CS_6_DISABLE_TMU_OBJ_MASK GENMASK(3, 2) 467 #define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL1 BIT(2) 468 #define TMU_ADP_CS_6_DISABLE_TMU_OBJ_CL2 BIT(3) 469 470 /* Plug Events registers */ 471 #define TB_PLUG_EVENTS_USB_DISABLE BIT(2) 472 #define TB_PLUG_EVENTS_CS_1_LANE_DISABLE BIT(3) 473 #define TB_PLUG_EVENTS_CS_1_DPOUT_DISABLE BIT(4) 474 #define TB_PLUG_EVENTS_CS_1_LOW_DPIN_DISABLE BIT(5) 475 #define TB_PLUG_EVENTS_CS_1_HIGH_DPIN_DISABLE BIT(6) 476 477 #define TB_PLUG_EVENTS_PCIE_WR_DATA 0x1b 478 #define TB_PLUG_EVENTS_PCIE_CMD 0x1c 479 #define TB_PLUG_EVENTS_PCIE_CMD_DW_OFFSET_MASK GENMASK(9, 0) 480 #define TB_PLUG_EVENTS_PCIE_CMD_BR_SHIFT 10 481 #define TB_PLUG_EVENTS_PCIE_CMD_BR_MASK GENMASK(17, 10) 482 #define TB_PLUG_EVENTS_PCIE_CMD_RD_WR_MASK BIT(21) 483 #define TB_PLUG_EVENTS_PCIE_CMD_WR 0x1 484 #define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_SHIFT 22 485 #define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_MASK GENMASK(24, 22) 486 #define TB_PLUG_EVENTS_PCIE_CMD_COMMAND_VAL 0x2 487 #define TB_PLUG_EVENTS_PCIE_CMD_REQ_ACK_MASK BIT(30) 488 #define TB_PLUG_EVENTS_PCIE_CMD_TIMEOUT_MASK BIT(31) 489 #define TB_PLUG_EVENTS_PCIE_CMD_RD_DATA 0x1d 490 491 /* CP Low Power registers */ 492 #define TB_LOW_PWR_C1_CL1 0x1 493 #define TB_LOW_PWR_C1_CL1_OBJ_MASK GENMASK(4, 1) 494 #define TB_LOW_PWR_C1_CL2_OBJ_MASK GENMASK(4, 1) 495 #define TB_LOW_PWR_C1_PORT_A_MASK GENMASK(2, 1) 496 #define TB_LOW_PWR_C0_PORT_B_MASK GENMASK(4, 3) 497 #define TB_LOW_PWR_C3_CL1 0x3 498 499 /* Common link controller registers */ 500 #define TB_LC_DESC 0x02 501 #define TB_LC_DESC_NLC_MASK GENMASK(3, 0) 502 #define TB_LC_DESC_SIZE_SHIFT 8 503 #define TB_LC_DESC_SIZE_MASK GENMASK(15, 8) 504 #define TB_LC_DESC_PORT_SIZE_SHIFT 16 505 #define TB_LC_DESC_PORT_SIZE_MASK GENMASK(27, 16) 506 #define TB_LC_FUSE 0x03 507 #define TB_LC_SNK_ALLOCATION 0x10 508 #define TB_LC_SNK_ALLOCATION_SNK0_MASK GENMASK(3, 0) 509 #define TB_LC_SNK_ALLOCATION_SNK0_CM 0x1 510 #define TB_LC_SNK_ALLOCATION_SNK1_SHIFT 4 511 #define TB_LC_SNK_ALLOCATION_SNK1_MASK GENMASK(7, 4) 512 #define TB_LC_SNK_ALLOCATION_SNK1_CM 0x1 513 #define TB_LC_POWER 0x740 514 515 /* Link controller registers */ 516 #define TB_LC_CS_42 0x2a 517 #define TB_LC_CS_42_USB_PLUGGED BIT(31) 518 519 #define TB_LC_PORT_ATTR 0x8d 520 #define TB_LC_PORT_ATTR_BE BIT(12) 521 522 #define TB_LC_SX_CTRL 0x96 523 #define TB_LC_SX_CTRL_WOC BIT(1) 524 #define TB_LC_SX_CTRL_WOD BIT(2) 525 #define TB_LC_SX_CTRL_WODPC BIT(3) 526 #define TB_LC_SX_CTRL_WODPD BIT(4) 527 #define TB_LC_SX_CTRL_WOU4 BIT(5) 528 #define TB_LC_SX_CTRL_WOP BIT(6) 529 #define TB_LC_SX_CTRL_L1C BIT(16) 530 #define TB_LC_SX_CTRL_L1D BIT(17) 531 #define TB_LC_SX_CTRL_L2C BIT(20) 532 #define TB_LC_SX_CTRL_L2D BIT(21) 533 #define TB_LC_SX_CTRL_SLI BIT(29) 534 #define TB_LC_SX_CTRL_UPSTREAM BIT(30) 535 #define TB_LC_SX_CTRL_SLP BIT(31) 536 #define TB_LC_LINK_ATTR 0x97 537 #define TB_LC_LINK_ATTR_CPS BIT(18) 538 539 #define TB_LC_LINK_REQ 0xad 540 #define TB_LC_LINK_REQ_XHCI_CONNECT BIT(31) 541 542 #endif 543