102d12855SRajmohan Mani /* SPDX-License-Identifier: GPL-2.0 */ 202d12855SRajmohan Mani /* 302d12855SRajmohan Mani * USB4 port sideband registers found on routers and retimers 402d12855SRajmohan Mani * 502d12855SRajmohan Mani * Copyright (C) 2020, Intel Corporation 602d12855SRajmohan Mani * Authors: Mika Westerberg <mika.westerberg@linux.intel.com> 702d12855SRajmohan Mani * Rajmohan Mani <rajmohan.mani@intel.com> 802d12855SRajmohan Mani */ 902d12855SRajmohan Mani 1002d12855SRajmohan Mani #ifndef _SB_REGS 1102d12855SRajmohan Mani #define _SB_REGS 1202d12855SRajmohan Mani 13dacb1287SKranthi Kuntala #define USB4_SB_VENDOR_ID 0x00 14dacb1287SKranthi Kuntala #define USB4_SB_PRODUCT_ID 0x01 1502d12855SRajmohan Mani #define USB4_SB_OPCODE 0x08 1602d12855SRajmohan Mani 1702d12855SRajmohan Mani enum usb4_sb_opcode { 1802d12855SRajmohan Mani USB4_SB_OPCODE_ERR = 0x20525245, /* "ERR " */ 1902d12855SRajmohan Mani USB4_SB_OPCODE_ONS = 0x444d4321, /* "!CMD" */ 203406de7cSRajmohan Mani USB4_SB_OPCODE_ROUTER_OFFLINE = 0x4e45534c, /* "LSEN" */ 2102d12855SRajmohan Mani USB4_SB_OPCODE_ENUMERATE_RETIMERS = 0x4d554e45, /* "ENUM" */ 223406de7cSRajmohan Mani USB4_SB_OPCODE_SET_INBOUND_SBTX = 0x5055534c, /* "LSUP" */ 2302d12855SRajmohan Mani USB4_SB_OPCODE_QUERY_LAST_RETIMER = 0x5453414c, /* "LAST" */ 2402d12855SRajmohan Mani USB4_SB_OPCODE_GET_NVM_SECTOR_SIZE = 0x53534e47, /* "GNSS" */ 2502d12855SRajmohan Mani USB4_SB_OPCODE_NVM_SET_OFFSET = 0x53504f42, /* "BOPS" */ 2602d12855SRajmohan Mani USB4_SB_OPCODE_NVM_BLOCK_WRITE = 0x574b4c42, /* "BLKW" */ 2702d12855SRajmohan Mani USB4_SB_OPCODE_NVM_AUTH_WRITE = 0x48545541, /* "AUTH" */ 2802d12855SRajmohan Mani USB4_SB_OPCODE_NVM_READ = 0x52524641, /* "AFRR" */ 29*d0f1e0c2SMika Westerberg USB4_SB_OPCODE_READ_LANE_MARGINING_CAP = 0x50434452, /* "RDCP" */ 30*d0f1e0c2SMika Westerberg USB4_SB_OPCODE_RUN_HW_LANE_MARGINING = 0x474d4852, /* "RHMG" */ 31*d0f1e0c2SMika Westerberg USB4_SB_OPCODE_RUN_SW_LANE_MARGINING = 0x474d5352, /* "RSMG" */ 32*d0f1e0c2SMika Westerberg USB4_SB_OPCODE_READ_SW_MARGIN_ERR = 0x57534452, /* "RDSW" */ 3302d12855SRajmohan Mani }; 3402d12855SRajmohan Mani 3502d12855SRajmohan Mani #define USB4_SB_METADATA 0x09 3602d12855SRajmohan Mani #define USB4_SB_METADATA_NVM_AUTH_WRITE_MASK GENMASK(5, 0) 3702d12855SRajmohan Mani #define USB4_SB_DATA 0x12 3802d12855SRajmohan Mani 39*d0f1e0c2SMika Westerberg /* USB4_SB_OPCODE_READ_LANE_MARGINING_CAP */ 40*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_0_MODES_HW BIT(0) 41*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_0_MODES_SW BIT(1) 42*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_0_2_LANES BIT(2) 43*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_0_VOLTAGE_INDP_MASK GENMASK(4, 3) 44*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_0_VOLTAGE_INDP_SHIFT 3 45*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_0_VOLTAGE_MIN 0x0 46*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_0_VOLTAGE_HL 0x1 47*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_0_VOLTAGE_BOTH 0x2 48*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_0_TIME BIT(5) 49*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_0_VOLTAGE_STEPS_MASK GENMASK(12, 6) 50*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_0_VOLTAGE_STEPS_SHIFT 6 51*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_0_MAX_VOLTAGE_OFFSET_MASK GENMASK(18, 13) 52*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_0_MAX_VOLTAGE_OFFSET_SHIFT 13 53*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_TIME_DESTR BIT(8) 54*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_TIME_INDP_MASK GENMASK(10, 9) 55*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_TIME_INDP_SHIFT 9 56*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_TIME_MIN 0x0 57*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_TIME_LR 0x1 58*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_TIME_BOTH 0x2 59*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_TIME_STEPS_MASK GENMASK(15, 11) 60*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_TIME_STEPS_SHIFT 11 61*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_TIME_OFFSET_MASK GENMASK(20, 16) 62*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_TIME_OFFSET_SHIFT 16 63*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_MIN_BER_MASK GENMASK(25, 21) 64*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_MIN_BER_SHIFT 21 65*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_MAX_BER_MASK GENMASK(30, 26) 66*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_MAX_BER_SHIFT 26 67*d0f1e0c2SMika Westerberg #define USB4_MARGIN_CAP_1_MAX_BER_SHIFT 26 68*d0f1e0c2SMika Westerberg 69*d0f1e0c2SMika Westerberg /* USB4_SB_OPCODE_RUN_HW_LANE_MARGINING */ 70*d0f1e0c2SMika Westerberg #define USB4_MARGIN_HW_TIME BIT(3) 71*d0f1e0c2SMika Westerberg #define USB4_MARGIN_HW_RH BIT(4) 72*d0f1e0c2SMika Westerberg #define USB4_MARGIN_HW_BER_MASK GENMASK(9, 5) 73*d0f1e0c2SMika Westerberg #define USB4_MARGIN_HW_BER_SHIFT 5 74*d0f1e0c2SMika Westerberg 75*d0f1e0c2SMika Westerberg /* Applicable to all margin values */ 76*d0f1e0c2SMika Westerberg #define USB4_MARGIN_HW_RES_1_MARGIN_MASK GENMASK(6, 0) 77*d0f1e0c2SMika Westerberg #define USB4_MARGIN_HW_RES_1_EXCEEDS BIT(7) 78*d0f1e0c2SMika Westerberg /* Different lane margin shifts */ 79*d0f1e0c2SMika Westerberg #define USB4_MARGIN_HW_RES_1_L0_LL_MARGIN_SHIFT 8 80*d0f1e0c2SMika Westerberg #define USB4_MARGIN_HW_RES_1_L1_RH_MARGIN_SHIFT 16 81*d0f1e0c2SMika Westerberg #define USB4_MARGIN_HW_RES_1_L1_LL_MARGIN_SHIFT 24 82*d0f1e0c2SMika Westerberg 83*d0f1e0c2SMika Westerberg /* USB4_SB_OPCODE_RUN_SW_LANE_MARGINING */ 84*d0f1e0c2SMika Westerberg #define USB4_MARGIN_SW_TIME BIT(3) 85*d0f1e0c2SMika Westerberg #define USB4_MARGIN_SW_RH BIT(4) 86*d0f1e0c2SMika Westerberg #define USB4_MARGIN_SW_COUNTER_MASK GENMASK(14, 13) 87*d0f1e0c2SMika Westerberg #define USB4_MARGIN_SW_COUNTER_SHIFT 13 88*d0f1e0c2SMika Westerberg #define USB4_MARGIN_SW_COUNTER_NOP 0x0 89*d0f1e0c2SMika Westerberg #define USB4_MARGIN_SW_COUNTER_CLEAR 0x1 90*d0f1e0c2SMika Westerberg #define USB4_MARGIN_SW_COUNTER_START 0x2 91*d0f1e0c2SMika Westerberg #define USB4_MARGIN_SW_COUNTER_STOP 0x3 92*d0f1e0c2SMika Westerberg 9302d12855SRajmohan Mani #endif 94