1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Thunderbolt driver - quirks 4 * 5 * Copyright (c) 2020 Mario Limonciello <mario.limonciello@dell.com> 6 */ 7 8 #include "tb.h" 9 10 static void quirk_force_power_link(struct tb_switch *sw) 11 { 12 sw->quirks |= QUIRK_FORCE_POWER_LINK_CONTROLLER; 13 tb_sw_dbg(sw, "forcing power to link controller\n"); 14 } 15 16 static void quirk_dp_credit_allocation(struct tb_switch *sw) 17 { 18 if (sw->credit_allocation && sw->min_dp_main_credits == 56) { 19 sw->min_dp_main_credits = 18; 20 tb_sw_dbg(sw, "quirked DP main: %u\n", sw->min_dp_main_credits); 21 } 22 } 23 24 static void quirk_clx_disable(struct tb_switch *sw) 25 { 26 sw->quirks |= QUIRK_NO_CLX; 27 tb_sw_dbg(sw, "disabling CL states\n"); 28 } 29 30 static void quirk_usb3_maximum_bandwidth(struct tb_switch *sw) 31 { 32 struct tb_port *port; 33 34 if (tb_switch_is_icm(sw)) 35 return; 36 37 tb_switch_for_each_port(sw, port) { 38 if (!tb_port_is_usb3_down(port)) 39 continue; 40 port->max_bw = 16376; 41 tb_port_dbg(port, "USB3 maximum bandwidth limited to %u Mb/s\n", 42 port->max_bw); 43 } 44 } 45 46 struct tb_quirk { 47 u16 hw_vendor_id; 48 u16 hw_device_id; 49 u16 vendor; 50 u16 device; 51 void (*hook)(struct tb_switch *sw); 52 }; 53 54 static const struct tb_quirk tb_quirks[] = { 55 /* Dell WD19TB supports self-authentication on unplug */ 56 { 0x0000, 0x0000, 0x00d4, 0xb070, quirk_force_power_link }, 57 { 0x0000, 0x0000, 0x00d4, 0xb071, quirk_force_power_link }, 58 /* 59 * Intel Goshen Ridge NVM 27 and before report wrong number of 60 * DP buffers. 61 */ 62 { 0x8087, 0x0b26, 0x0000, 0x0000, quirk_dp_credit_allocation }, 63 /* 64 * Limit the maximum USB3 bandwidth for the following Intel USB4 65 * host routers due to a hardware issue. 66 */ 67 { 0x8087, PCI_DEVICE_ID_INTEL_ADL_NHI0, 0x0000, 0x0000, 68 quirk_usb3_maximum_bandwidth }, 69 { 0x8087, PCI_DEVICE_ID_INTEL_ADL_NHI1, 0x0000, 0x0000, 70 quirk_usb3_maximum_bandwidth }, 71 { 0x8087, PCI_DEVICE_ID_INTEL_RPL_NHI0, 0x0000, 0x0000, 72 quirk_usb3_maximum_bandwidth }, 73 { 0x8087, PCI_DEVICE_ID_INTEL_RPL_NHI1, 0x0000, 0x0000, 74 quirk_usb3_maximum_bandwidth }, 75 { 0x8087, PCI_DEVICE_ID_INTEL_MTL_M_NHI0, 0x0000, 0x0000, 76 quirk_usb3_maximum_bandwidth }, 77 { 0x8087, PCI_DEVICE_ID_INTEL_MTL_P_NHI0, 0x0000, 0x0000, 78 quirk_usb3_maximum_bandwidth }, 79 { 0x8087, PCI_DEVICE_ID_INTEL_MTL_P_NHI1, 0x0000, 0x0000, 80 quirk_usb3_maximum_bandwidth }, 81 { 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI, 0x0000, 0x0000, 82 quirk_usb3_maximum_bandwidth }, 83 { 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI, 0x0000, 0x0000, 84 quirk_usb3_maximum_bandwidth }, 85 { 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_80G_BRIDGE, 0x0000, 0x0000, 86 quirk_usb3_maximum_bandwidth }, 87 { 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_40G_BRIDGE, 0x0000, 0x0000, 88 quirk_usb3_maximum_bandwidth }, 89 /* 90 * CLx is not supported on AMD USB4 Yellow Carp and Pink Sardine platforms. 91 */ 92 { 0x0438, 0x0208, 0x0000, 0x0000, quirk_clx_disable }, 93 { 0x0438, 0x0209, 0x0000, 0x0000, quirk_clx_disable }, 94 { 0x0438, 0x020a, 0x0000, 0x0000, quirk_clx_disable }, 95 { 0x0438, 0x020b, 0x0000, 0x0000, quirk_clx_disable }, 96 }; 97 98 /** 99 * tb_check_quirks() - Check for quirks to apply 100 * @sw: Thunderbolt switch 101 * 102 * Apply any quirks for the Thunderbolt controller. 103 */ 104 void tb_check_quirks(struct tb_switch *sw) 105 { 106 int i; 107 108 for (i = 0; i < ARRAY_SIZE(tb_quirks); i++) { 109 const struct tb_quirk *q = &tb_quirks[i]; 110 111 if (q->hw_vendor_id && q->hw_vendor_id != sw->config.vendor_id) 112 continue; 113 if (q->hw_device_id && q->hw_device_id != sw->config.device_id) 114 continue; 115 if (q->vendor && q->vendor != sw->vendor) 116 continue; 117 if (q->device && q->device != sw->device) 118 continue; 119 120 tb_sw_dbg(sw, "running %ps\n", q->hook); 121 q->hook(sw); 122 } 123 } 124