1 /* 2 * Thunderbolt driver - NHI registers 3 * 4 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> 5 */ 6 7 #ifndef NHI_REGS_H_ 8 #define NHI_REGS_H_ 9 10 #include <linux/types.h> 11 12 enum ring_flags { 13 RING_FLAG_ISOCH_ENABLE = 1 << 27, /* TX only? */ 14 RING_FLAG_E2E_FLOW_CONTROL = 1 << 28, 15 RING_FLAG_PCI_NO_SNOOP = 1 << 29, 16 RING_FLAG_RAW = 1 << 30, /* ignore EOF/SOF mask, include checksum */ 17 RING_FLAG_ENABLE = 1 << 31, 18 }; 19 20 /** 21 * struct ring_desc - TX/RX ring entry 22 * 23 * For TX set length/eof/sof. 24 * For RX length/eof/sof are set by the NHI. 25 */ 26 struct ring_desc { 27 u64 phys; 28 u32 length:12; 29 u32 eof:4; 30 u32 sof:4; 31 enum ring_desc_flags flags:12; 32 u32 time; /* write zero */ 33 } __packed; 34 35 /* NHI registers in bar 0 */ 36 37 /* 38 * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT) 39 * 00: physical pointer to an array of struct ring_desc 40 * 08: ring tail (set by NHI) 41 * 10: ring head (index of first non posted descriptor) 42 * 12: descriptor count 43 */ 44 #define REG_TX_RING_BASE 0x00000 45 46 /* 47 * 16 bytes per entry, one entry for every hop (REG_HOP_COUNT) 48 * 00: physical pointer to an array of struct ring_desc 49 * 08: ring head (index of first not posted descriptor) 50 * 10: ring tail (set by NHI) 51 * 12: descriptor count 52 * 14: max frame sizes (anything larger than 0x100 has no effect) 53 */ 54 #define REG_RX_RING_BASE 0x08000 55 56 /* 57 * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT) 58 * 00: enum_ring_flags 59 * 04: isoch time stamp ?? (write 0) 60 * ..: unknown 61 */ 62 #define REG_TX_OPTIONS_BASE 0x19800 63 64 /* 65 * 32 bytes per entry, one entry for every hop (REG_HOP_COUNT) 66 * 00: enum ring_flags 67 * If RING_FLAG_E2E_FLOW_CONTROL is set then bits 13-23 must be set to 68 * the corresponding TX hop id. 69 * 04: EOF/SOF mask (ignored for RING_FLAG_RAW rings) 70 * ..: unknown 71 */ 72 #define REG_RX_OPTIONS_BASE 0x29800 73 #define REG_RX_OPTIONS_E2E_HOP_MASK GENMASK(22, 12) 74 #define REG_RX_OPTIONS_E2E_HOP_SHIFT 12 75 76 /* 77 * three bitfields: tx, rx, rx overflow 78 * Every bitfield contains one bit for every hop (REG_HOP_COUNT). Registers are 79 * cleared on read. New interrupts are fired only after ALL registers have been 80 * read (even those containing only disabled rings). 81 */ 82 #define REG_RING_NOTIFY_BASE 0x37800 83 #define RING_NOTIFY_REG_COUNT(nhi) ((31 + 3 * nhi->hop_count) / 32) 84 85 /* 86 * two bitfields: rx, tx 87 * Both bitfields contains one bit for every hop (REG_HOP_COUNT). To 88 * enable/disable interrupts set/clear the corresponding bits. 89 */ 90 #define REG_RING_INTERRUPT_BASE 0x38200 91 #define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32) 92 93 #define REG_INT_THROTTLING_RATE 0x38c00 94 95 /* Interrupt Vector Allocation */ 96 #define REG_INT_VEC_ALLOC_BASE 0x38c40 97 #define REG_INT_VEC_ALLOC_BITS 4 98 #define REG_INT_VEC_ALLOC_MASK GENMASK(3, 0) 99 #define REG_INT_VEC_ALLOC_REGS (32 / REG_INT_VEC_ALLOC_BITS) 100 101 /* The last 11 bits contain the number of hops supported by the NHI port. */ 102 #define REG_HOP_COUNT 0x39640 103 104 #define REG_DMA_MISC 0x39864 105 #define REG_DMA_MISC_INT_AUTO_CLEAR BIT(2) 106 107 #define REG_INMAIL_DATA 0x39900 108 109 #define REG_INMAIL_CMD 0x39904 110 #define REG_INMAIL_CMD_MASK GENMASK(7, 0) 111 #define REG_INMAIL_ERROR BIT(30) 112 #define REG_INMAIL_OP_REQUEST BIT(31) 113 114 #define REG_OUTMAIL_CMD 0x3990c 115 #define REG_OUTMAIL_CMD_OPMODE_SHIFT 8 116 #define REG_OUTMAIL_CMD_OPMODE_MASK GENMASK(11, 8) 117 118 #define REG_FW_STS 0x39944 119 #define REG_FW_STS_NVM_AUTH_DONE BIT(31) 120 #define REG_FW_STS_CIO_RESET_REQ BIT(30) 121 #define REG_FW_STS_ICM_EN_CPU BIT(2) 122 #define REG_FW_STS_ICM_EN_INVERT BIT(1) 123 #define REG_FW_STS_ICM_EN BIT(0) 124 125 #endif 126