1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Thunderbolt driver - NHI driver 4 * 5 * The NHI (native host interface) is the pci device that allows us to send and 6 * receive frames from the thunderbolt bus. 7 * 8 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> 9 * Copyright (C) 2018, Intel Corporation 10 */ 11 12 #include <linux/pm_runtime.h> 13 #include <linux/slab.h> 14 #include <linux/errno.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/interrupt.h> 18 #include <linux/iommu.h> 19 #include <linux/module.h> 20 #include <linux/delay.h> 21 #include <linux/property.h> 22 #include <linux/string_helpers.h> 23 24 #include "nhi.h" 25 #include "nhi_regs.h" 26 #include "tb.h" 27 28 #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring") 29 30 #define RING_FIRST_USABLE_HOPID 1 31 /* 32 * Used with QUIRK_E2E to specify an unused HopID the Rx credits are 33 * transferred. 34 */ 35 #define RING_E2E_RESERVED_HOPID RING_FIRST_USABLE_HOPID 36 /* 37 * Minimal number of vectors when we use MSI-X. Two for control channel 38 * Rx/Tx and the rest four are for cross domain DMA paths. 39 */ 40 #define MSIX_MIN_VECS 6 41 #define MSIX_MAX_VECS 16 42 43 #define NHI_MAILBOX_TIMEOUT 500 /* ms */ 44 45 /* Host interface quirks */ 46 #define QUIRK_AUTO_CLEAR_INT BIT(0) 47 #define QUIRK_E2E BIT(1) 48 49 static int ring_interrupt_index(struct tb_ring *ring) 50 { 51 int bit = ring->hop; 52 if (!ring->is_tx) 53 bit += ring->nhi->hop_count; 54 return bit; 55 } 56 57 /* 58 * ring_interrupt_active() - activate/deactivate interrupts for a single ring 59 * 60 * ring->nhi->lock must be held. 61 */ 62 static void ring_interrupt_active(struct tb_ring *ring, bool active) 63 { 64 int reg = REG_RING_INTERRUPT_BASE + 65 ring_interrupt_index(ring) / 32 * 4; 66 int bit = ring_interrupt_index(ring) & 31; 67 int mask = 1 << bit; 68 u32 old, new; 69 70 if (ring->irq > 0) { 71 u32 step, shift, ivr, misc; 72 void __iomem *ivr_base; 73 int index; 74 75 if (ring->is_tx) 76 index = ring->hop; 77 else 78 index = ring->hop + ring->nhi->hop_count; 79 80 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT) { 81 /* 82 * Ask the hardware to clear interrupt status 83 * bits automatically since we already know 84 * which interrupt was triggered. 85 */ 86 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); 87 if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) { 88 misc |= REG_DMA_MISC_INT_AUTO_CLEAR; 89 iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); 90 } 91 } 92 93 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE; 94 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; 95 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; 96 ivr = ioread32(ivr_base + step); 97 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift); 98 if (active) 99 ivr |= ring->vector << shift; 100 iowrite32(ivr, ivr_base + step); 101 } 102 103 old = ioread32(ring->nhi->iobase + reg); 104 if (active) 105 new = old | mask; 106 else 107 new = old & ~mask; 108 109 dev_dbg(&ring->nhi->pdev->dev, 110 "%s interrupt at register %#x bit %d (%#x -> %#x)\n", 111 active ? "enabling" : "disabling", reg, bit, old, new); 112 113 if (new == old) 114 dev_WARN(&ring->nhi->pdev->dev, 115 "interrupt for %s %d is already %s\n", 116 RING_TYPE(ring), ring->hop, 117 active ? "enabled" : "disabled"); 118 iowrite32(new, ring->nhi->iobase + reg); 119 } 120 121 /* 122 * nhi_disable_interrupts() - disable interrupts for all rings 123 * 124 * Use only during init and shutdown. 125 */ 126 static void nhi_disable_interrupts(struct tb_nhi *nhi) 127 { 128 int i = 0; 129 /* disable interrupts */ 130 for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++) 131 iowrite32(0, nhi->iobase + REG_RING_INTERRUPT_BASE + 4 * i); 132 133 /* clear interrupt status bits */ 134 for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++) 135 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i); 136 } 137 138 /* ring helper methods */ 139 140 static void __iomem *ring_desc_base(struct tb_ring *ring) 141 { 142 void __iomem *io = ring->nhi->iobase; 143 io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE; 144 io += ring->hop * 16; 145 return io; 146 } 147 148 static void __iomem *ring_options_base(struct tb_ring *ring) 149 { 150 void __iomem *io = ring->nhi->iobase; 151 io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE; 152 io += ring->hop * 32; 153 return io; 154 } 155 156 static void ring_iowrite_cons(struct tb_ring *ring, u16 cons) 157 { 158 /* 159 * The other 16-bits in the register is read-only and writes to it 160 * are ignored by the hardware so we can save one ioread32() by 161 * filling the read-only bits with zeroes. 162 */ 163 iowrite32(cons, ring_desc_base(ring) + 8); 164 } 165 166 static void ring_iowrite_prod(struct tb_ring *ring, u16 prod) 167 { 168 /* See ring_iowrite_cons() above for explanation */ 169 iowrite32(prod << 16, ring_desc_base(ring) + 8); 170 } 171 172 static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset) 173 { 174 iowrite32(value, ring_desc_base(ring) + offset); 175 } 176 177 static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset) 178 { 179 iowrite32(value, ring_desc_base(ring) + offset); 180 iowrite32(value >> 32, ring_desc_base(ring) + offset + 4); 181 } 182 183 static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset) 184 { 185 iowrite32(value, ring_options_base(ring) + offset); 186 } 187 188 static bool ring_full(struct tb_ring *ring) 189 { 190 return ((ring->head + 1) % ring->size) == ring->tail; 191 } 192 193 static bool ring_empty(struct tb_ring *ring) 194 { 195 return ring->head == ring->tail; 196 } 197 198 /* 199 * ring_write_descriptors() - post frames from ring->queue to the controller 200 * 201 * ring->lock is held. 202 */ 203 static void ring_write_descriptors(struct tb_ring *ring) 204 { 205 struct ring_frame *frame, *n; 206 struct ring_desc *descriptor; 207 list_for_each_entry_safe(frame, n, &ring->queue, list) { 208 if (ring_full(ring)) 209 break; 210 list_move_tail(&frame->list, &ring->in_flight); 211 descriptor = &ring->descriptors[ring->head]; 212 descriptor->phys = frame->buffer_phy; 213 descriptor->time = 0; 214 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT; 215 if (ring->is_tx) { 216 descriptor->length = frame->size; 217 descriptor->eof = frame->eof; 218 descriptor->sof = frame->sof; 219 } 220 ring->head = (ring->head + 1) % ring->size; 221 if (ring->is_tx) 222 ring_iowrite_prod(ring, ring->head); 223 else 224 ring_iowrite_cons(ring, ring->head); 225 } 226 } 227 228 /* 229 * ring_work() - progress completed frames 230 * 231 * If the ring is shutting down then all frames are marked as canceled and 232 * their callbacks are invoked. 233 * 234 * Otherwise we collect all completed frame from the ring buffer, write new 235 * frame to the ring buffer and invoke the callbacks for the completed frames. 236 */ 237 static void ring_work(struct work_struct *work) 238 { 239 struct tb_ring *ring = container_of(work, typeof(*ring), work); 240 struct ring_frame *frame; 241 bool canceled = false; 242 unsigned long flags; 243 LIST_HEAD(done); 244 245 spin_lock_irqsave(&ring->lock, flags); 246 247 if (!ring->running) { 248 /* Move all frames to done and mark them as canceled. */ 249 list_splice_tail_init(&ring->in_flight, &done); 250 list_splice_tail_init(&ring->queue, &done); 251 canceled = true; 252 goto invoke_callback; 253 } 254 255 while (!ring_empty(ring)) { 256 if (!(ring->descriptors[ring->tail].flags 257 & RING_DESC_COMPLETED)) 258 break; 259 frame = list_first_entry(&ring->in_flight, typeof(*frame), 260 list); 261 list_move_tail(&frame->list, &done); 262 if (!ring->is_tx) { 263 frame->size = ring->descriptors[ring->tail].length; 264 frame->eof = ring->descriptors[ring->tail].eof; 265 frame->sof = ring->descriptors[ring->tail].sof; 266 frame->flags = ring->descriptors[ring->tail].flags; 267 } 268 ring->tail = (ring->tail + 1) % ring->size; 269 } 270 ring_write_descriptors(ring); 271 272 invoke_callback: 273 /* allow callbacks to schedule new work */ 274 spin_unlock_irqrestore(&ring->lock, flags); 275 while (!list_empty(&done)) { 276 frame = list_first_entry(&done, typeof(*frame), list); 277 /* 278 * The callback may reenqueue or delete frame. 279 * Do not hold on to it. 280 */ 281 list_del_init(&frame->list); 282 if (frame->callback) 283 frame->callback(ring, frame, canceled); 284 } 285 } 286 287 int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame) 288 { 289 unsigned long flags; 290 int ret = 0; 291 292 spin_lock_irqsave(&ring->lock, flags); 293 if (ring->running) { 294 list_add_tail(&frame->list, &ring->queue); 295 ring_write_descriptors(ring); 296 } else { 297 ret = -ESHUTDOWN; 298 } 299 spin_unlock_irqrestore(&ring->lock, flags); 300 return ret; 301 } 302 EXPORT_SYMBOL_GPL(__tb_ring_enqueue); 303 304 /** 305 * tb_ring_poll() - Poll one completed frame from the ring 306 * @ring: Ring to poll 307 * 308 * This function can be called when @start_poll callback of the @ring 309 * has been called. It will read one completed frame from the ring and 310 * return it to the caller. Returns %NULL if there is no more completed 311 * frames. 312 */ 313 struct ring_frame *tb_ring_poll(struct tb_ring *ring) 314 { 315 struct ring_frame *frame = NULL; 316 unsigned long flags; 317 318 spin_lock_irqsave(&ring->lock, flags); 319 if (!ring->running) 320 goto unlock; 321 if (ring_empty(ring)) 322 goto unlock; 323 324 if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) { 325 frame = list_first_entry(&ring->in_flight, typeof(*frame), 326 list); 327 list_del_init(&frame->list); 328 329 if (!ring->is_tx) { 330 frame->size = ring->descriptors[ring->tail].length; 331 frame->eof = ring->descriptors[ring->tail].eof; 332 frame->sof = ring->descriptors[ring->tail].sof; 333 frame->flags = ring->descriptors[ring->tail].flags; 334 } 335 336 ring->tail = (ring->tail + 1) % ring->size; 337 } 338 339 unlock: 340 spin_unlock_irqrestore(&ring->lock, flags); 341 return frame; 342 } 343 EXPORT_SYMBOL_GPL(tb_ring_poll); 344 345 static void __ring_interrupt_mask(struct tb_ring *ring, bool mask) 346 { 347 int idx = ring_interrupt_index(ring); 348 int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4; 349 int bit = idx % 32; 350 u32 val; 351 352 val = ioread32(ring->nhi->iobase + reg); 353 if (mask) 354 val &= ~BIT(bit); 355 else 356 val |= BIT(bit); 357 iowrite32(val, ring->nhi->iobase + reg); 358 } 359 360 /* Both @nhi->lock and @ring->lock should be held */ 361 static void __ring_interrupt(struct tb_ring *ring) 362 { 363 if (!ring->running) 364 return; 365 366 if (ring->start_poll) { 367 __ring_interrupt_mask(ring, true); 368 ring->start_poll(ring->poll_data); 369 } else { 370 schedule_work(&ring->work); 371 } 372 } 373 374 /** 375 * tb_ring_poll_complete() - Re-start interrupt for the ring 376 * @ring: Ring to re-start the interrupt 377 * 378 * This will re-start (unmask) the ring interrupt once the user is done 379 * with polling. 380 */ 381 void tb_ring_poll_complete(struct tb_ring *ring) 382 { 383 unsigned long flags; 384 385 spin_lock_irqsave(&ring->nhi->lock, flags); 386 spin_lock(&ring->lock); 387 if (ring->start_poll) 388 __ring_interrupt_mask(ring, false); 389 spin_unlock(&ring->lock); 390 spin_unlock_irqrestore(&ring->nhi->lock, flags); 391 } 392 EXPORT_SYMBOL_GPL(tb_ring_poll_complete); 393 394 static void ring_clear_msix(const struct tb_ring *ring) 395 { 396 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT) 397 return; 398 399 if (ring->is_tx) 400 ioread32(ring->nhi->iobase + REG_RING_NOTIFY_BASE); 401 else 402 ioread32(ring->nhi->iobase + REG_RING_NOTIFY_BASE + 403 4 * (ring->nhi->hop_count / 32)); 404 } 405 406 static irqreturn_t ring_msix(int irq, void *data) 407 { 408 struct tb_ring *ring = data; 409 410 spin_lock(&ring->nhi->lock); 411 ring_clear_msix(ring); 412 spin_lock(&ring->lock); 413 __ring_interrupt(ring); 414 spin_unlock(&ring->lock); 415 spin_unlock(&ring->nhi->lock); 416 417 return IRQ_HANDLED; 418 } 419 420 static int ring_request_msix(struct tb_ring *ring, bool no_suspend) 421 { 422 struct tb_nhi *nhi = ring->nhi; 423 unsigned long irqflags; 424 int ret; 425 426 if (!nhi->pdev->msix_enabled) 427 return 0; 428 429 ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL); 430 if (ret < 0) 431 return ret; 432 433 ring->vector = ret; 434 435 ret = pci_irq_vector(ring->nhi->pdev, ring->vector); 436 if (ret < 0) 437 goto err_ida_remove; 438 439 ring->irq = ret; 440 441 irqflags = no_suspend ? IRQF_NO_SUSPEND : 0; 442 ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring); 443 if (ret) 444 goto err_ida_remove; 445 446 return 0; 447 448 err_ida_remove: 449 ida_simple_remove(&nhi->msix_ida, ring->vector); 450 451 return ret; 452 } 453 454 static void ring_release_msix(struct tb_ring *ring) 455 { 456 if (ring->irq <= 0) 457 return; 458 459 free_irq(ring->irq, ring); 460 ida_simple_remove(&ring->nhi->msix_ida, ring->vector); 461 ring->vector = 0; 462 ring->irq = 0; 463 } 464 465 static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring) 466 { 467 unsigned int start_hop = RING_FIRST_USABLE_HOPID; 468 int ret = 0; 469 470 if (nhi->quirks & QUIRK_E2E) { 471 start_hop = RING_FIRST_USABLE_HOPID + 1; 472 if (ring->flags & RING_FLAG_E2E && !ring->is_tx) { 473 dev_dbg(&nhi->pdev->dev, "quirking E2E TX HopID %u -> %u\n", 474 ring->e2e_tx_hop, RING_E2E_RESERVED_HOPID); 475 ring->e2e_tx_hop = RING_E2E_RESERVED_HOPID; 476 } 477 } 478 479 spin_lock_irq(&nhi->lock); 480 481 if (ring->hop < 0) { 482 unsigned int i; 483 484 /* 485 * Automatically allocate HopID from the non-reserved 486 * range 1 .. hop_count - 1. 487 */ 488 for (i = start_hop; i < nhi->hop_count; i++) { 489 if (ring->is_tx) { 490 if (!nhi->tx_rings[i]) { 491 ring->hop = i; 492 break; 493 } 494 } else { 495 if (!nhi->rx_rings[i]) { 496 ring->hop = i; 497 break; 498 } 499 } 500 } 501 } 502 503 if (ring->hop > 0 && ring->hop < start_hop) { 504 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop); 505 ret = -EINVAL; 506 goto err_unlock; 507 } 508 if (ring->hop < 0 || ring->hop >= nhi->hop_count) { 509 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop); 510 ret = -EINVAL; 511 goto err_unlock; 512 } 513 if (ring->is_tx && nhi->tx_rings[ring->hop]) { 514 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n", 515 ring->hop); 516 ret = -EBUSY; 517 goto err_unlock; 518 } else if (!ring->is_tx && nhi->rx_rings[ring->hop]) { 519 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n", 520 ring->hop); 521 ret = -EBUSY; 522 goto err_unlock; 523 } 524 525 if (ring->is_tx) 526 nhi->tx_rings[ring->hop] = ring; 527 else 528 nhi->rx_rings[ring->hop] = ring; 529 530 err_unlock: 531 spin_unlock_irq(&nhi->lock); 532 533 return ret; 534 } 535 536 static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size, 537 bool transmit, unsigned int flags, 538 int e2e_tx_hop, u16 sof_mask, u16 eof_mask, 539 void (*start_poll)(void *), 540 void *poll_data) 541 { 542 struct tb_ring *ring = NULL; 543 544 dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n", 545 transmit ? "TX" : "RX", hop, size); 546 547 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 548 if (!ring) 549 return NULL; 550 551 spin_lock_init(&ring->lock); 552 INIT_LIST_HEAD(&ring->queue); 553 INIT_LIST_HEAD(&ring->in_flight); 554 INIT_WORK(&ring->work, ring_work); 555 556 ring->nhi = nhi; 557 ring->hop = hop; 558 ring->is_tx = transmit; 559 ring->size = size; 560 ring->flags = flags; 561 ring->e2e_tx_hop = e2e_tx_hop; 562 ring->sof_mask = sof_mask; 563 ring->eof_mask = eof_mask; 564 ring->head = 0; 565 ring->tail = 0; 566 ring->running = false; 567 ring->start_poll = start_poll; 568 ring->poll_data = poll_data; 569 570 ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev, 571 size * sizeof(*ring->descriptors), 572 &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO); 573 if (!ring->descriptors) 574 goto err_free_ring; 575 576 if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND)) 577 goto err_free_descs; 578 579 if (nhi_alloc_hop(nhi, ring)) 580 goto err_release_msix; 581 582 return ring; 583 584 err_release_msix: 585 ring_release_msix(ring); 586 err_free_descs: 587 dma_free_coherent(&ring->nhi->pdev->dev, 588 ring->size * sizeof(*ring->descriptors), 589 ring->descriptors, ring->descriptors_dma); 590 err_free_ring: 591 kfree(ring); 592 593 return NULL; 594 } 595 596 /** 597 * tb_ring_alloc_tx() - Allocate DMA ring for transmit 598 * @nhi: Pointer to the NHI the ring is to be allocated 599 * @hop: HopID (ring) to allocate 600 * @size: Number of entries in the ring 601 * @flags: Flags for the ring 602 */ 603 struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size, 604 unsigned int flags) 605 { 606 return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, 0, NULL, NULL); 607 } 608 EXPORT_SYMBOL_GPL(tb_ring_alloc_tx); 609 610 /** 611 * tb_ring_alloc_rx() - Allocate DMA ring for receive 612 * @nhi: Pointer to the NHI the ring is to be allocated 613 * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation. 614 * @size: Number of entries in the ring 615 * @flags: Flags for the ring 616 * @e2e_tx_hop: Transmit HopID when E2E is enabled in @flags 617 * @sof_mask: Mask of PDF values that start a frame 618 * @eof_mask: Mask of PDF values that end a frame 619 * @start_poll: If not %NULL the ring will call this function when an 620 * interrupt is triggered and masked, instead of callback 621 * in each Rx frame. 622 * @poll_data: Optional data passed to @start_poll 623 */ 624 struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size, 625 unsigned int flags, int e2e_tx_hop, 626 u16 sof_mask, u16 eof_mask, 627 void (*start_poll)(void *), void *poll_data) 628 { 629 return tb_ring_alloc(nhi, hop, size, false, flags, e2e_tx_hop, sof_mask, eof_mask, 630 start_poll, poll_data); 631 } 632 EXPORT_SYMBOL_GPL(tb_ring_alloc_rx); 633 634 /** 635 * tb_ring_start() - enable a ring 636 * @ring: Ring to start 637 * 638 * Must not be invoked in parallel with tb_ring_stop(). 639 */ 640 void tb_ring_start(struct tb_ring *ring) 641 { 642 u16 frame_size; 643 u32 flags; 644 645 spin_lock_irq(&ring->nhi->lock); 646 spin_lock(&ring->lock); 647 if (ring->nhi->going_away) 648 goto err; 649 if (ring->running) { 650 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n"); 651 goto err; 652 } 653 dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n", 654 RING_TYPE(ring), ring->hop); 655 656 if (ring->flags & RING_FLAG_FRAME) { 657 /* Means 4096 */ 658 frame_size = 0; 659 flags = RING_FLAG_ENABLE; 660 } else { 661 frame_size = TB_FRAME_SIZE; 662 flags = RING_FLAG_ENABLE | RING_FLAG_RAW; 663 } 664 665 ring_iowrite64desc(ring, ring->descriptors_dma, 0); 666 if (ring->is_tx) { 667 ring_iowrite32desc(ring, ring->size, 12); 668 ring_iowrite32options(ring, 0, 4); /* time releated ? */ 669 ring_iowrite32options(ring, flags, 0); 670 } else { 671 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask; 672 673 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12); 674 ring_iowrite32options(ring, sof_eof_mask, 4); 675 ring_iowrite32options(ring, flags, 0); 676 } 677 678 /* 679 * Now that the ring valid bit is set we can configure E2E if 680 * enabled for the ring. 681 */ 682 if (ring->flags & RING_FLAG_E2E) { 683 if (!ring->is_tx) { 684 u32 hop; 685 686 hop = ring->e2e_tx_hop << REG_RX_OPTIONS_E2E_HOP_SHIFT; 687 hop &= REG_RX_OPTIONS_E2E_HOP_MASK; 688 flags |= hop; 689 690 dev_dbg(&ring->nhi->pdev->dev, 691 "enabling E2E for %s %d with TX HopID %d\n", 692 RING_TYPE(ring), ring->hop, ring->e2e_tx_hop); 693 } else { 694 dev_dbg(&ring->nhi->pdev->dev, "enabling E2E for %s %d\n", 695 RING_TYPE(ring), ring->hop); 696 } 697 698 flags |= RING_FLAG_E2E_FLOW_CONTROL; 699 ring_iowrite32options(ring, flags, 0); 700 } 701 702 ring_interrupt_active(ring, true); 703 ring->running = true; 704 err: 705 spin_unlock(&ring->lock); 706 spin_unlock_irq(&ring->nhi->lock); 707 } 708 EXPORT_SYMBOL_GPL(tb_ring_start); 709 710 /** 711 * tb_ring_stop() - shutdown a ring 712 * @ring: Ring to stop 713 * 714 * Must not be invoked from a callback. 715 * 716 * This method will disable the ring. Further calls to 717 * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been 718 * called. 719 * 720 * All enqueued frames will be canceled and their callbacks will be executed 721 * with frame->canceled set to true (on the callback thread). This method 722 * returns only after all callback invocations have finished. 723 */ 724 void tb_ring_stop(struct tb_ring *ring) 725 { 726 spin_lock_irq(&ring->nhi->lock); 727 spin_lock(&ring->lock); 728 dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n", 729 RING_TYPE(ring), ring->hop); 730 if (ring->nhi->going_away) 731 goto err; 732 if (!ring->running) { 733 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n", 734 RING_TYPE(ring), ring->hop); 735 goto err; 736 } 737 ring_interrupt_active(ring, false); 738 739 ring_iowrite32options(ring, 0, 0); 740 ring_iowrite64desc(ring, 0, 0); 741 ring_iowrite32desc(ring, 0, 8); 742 ring_iowrite32desc(ring, 0, 12); 743 ring->head = 0; 744 ring->tail = 0; 745 ring->running = false; 746 747 err: 748 spin_unlock(&ring->lock); 749 spin_unlock_irq(&ring->nhi->lock); 750 751 /* 752 * schedule ring->work to invoke callbacks on all remaining frames. 753 */ 754 schedule_work(&ring->work); 755 flush_work(&ring->work); 756 } 757 EXPORT_SYMBOL_GPL(tb_ring_stop); 758 759 /* 760 * tb_ring_free() - free ring 761 * 762 * When this method returns all invocations of ring->callback will have 763 * finished. 764 * 765 * Ring must be stopped. 766 * 767 * Must NOT be called from ring_frame->callback! 768 */ 769 void tb_ring_free(struct tb_ring *ring) 770 { 771 spin_lock_irq(&ring->nhi->lock); 772 /* 773 * Dissociate the ring from the NHI. This also ensures that 774 * nhi_interrupt_work cannot reschedule ring->work. 775 */ 776 if (ring->is_tx) 777 ring->nhi->tx_rings[ring->hop] = NULL; 778 else 779 ring->nhi->rx_rings[ring->hop] = NULL; 780 781 if (ring->running) { 782 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n", 783 RING_TYPE(ring), ring->hop); 784 } 785 spin_unlock_irq(&ring->nhi->lock); 786 787 ring_release_msix(ring); 788 789 dma_free_coherent(&ring->nhi->pdev->dev, 790 ring->size * sizeof(*ring->descriptors), 791 ring->descriptors, ring->descriptors_dma); 792 793 ring->descriptors = NULL; 794 ring->descriptors_dma = 0; 795 796 797 dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring), 798 ring->hop); 799 800 /* 801 * ring->work can no longer be scheduled (it is scheduled only 802 * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it 803 * to finish before freeing the ring. 804 */ 805 flush_work(&ring->work); 806 kfree(ring); 807 } 808 EXPORT_SYMBOL_GPL(tb_ring_free); 809 810 /** 811 * nhi_mailbox_cmd() - Send a command through NHI mailbox 812 * @nhi: Pointer to the NHI structure 813 * @cmd: Command to send 814 * @data: Data to be send with the command 815 * 816 * Sends mailbox command to the firmware running on NHI. Returns %0 in 817 * case of success and negative errno in case of failure. 818 */ 819 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data) 820 { 821 ktime_t timeout; 822 u32 val; 823 824 iowrite32(data, nhi->iobase + REG_INMAIL_DATA); 825 826 val = ioread32(nhi->iobase + REG_INMAIL_CMD); 827 val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR); 828 val |= REG_INMAIL_OP_REQUEST | cmd; 829 iowrite32(val, nhi->iobase + REG_INMAIL_CMD); 830 831 timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT); 832 do { 833 val = ioread32(nhi->iobase + REG_INMAIL_CMD); 834 if (!(val & REG_INMAIL_OP_REQUEST)) 835 break; 836 usleep_range(10, 20); 837 } while (ktime_before(ktime_get(), timeout)); 838 839 if (val & REG_INMAIL_OP_REQUEST) 840 return -ETIMEDOUT; 841 if (val & REG_INMAIL_ERROR) 842 return -EIO; 843 844 return 0; 845 } 846 847 /** 848 * nhi_mailbox_mode() - Return current firmware operation mode 849 * @nhi: Pointer to the NHI structure 850 * 851 * The function reads current firmware operation mode using NHI mailbox 852 * registers and returns it to the caller. 853 */ 854 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi) 855 { 856 u32 val; 857 858 val = ioread32(nhi->iobase + REG_OUTMAIL_CMD); 859 val &= REG_OUTMAIL_CMD_OPMODE_MASK; 860 val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT; 861 862 return (enum nhi_fw_mode)val; 863 } 864 865 static void nhi_interrupt_work(struct work_struct *work) 866 { 867 struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work); 868 int value = 0; /* Suppress uninitialized usage warning. */ 869 int bit; 870 int hop = -1; 871 int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */ 872 struct tb_ring *ring; 873 874 spin_lock_irq(&nhi->lock); 875 876 /* 877 * Starting at REG_RING_NOTIFY_BASE there are three status bitfields 878 * (TX, RX, RX overflow). We iterate over the bits and read a new 879 * dwords as required. The registers are cleared on read. 880 */ 881 for (bit = 0; bit < 3 * nhi->hop_count; bit++) { 882 if (bit % 32 == 0) 883 value = ioread32(nhi->iobase 884 + REG_RING_NOTIFY_BASE 885 + 4 * (bit / 32)); 886 if (++hop == nhi->hop_count) { 887 hop = 0; 888 type++; 889 } 890 if ((value & (1 << (bit % 32))) == 0) 891 continue; 892 if (type == 2) { 893 dev_warn(&nhi->pdev->dev, 894 "RX overflow for ring %d\n", 895 hop); 896 continue; 897 } 898 if (type == 0) 899 ring = nhi->tx_rings[hop]; 900 else 901 ring = nhi->rx_rings[hop]; 902 if (ring == NULL) { 903 dev_warn(&nhi->pdev->dev, 904 "got interrupt for inactive %s ring %d\n", 905 type ? "RX" : "TX", 906 hop); 907 continue; 908 } 909 910 spin_lock(&ring->lock); 911 __ring_interrupt(ring); 912 spin_unlock(&ring->lock); 913 } 914 spin_unlock_irq(&nhi->lock); 915 } 916 917 static irqreturn_t nhi_msi(int irq, void *data) 918 { 919 struct tb_nhi *nhi = data; 920 schedule_work(&nhi->interrupt_work); 921 return IRQ_HANDLED; 922 } 923 924 static int __nhi_suspend_noirq(struct device *dev, bool wakeup) 925 { 926 struct pci_dev *pdev = to_pci_dev(dev); 927 struct tb *tb = pci_get_drvdata(pdev); 928 struct tb_nhi *nhi = tb->nhi; 929 int ret; 930 931 ret = tb_domain_suspend_noirq(tb); 932 if (ret) 933 return ret; 934 935 if (nhi->ops && nhi->ops->suspend_noirq) { 936 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup); 937 if (ret) 938 return ret; 939 } 940 941 return 0; 942 } 943 944 static int nhi_suspend_noirq(struct device *dev) 945 { 946 return __nhi_suspend_noirq(dev, device_may_wakeup(dev)); 947 } 948 949 static int nhi_freeze_noirq(struct device *dev) 950 { 951 struct pci_dev *pdev = to_pci_dev(dev); 952 struct tb *tb = pci_get_drvdata(pdev); 953 954 return tb_domain_freeze_noirq(tb); 955 } 956 957 static int nhi_thaw_noirq(struct device *dev) 958 { 959 struct pci_dev *pdev = to_pci_dev(dev); 960 struct tb *tb = pci_get_drvdata(pdev); 961 962 return tb_domain_thaw_noirq(tb); 963 } 964 965 static bool nhi_wake_supported(struct pci_dev *pdev) 966 { 967 u8 val; 968 969 /* 970 * If power rails are sustainable for wakeup from S4 this 971 * property is set by the BIOS. 972 */ 973 if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val)) 974 return !!val; 975 976 return true; 977 } 978 979 static int nhi_poweroff_noirq(struct device *dev) 980 { 981 struct pci_dev *pdev = to_pci_dev(dev); 982 bool wakeup; 983 984 wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev); 985 return __nhi_suspend_noirq(dev, wakeup); 986 } 987 988 static void nhi_enable_int_throttling(struct tb_nhi *nhi) 989 { 990 /* Throttling is specified in 256ns increments */ 991 u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256); 992 unsigned int i; 993 994 /* 995 * Configure interrupt throttling for all vectors even if we 996 * only use few. 997 */ 998 for (i = 0; i < MSIX_MAX_VECS; i++) { 999 u32 reg = REG_INT_THROTTLING_RATE + i * 4; 1000 iowrite32(throttle, nhi->iobase + reg); 1001 } 1002 } 1003 1004 static int nhi_resume_noirq(struct device *dev) 1005 { 1006 struct pci_dev *pdev = to_pci_dev(dev); 1007 struct tb *tb = pci_get_drvdata(pdev); 1008 struct tb_nhi *nhi = tb->nhi; 1009 int ret; 1010 1011 /* 1012 * Check that the device is still there. It may be that the user 1013 * unplugged last device which causes the host controller to go 1014 * away on PCs. 1015 */ 1016 if (!pci_device_is_present(pdev)) { 1017 nhi->going_away = true; 1018 } else { 1019 if (nhi->ops && nhi->ops->resume_noirq) { 1020 ret = nhi->ops->resume_noirq(nhi); 1021 if (ret) 1022 return ret; 1023 } 1024 nhi_enable_int_throttling(tb->nhi); 1025 } 1026 1027 return tb_domain_resume_noirq(tb); 1028 } 1029 1030 static int nhi_suspend(struct device *dev) 1031 { 1032 struct pci_dev *pdev = to_pci_dev(dev); 1033 struct tb *tb = pci_get_drvdata(pdev); 1034 1035 return tb_domain_suspend(tb); 1036 } 1037 1038 static void nhi_complete(struct device *dev) 1039 { 1040 struct pci_dev *pdev = to_pci_dev(dev); 1041 struct tb *tb = pci_get_drvdata(pdev); 1042 1043 /* 1044 * If we were runtime suspended when system suspend started, 1045 * schedule runtime resume now. It should bring the domain back 1046 * to functional state. 1047 */ 1048 if (pm_runtime_suspended(&pdev->dev)) 1049 pm_runtime_resume(&pdev->dev); 1050 else 1051 tb_domain_complete(tb); 1052 } 1053 1054 static int nhi_runtime_suspend(struct device *dev) 1055 { 1056 struct pci_dev *pdev = to_pci_dev(dev); 1057 struct tb *tb = pci_get_drvdata(pdev); 1058 struct tb_nhi *nhi = tb->nhi; 1059 int ret; 1060 1061 ret = tb_domain_runtime_suspend(tb); 1062 if (ret) 1063 return ret; 1064 1065 if (nhi->ops && nhi->ops->runtime_suspend) { 1066 ret = nhi->ops->runtime_suspend(tb->nhi); 1067 if (ret) 1068 return ret; 1069 } 1070 return 0; 1071 } 1072 1073 static int nhi_runtime_resume(struct device *dev) 1074 { 1075 struct pci_dev *pdev = to_pci_dev(dev); 1076 struct tb *tb = pci_get_drvdata(pdev); 1077 struct tb_nhi *nhi = tb->nhi; 1078 int ret; 1079 1080 if (nhi->ops && nhi->ops->runtime_resume) { 1081 ret = nhi->ops->runtime_resume(nhi); 1082 if (ret) 1083 return ret; 1084 } 1085 1086 nhi_enable_int_throttling(nhi); 1087 return tb_domain_runtime_resume(tb); 1088 } 1089 1090 static void nhi_shutdown(struct tb_nhi *nhi) 1091 { 1092 int i; 1093 1094 dev_dbg(&nhi->pdev->dev, "shutdown\n"); 1095 1096 for (i = 0; i < nhi->hop_count; i++) { 1097 if (nhi->tx_rings[i]) 1098 dev_WARN(&nhi->pdev->dev, 1099 "TX ring %d is still active\n", i); 1100 if (nhi->rx_rings[i]) 1101 dev_WARN(&nhi->pdev->dev, 1102 "RX ring %d is still active\n", i); 1103 } 1104 nhi_disable_interrupts(nhi); 1105 /* 1106 * We have to release the irq before calling flush_work. Otherwise an 1107 * already executing IRQ handler could call schedule_work again. 1108 */ 1109 if (!nhi->pdev->msix_enabled) { 1110 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi); 1111 flush_work(&nhi->interrupt_work); 1112 } 1113 ida_destroy(&nhi->msix_ida); 1114 1115 if (nhi->ops && nhi->ops->shutdown) 1116 nhi->ops->shutdown(nhi); 1117 } 1118 1119 static void nhi_check_quirks(struct tb_nhi *nhi) 1120 { 1121 if (nhi->pdev->vendor == PCI_VENDOR_ID_INTEL) { 1122 /* 1123 * Intel hardware supports auto clear of the interrupt 1124 * status register right after interrupt is being 1125 * issued. 1126 */ 1127 nhi->quirks |= QUIRK_AUTO_CLEAR_INT; 1128 1129 switch (nhi->pdev->device) { 1130 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI: 1131 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI: 1132 /* 1133 * Falcon Ridge controller needs the end-to-end 1134 * flow control workaround to avoid losing Rx 1135 * packets when RING_FLAG_E2E is set. 1136 */ 1137 nhi->quirks |= QUIRK_E2E; 1138 break; 1139 } 1140 } 1141 } 1142 1143 static int nhi_check_iommu_pdev(struct pci_dev *pdev, void *data) 1144 { 1145 if (!pdev->external_facing || 1146 !device_iommu_capable(&pdev->dev, IOMMU_CAP_PRE_BOOT_PROTECTION)) 1147 return 0; 1148 *(bool *)data = true; 1149 return 1; /* Stop walking */ 1150 } 1151 1152 static void nhi_check_iommu(struct tb_nhi *nhi) 1153 { 1154 struct pci_bus *bus = nhi->pdev->bus; 1155 bool port_ok = false; 1156 1157 /* 1158 * Ideally what we'd do here is grab every PCI device that 1159 * represents a tunnelling adapter for this NHI and check their 1160 * status directly, but unfortunately USB4 seems to make it 1161 * obnoxiously difficult to reliably make any correlation. 1162 * 1163 * So for now we'll have to bodge it... Hoping that the system 1164 * is at least sane enough that an adapter is in the same PCI 1165 * segment as its NHI, if we can find *something* on that segment 1166 * which meets the requirements for Kernel DMA Protection, we'll 1167 * take that to imply that firmware is aware and has (hopefully) 1168 * done the right thing in general. We need to know that the PCI 1169 * layer has seen the ExternalFacingPort property which will then 1170 * inform the IOMMU layer to enforce the complete "untrusted DMA" 1171 * flow, but also that the IOMMU driver itself can be trusted not 1172 * to have been subverted by a pre-boot DMA attack. 1173 */ 1174 while (bus->parent) 1175 bus = bus->parent; 1176 1177 pci_walk_bus(bus, nhi_check_iommu_pdev, &port_ok); 1178 1179 nhi->iommu_dma_protection = port_ok; 1180 dev_dbg(&nhi->pdev->dev, "IOMMU DMA protection is %s\n", 1181 str_enabled_disabled(port_ok)); 1182 } 1183 1184 static int nhi_init_msi(struct tb_nhi *nhi) 1185 { 1186 struct pci_dev *pdev = nhi->pdev; 1187 struct device *dev = &pdev->dev; 1188 int res, irq, nvec; 1189 1190 /* In case someone left them on. */ 1191 nhi_disable_interrupts(nhi); 1192 1193 nhi_enable_int_throttling(nhi); 1194 1195 ida_init(&nhi->msix_ida); 1196 1197 /* 1198 * The NHI has 16 MSI-X vectors or a single MSI. We first try to 1199 * get all MSI-X vectors and if we succeed, each ring will have 1200 * one MSI-X. If for some reason that does not work out, we 1201 * fallback to a single MSI. 1202 */ 1203 nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS, 1204 PCI_IRQ_MSIX); 1205 if (nvec < 0) { 1206 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1207 if (nvec < 0) 1208 return nvec; 1209 1210 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work); 1211 1212 irq = pci_irq_vector(nhi->pdev, 0); 1213 if (irq < 0) 1214 return irq; 1215 1216 res = devm_request_irq(&pdev->dev, irq, nhi_msi, 1217 IRQF_NO_SUSPEND, "thunderbolt", nhi); 1218 if (res) 1219 return dev_err_probe(dev, res, "request_irq failed, aborting\n"); 1220 } 1221 1222 return 0; 1223 } 1224 1225 static bool nhi_imr_valid(struct pci_dev *pdev) 1226 { 1227 u8 val; 1228 1229 if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val)) 1230 return !!val; 1231 1232 return true; 1233 } 1234 1235 static struct tb *nhi_select_cm(struct tb_nhi *nhi) 1236 { 1237 struct tb *tb; 1238 1239 /* 1240 * USB4 case is simple. If we got control of any of the 1241 * capabilities, we use software CM. 1242 */ 1243 if (tb_acpi_is_native()) 1244 return tb_probe(nhi); 1245 1246 /* 1247 * Either firmware based CM is running (we did not get control 1248 * from the firmware) or this is pre-USB4 PC so try first 1249 * firmware CM and then fallback to software CM. 1250 */ 1251 tb = icm_probe(nhi); 1252 if (!tb) 1253 tb = tb_probe(nhi); 1254 1255 return tb; 1256 } 1257 1258 static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1259 { 1260 struct device *dev = &pdev->dev; 1261 struct tb_nhi *nhi; 1262 struct tb *tb; 1263 int res; 1264 1265 if (!nhi_imr_valid(pdev)) 1266 return dev_err_probe(dev, -ENODEV, "firmware image not valid, aborting\n"); 1267 1268 res = pcim_enable_device(pdev); 1269 if (res) 1270 return dev_err_probe(dev, res, "cannot enable PCI device, aborting\n"); 1271 1272 res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt"); 1273 if (res) 1274 return dev_err_probe(dev, res, "cannot obtain PCI resources, aborting\n"); 1275 1276 nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL); 1277 if (!nhi) 1278 return -ENOMEM; 1279 1280 nhi->pdev = pdev; 1281 nhi->ops = (const struct tb_nhi_ops *)id->driver_data; 1282 /* cannot fail - table is allocated in pcim_iomap_regions */ 1283 nhi->iobase = pcim_iomap_table(pdev)[0]; 1284 nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff; 1285 dev_dbg(dev, "total paths: %d\n", nhi->hop_count); 1286 1287 nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count, 1288 sizeof(*nhi->tx_rings), GFP_KERNEL); 1289 nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count, 1290 sizeof(*nhi->rx_rings), GFP_KERNEL); 1291 if (!nhi->tx_rings || !nhi->rx_rings) 1292 return -ENOMEM; 1293 1294 nhi_check_quirks(nhi); 1295 nhi_check_iommu(nhi); 1296 1297 res = nhi_init_msi(nhi); 1298 if (res) 1299 return dev_err_probe(dev, res, "cannot enable MSI, aborting\n"); 1300 1301 spin_lock_init(&nhi->lock); 1302 1303 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1304 if (res) 1305 return dev_err_probe(dev, res, "failed to set DMA mask\n"); 1306 1307 pci_set_master(pdev); 1308 1309 if (nhi->ops && nhi->ops->init) { 1310 res = nhi->ops->init(nhi); 1311 if (res) 1312 return res; 1313 } 1314 1315 tb = nhi_select_cm(nhi); 1316 if (!tb) 1317 return dev_err_probe(dev, -ENODEV, 1318 "failed to determine connection manager, aborting\n"); 1319 1320 dev_dbg(dev, "NHI initialized, starting thunderbolt\n"); 1321 1322 res = tb_domain_add(tb); 1323 if (res) { 1324 /* 1325 * At this point the RX/TX rings might already have been 1326 * activated. Do a proper shutdown. 1327 */ 1328 tb_domain_put(tb); 1329 nhi_shutdown(nhi); 1330 return res; 1331 } 1332 pci_set_drvdata(pdev, tb); 1333 1334 device_wakeup_enable(&pdev->dev); 1335 1336 pm_runtime_allow(&pdev->dev); 1337 pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY); 1338 pm_runtime_use_autosuspend(&pdev->dev); 1339 pm_runtime_put_autosuspend(&pdev->dev); 1340 1341 return 0; 1342 } 1343 1344 static void nhi_remove(struct pci_dev *pdev) 1345 { 1346 struct tb *tb = pci_get_drvdata(pdev); 1347 struct tb_nhi *nhi = tb->nhi; 1348 1349 pm_runtime_get_sync(&pdev->dev); 1350 pm_runtime_dont_use_autosuspend(&pdev->dev); 1351 pm_runtime_forbid(&pdev->dev); 1352 1353 tb_domain_remove(tb); 1354 nhi_shutdown(nhi); 1355 } 1356 1357 /* 1358 * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable 1359 * the tunnels asap. A corresponding pci quirk blocks the downstream bridges 1360 * resume_noirq until we are done. 1361 */ 1362 static const struct dev_pm_ops nhi_pm_ops = { 1363 .suspend_noirq = nhi_suspend_noirq, 1364 .resume_noirq = nhi_resume_noirq, 1365 .freeze_noirq = nhi_freeze_noirq, /* 1366 * we just disable hotplug, the 1367 * pci-tunnels stay alive. 1368 */ 1369 .thaw_noirq = nhi_thaw_noirq, 1370 .restore_noirq = nhi_resume_noirq, 1371 .suspend = nhi_suspend, 1372 .poweroff_noirq = nhi_poweroff_noirq, 1373 .poweroff = nhi_suspend, 1374 .complete = nhi_complete, 1375 .runtime_suspend = nhi_runtime_suspend, 1376 .runtime_resume = nhi_runtime_resume, 1377 }; 1378 1379 static struct pci_device_id nhi_ids[] = { 1380 /* 1381 * We have to specify class, the TB bridges use the same device and 1382 * vendor (sub)id on gen 1 and gen 2 controllers. 1383 */ 1384 { 1385 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1386 .vendor = PCI_VENDOR_ID_INTEL, 1387 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 1388 .subvendor = 0x2222, .subdevice = 0x1111, 1389 }, 1390 { 1391 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1392 .vendor = PCI_VENDOR_ID_INTEL, 1393 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 1394 .subvendor = 0x2222, .subdevice = 0x1111, 1395 }, 1396 { 1397 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1398 .vendor = PCI_VENDOR_ID_INTEL, 1399 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI, 1400 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 1401 }, 1402 { 1403 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1404 .vendor = PCI_VENDOR_ID_INTEL, 1405 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI, 1406 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 1407 }, 1408 1409 /* Thunderbolt 3 */ 1410 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) }, 1411 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) }, 1412 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) }, 1413 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) }, 1414 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) }, 1415 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) }, 1416 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) }, 1417 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) }, 1418 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) }, 1419 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) }, 1420 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0), 1421 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1422 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1), 1423 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1424 /* Thunderbolt 4 */ 1425 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0), 1426 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1427 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1), 1428 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1429 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0), 1430 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1431 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1), 1432 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1433 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI0), 1434 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1435 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI1), 1436 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1437 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI0), 1438 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1439 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI1), 1440 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1441 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_M_NHI0), 1442 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1443 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI0), 1444 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1445 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI1), 1446 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1447 1448 /* Any USB4 compliant host */ 1449 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) }, 1450 1451 { 0,} 1452 }; 1453 1454 MODULE_DEVICE_TABLE(pci, nhi_ids); 1455 MODULE_LICENSE("GPL"); 1456 1457 static struct pci_driver nhi_driver = { 1458 .name = "thunderbolt", 1459 .id_table = nhi_ids, 1460 .probe = nhi_probe, 1461 .remove = nhi_remove, 1462 .shutdown = nhi_remove, 1463 .driver.pm = &nhi_pm_ops, 1464 }; 1465 1466 static int __init nhi_init(void) 1467 { 1468 int ret; 1469 1470 ret = tb_domain_init(); 1471 if (ret) 1472 return ret; 1473 ret = pci_register_driver(&nhi_driver); 1474 if (ret) 1475 tb_domain_exit(); 1476 return ret; 1477 } 1478 1479 static void __exit nhi_unload(void) 1480 { 1481 pci_unregister_driver(&nhi_driver); 1482 tb_domain_exit(); 1483 } 1484 1485 rootfs_initcall(nhi_init); 1486 module_exit(nhi_unload); 1487