1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Thunderbolt driver - NHI driver 4 * 5 * The NHI (native host interface) is the pci device that allows us to send and 6 * receive frames from the thunderbolt bus. 7 * 8 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> 9 * Copyright (C) 2018, Intel Corporation 10 */ 11 12 #include <linux/pm_runtime.h> 13 #include <linux/slab.h> 14 #include <linux/errno.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/interrupt.h> 18 #include <linux/iommu.h> 19 #include <linux/module.h> 20 #include <linux/delay.h> 21 #include <linux/property.h> 22 #include <linux/string_helpers.h> 23 24 #include "nhi.h" 25 #include "nhi_regs.h" 26 #include "tb.h" 27 28 #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring") 29 30 #define RING_FIRST_USABLE_HOPID 1 31 /* 32 * Used with QUIRK_E2E to specify an unused HopID the Rx credits are 33 * transferred. 34 */ 35 #define RING_E2E_RESERVED_HOPID RING_FIRST_USABLE_HOPID 36 /* 37 * Minimal number of vectors when we use MSI-X. Two for control channel 38 * Rx/Tx and the rest four are for cross domain DMA paths. 39 */ 40 #define MSIX_MIN_VECS 6 41 #define MSIX_MAX_VECS 16 42 43 #define NHI_MAILBOX_TIMEOUT 500 /* ms */ 44 45 /* Host interface quirks */ 46 #define QUIRK_AUTO_CLEAR_INT BIT(0) 47 #define QUIRK_E2E BIT(1) 48 49 static int ring_interrupt_index(const struct tb_ring *ring) 50 { 51 int bit = ring->hop; 52 if (!ring->is_tx) 53 bit += ring->nhi->hop_count; 54 return bit; 55 } 56 57 static void nhi_mask_interrupt(struct tb_nhi *nhi, int mask, int ring) 58 { 59 if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) 60 return; 61 iowrite32(mask, nhi->iobase + REG_RING_INTERRUPT_MASK_CLEAR_BASE + ring); 62 } 63 64 static void nhi_clear_interrupt(struct tb_nhi *nhi, int ring) 65 { 66 if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) 67 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + ring); 68 else 69 iowrite32(~0, nhi->iobase + REG_RING_INT_CLEAR + ring); 70 } 71 72 /* 73 * ring_interrupt_active() - activate/deactivate interrupts for a single ring 74 * 75 * ring->nhi->lock must be held. 76 */ 77 static void ring_interrupt_active(struct tb_ring *ring, bool active) 78 { 79 int index = ring_interrupt_index(ring) / 32 * 4; 80 int reg = REG_RING_INTERRUPT_BASE + index; 81 int interrupt_bit = ring_interrupt_index(ring) & 31; 82 int mask = 1 << interrupt_bit; 83 u32 old, new; 84 85 if (ring->irq > 0) { 86 u32 step, shift, ivr, misc; 87 void __iomem *ivr_base; 88 int auto_clear_bit; 89 int index; 90 91 if (ring->is_tx) 92 index = ring->hop; 93 else 94 index = ring->hop + ring->nhi->hop_count; 95 96 /* 97 * Intel routers support a bit that isn't part of 98 * the USB4 spec to ask the hardware to clear 99 * interrupt status bits automatically since 100 * we already know which interrupt was triggered. 101 * 102 * Other routers explicitly disable auto-clear 103 * to prevent conditions that may occur where two 104 * MSIX interrupts are simultaneously active and 105 * reading the register clears both of them. 106 */ 107 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); 108 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT) 109 auto_clear_bit = REG_DMA_MISC_INT_AUTO_CLEAR; 110 else 111 auto_clear_bit = REG_DMA_MISC_DISABLE_AUTO_CLEAR; 112 if (!(misc & auto_clear_bit)) 113 iowrite32(misc | auto_clear_bit, 114 ring->nhi->iobase + REG_DMA_MISC); 115 116 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE; 117 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; 118 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; 119 ivr = ioread32(ivr_base + step); 120 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift); 121 if (active) 122 ivr |= ring->vector << shift; 123 iowrite32(ivr, ivr_base + step); 124 } 125 126 old = ioread32(ring->nhi->iobase + reg); 127 if (active) 128 new = old | mask; 129 else 130 new = old & ~mask; 131 132 dev_dbg(&ring->nhi->pdev->dev, 133 "%s interrupt at register %#x bit %d (%#x -> %#x)\n", 134 active ? "enabling" : "disabling", reg, interrupt_bit, old, new); 135 136 if (new == old) 137 dev_WARN(&ring->nhi->pdev->dev, 138 "interrupt for %s %d is already %s\n", 139 RING_TYPE(ring), ring->hop, 140 active ? "enabled" : "disabled"); 141 142 if (active) 143 iowrite32(new, ring->nhi->iobase + reg); 144 else 145 nhi_mask_interrupt(ring->nhi, mask, index); 146 } 147 148 /* 149 * nhi_disable_interrupts() - disable interrupts for all rings 150 * 151 * Use only during init and shutdown. 152 */ 153 static void nhi_disable_interrupts(struct tb_nhi *nhi) 154 { 155 int i = 0; 156 /* disable interrupts */ 157 for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++) 158 nhi_mask_interrupt(nhi, ~0, 4 * i); 159 160 /* clear interrupt status bits */ 161 for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++) 162 nhi_clear_interrupt(nhi, 4 * i); 163 } 164 165 /* ring helper methods */ 166 167 static void __iomem *ring_desc_base(struct tb_ring *ring) 168 { 169 void __iomem *io = ring->nhi->iobase; 170 io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE; 171 io += ring->hop * 16; 172 return io; 173 } 174 175 static void __iomem *ring_options_base(struct tb_ring *ring) 176 { 177 void __iomem *io = ring->nhi->iobase; 178 io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE; 179 io += ring->hop * 32; 180 return io; 181 } 182 183 static void ring_iowrite_cons(struct tb_ring *ring, u16 cons) 184 { 185 /* 186 * The other 16-bits in the register is read-only and writes to it 187 * are ignored by the hardware so we can save one ioread32() by 188 * filling the read-only bits with zeroes. 189 */ 190 iowrite32(cons, ring_desc_base(ring) + 8); 191 } 192 193 static void ring_iowrite_prod(struct tb_ring *ring, u16 prod) 194 { 195 /* See ring_iowrite_cons() above for explanation */ 196 iowrite32(prod << 16, ring_desc_base(ring) + 8); 197 } 198 199 static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset) 200 { 201 iowrite32(value, ring_desc_base(ring) + offset); 202 } 203 204 static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset) 205 { 206 iowrite32(value, ring_desc_base(ring) + offset); 207 iowrite32(value >> 32, ring_desc_base(ring) + offset + 4); 208 } 209 210 static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset) 211 { 212 iowrite32(value, ring_options_base(ring) + offset); 213 } 214 215 static bool ring_full(struct tb_ring *ring) 216 { 217 return ((ring->head + 1) % ring->size) == ring->tail; 218 } 219 220 static bool ring_empty(struct tb_ring *ring) 221 { 222 return ring->head == ring->tail; 223 } 224 225 /* 226 * ring_write_descriptors() - post frames from ring->queue to the controller 227 * 228 * ring->lock is held. 229 */ 230 static void ring_write_descriptors(struct tb_ring *ring) 231 { 232 struct ring_frame *frame, *n; 233 struct ring_desc *descriptor; 234 list_for_each_entry_safe(frame, n, &ring->queue, list) { 235 if (ring_full(ring)) 236 break; 237 list_move_tail(&frame->list, &ring->in_flight); 238 descriptor = &ring->descriptors[ring->head]; 239 descriptor->phys = frame->buffer_phy; 240 descriptor->time = 0; 241 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT; 242 if (ring->is_tx) { 243 descriptor->length = frame->size; 244 descriptor->eof = frame->eof; 245 descriptor->sof = frame->sof; 246 } 247 ring->head = (ring->head + 1) % ring->size; 248 if (ring->is_tx) 249 ring_iowrite_prod(ring, ring->head); 250 else 251 ring_iowrite_cons(ring, ring->head); 252 } 253 } 254 255 /* 256 * ring_work() - progress completed frames 257 * 258 * If the ring is shutting down then all frames are marked as canceled and 259 * their callbacks are invoked. 260 * 261 * Otherwise we collect all completed frame from the ring buffer, write new 262 * frame to the ring buffer and invoke the callbacks for the completed frames. 263 */ 264 static void ring_work(struct work_struct *work) 265 { 266 struct tb_ring *ring = container_of(work, typeof(*ring), work); 267 struct ring_frame *frame; 268 bool canceled = false; 269 unsigned long flags; 270 LIST_HEAD(done); 271 272 spin_lock_irqsave(&ring->lock, flags); 273 274 if (!ring->running) { 275 /* Move all frames to done and mark them as canceled. */ 276 list_splice_tail_init(&ring->in_flight, &done); 277 list_splice_tail_init(&ring->queue, &done); 278 canceled = true; 279 goto invoke_callback; 280 } 281 282 while (!ring_empty(ring)) { 283 if (!(ring->descriptors[ring->tail].flags 284 & RING_DESC_COMPLETED)) 285 break; 286 frame = list_first_entry(&ring->in_flight, typeof(*frame), 287 list); 288 list_move_tail(&frame->list, &done); 289 if (!ring->is_tx) { 290 frame->size = ring->descriptors[ring->tail].length; 291 frame->eof = ring->descriptors[ring->tail].eof; 292 frame->sof = ring->descriptors[ring->tail].sof; 293 frame->flags = ring->descriptors[ring->tail].flags; 294 } 295 ring->tail = (ring->tail + 1) % ring->size; 296 } 297 ring_write_descriptors(ring); 298 299 invoke_callback: 300 /* allow callbacks to schedule new work */ 301 spin_unlock_irqrestore(&ring->lock, flags); 302 while (!list_empty(&done)) { 303 frame = list_first_entry(&done, typeof(*frame), list); 304 /* 305 * The callback may reenqueue or delete frame. 306 * Do not hold on to it. 307 */ 308 list_del_init(&frame->list); 309 if (frame->callback) 310 frame->callback(ring, frame, canceled); 311 } 312 } 313 314 int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame) 315 { 316 unsigned long flags; 317 int ret = 0; 318 319 spin_lock_irqsave(&ring->lock, flags); 320 if (ring->running) { 321 list_add_tail(&frame->list, &ring->queue); 322 ring_write_descriptors(ring); 323 } else { 324 ret = -ESHUTDOWN; 325 } 326 spin_unlock_irqrestore(&ring->lock, flags); 327 return ret; 328 } 329 EXPORT_SYMBOL_GPL(__tb_ring_enqueue); 330 331 /** 332 * tb_ring_poll() - Poll one completed frame from the ring 333 * @ring: Ring to poll 334 * 335 * This function can be called when @start_poll callback of the @ring 336 * has been called. It will read one completed frame from the ring and 337 * return it to the caller. Returns %NULL if there is no more completed 338 * frames. 339 */ 340 struct ring_frame *tb_ring_poll(struct tb_ring *ring) 341 { 342 struct ring_frame *frame = NULL; 343 unsigned long flags; 344 345 spin_lock_irqsave(&ring->lock, flags); 346 if (!ring->running) 347 goto unlock; 348 if (ring_empty(ring)) 349 goto unlock; 350 351 if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) { 352 frame = list_first_entry(&ring->in_flight, typeof(*frame), 353 list); 354 list_del_init(&frame->list); 355 356 if (!ring->is_tx) { 357 frame->size = ring->descriptors[ring->tail].length; 358 frame->eof = ring->descriptors[ring->tail].eof; 359 frame->sof = ring->descriptors[ring->tail].sof; 360 frame->flags = ring->descriptors[ring->tail].flags; 361 } 362 363 ring->tail = (ring->tail + 1) % ring->size; 364 } 365 366 unlock: 367 spin_unlock_irqrestore(&ring->lock, flags); 368 return frame; 369 } 370 EXPORT_SYMBOL_GPL(tb_ring_poll); 371 372 static void __ring_interrupt_mask(struct tb_ring *ring, bool mask) 373 { 374 int idx = ring_interrupt_index(ring); 375 int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4; 376 int bit = idx % 32; 377 u32 val; 378 379 val = ioread32(ring->nhi->iobase + reg); 380 if (mask) 381 val &= ~BIT(bit); 382 else 383 val |= BIT(bit); 384 iowrite32(val, ring->nhi->iobase + reg); 385 } 386 387 /* Both @nhi->lock and @ring->lock should be held */ 388 static void __ring_interrupt(struct tb_ring *ring) 389 { 390 if (!ring->running) 391 return; 392 393 if (ring->start_poll) { 394 __ring_interrupt_mask(ring, true); 395 ring->start_poll(ring->poll_data); 396 } else { 397 schedule_work(&ring->work); 398 } 399 } 400 401 /** 402 * tb_ring_poll_complete() - Re-start interrupt for the ring 403 * @ring: Ring to re-start the interrupt 404 * 405 * This will re-start (unmask) the ring interrupt once the user is done 406 * with polling. 407 */ 408 void tb_ring_poll_complete(struct tb_ring *ring) 409 { 410 unsigned long flags; 411 412 spin_lock_irqsave(&ring->nhi->lock, flags); 413 spin_lock(&ring->lock); 414 if (ring->start_poll) 415 __ring_interrupt_mask(ring, false); 416 spin_unlock(&ring->lock); 417 spin_unlock_irqrestore(&ring->nhi->lock, flags); 418 } 419 EXPORT_SYMBOL_GPL(tb_ring_poll_complete); 420 421 static void ring_clear_msix(const struct tb_ring *ring) 422 { 423 int bit; 424 425 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT) 426 return; 427 428 bit = ring_interrupt_index(ring) & 31; 429 if (ring->is_tx) 430 iowrite32(BIT(bit), ring->nhi->iobase + REG_RING_INT_CLEAR); 431 else 432 iowrite32(BIT(bit), ring->nhi->iobase + REG_RING_INT_CLEAR + 433 4 * (ring->nhi->hop_count / 32)); 434 } 435 436 static irqreturn_t ring_msix(int irq, void *data) 437 { 438 struct tb_ring *ring = data; 439 440 spin_lock(&ring->nhi->lock); 441 ring_clear_msix(ring); 442 spin_lock(&ring->lock); 443 __ring_interrupt(ring); 444 spin_unlock(&ring->lock); 445 spin_unlock(&ring->nhi->lock); 446 447 return IRQ_HANDLED; 448 } 449 450 static int ring_request_msix(struct tb_ring *ring, bool no_suspend) 451 { 452 struct tb_nhi *nhi = ring->nhi; 453 unsigned long irqflags; 454 int ret; 455 456 if (!nhi->pdev->msix_enabled) 457 return 0; 458 459 ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL); 460 if (ret < 0) 461 return ret; 462 463 ring->vector = ret; 464 465 ret = pci_irq_vector(ring->nhi->pdev, ring->vector); 466 if (ret < 0) 467 goto err_ida_remove; 468 469 ring->irq = ret; 470 471 irqflags = no_suspend ? IRQF_NO_SUSPEND : 0; 472 ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring); 473 if (ret) 474 goto err_ida_remove; 475 476 return 0; 477 478 err_ida_remove: 479 ida_simple_remove(&nhi->msix_ida, ring->vector); 480 481 return ret; 482 } 483 484 static void ring_release_msix(struct tb_ring *ring) 485 { 486 if (ring->irq <= 0) 487 return; 488 489 free_irq(ring->irq, ring); 490 ida_simple_remove(&ring->nhi->msix_ida, ring->vector); 491 ring->vector = 0; 492 ring->irq = 0; 493 } 494 495 static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring) 496 { 497 unsigned int start_hop = RING_FIRST_USABLE_HOPID; 498 int ret = 0; 499 500 if (nhi->quirks & QUIRK_E2E) { 501 start_hop = RING_FIRST_USABLE_HOPID + 1; 502 if (ring->flags & RING_FLAG_E2E && !ring->is_tx) { 503 dev_dbg(&nhi->pdev->dev, "quirking E2E TX HopID %u -> %u\n", 504 ring->e2e_tx_hop, RING_E2E_RESERVED_HOPID); 505 ring->e2e_tx_hop = RING_E2E_RESERVED_HOPID; 506 } 507 } 508 509 spin_lock_irq(&nhi->lock); 510 511 if (ring->hop < 0) { 512 unsigned int i; 513 514 /* 515 * Automatically allocate HopID from the non-reserved 516 * range 1 .. hop_count - 1. 517 */ 518 for (i = start_hop; i < nhi->hop_count; i++) { 519 if (ring->is_tx) { 520 if (!nhi->tx_rings[i]) { 521 ring->hop = i; 522 break; 523 } 524 } else { 525 if (!nhi->rx_rings[i]) { 526 ring->hop = i; 527 break; 528 } 529 } 530 } 531 } 532 533 if (ring->hop > 0 && ring->hop < start_hop) { 534 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop); 535 ret = -EINVAL; 536 goto err_unlock; 537 } 538 if (ring->hop < 0 || ring->hop >= nhi->hop_count) { 539 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop); 540 ret = -EINVAL; 541 goto err_unlock; 542 } 543 if (ring->is_tx && nhi->tx_rings[ring->hop]) { 544 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n", 545 ring->hop); 546 ret = -EBUSY; 547 goto err_unlock; 548 } 549 if (!ring->is_tx && nhi->rx_rings[ring->hop]) { 550 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n", 551 ring->hop); 552 ret = -EBUSY; 553 goto err_unlock; 554 } 555 556 if (ring->is_tx) 557 nhi->tx_rings[ring->hop] = ring; 558 else 559 nhi->rx_rings[ring->hop] = ring; 560 561 err_unlock: 562 spin_unlock_irq(&nhi->lock); 563 564 return ret; 565 } 566 567 static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size, 568 bool transmit, unsigned int flags, 569 int e2e_tx_hop, u16 sof_mask, u16 eof_mask, 570 void (*start_poll)(void *), 571 void *poll_data) 572 { 573 struct tb_ring *ring = NULL; 574 575 dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n", 576 transmit ? "TX" : "RX", hop, size); 577 578 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 579 if (!ring) 580 return NULL; 581 582 spin_lock_init(&ring->lock); 583 INIT_LIST_HEAD(&ring->queue); 584 INIT_LIST_HEAD(&ring->in_flight); 585 INIT_WORK(&ring->work, ring_work); 586 587 ring->nhi = nhi; 588 ring->hop = hop; 589 ring->is_tx = transmit; 590 ring->size = size; 591 ring->flags = flags; 592 ring->e2e_tx_hop = e2e_tx_hop; 593 ring->sof_mask = sof_mask; 594 ring->eof_mask = eof_mask; 595 ring->head = 0; 596 ring->tail = 0; 597 ring->running = false; 598 ring->start_poll = start_poll; 599 ring->poll_data = poll_data; 600 601 ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev, 602 size * sizeof(*ring->descriptors), 603 &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO); 604 if (!ring->descriptors) 605 goto err_free_ring; 606 607 if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND)) 608 goto err_free_descs; 609 610 if (nhi_alloc_hop(nhi, ring)) 611 goto err_release_msix; 612 613 return ring; 614 615 err_release_msix: 616 ring_release_msix(ring); 617 err_free_descs: 618 dma_free_coherent(&ring->nhi->pdev->dev, 619 ring->size * sizeof(*ring->descriptors), 620 ring->descriptors, ring->descriptors_dma); 621 err_free_ring: 622 kfree(ring); 623 624 return NULL; 625 } 626 627 /** 628 * tb_ring_alloc_tx() - Allocate DMA ring for transmit 629 * @nhi: Pointer to the NHI the ring is to be allocated 630 * @hop: HopID (ring) to allocate 631 * @size: Number of entries in the ring 632 * @flags: Flags for the ring 633 */ 634 struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size, 635 unsigned int flags) 636 { 637 return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, 0, NULL, NULL); 638 } 639 EXPORT_SYMBOL_GPL(tb_ring_alloc_tx); 640 641 /** 642 * tb_ring_alloc_rx() - Allocate DMA ring for receive 643 * @nhi: Pointer to the NHI the ring is to be allocated 644 * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation. 645 * @size: Number of entries in the ring 646 * @flags: Flags for the ring 647 * @e2e_tx_hop: Transmit HopID when E2E is enabled in @flags 648 * @sof_mask: Mask of PDF values that start a frame 649 * @eof_mask: Mask of PDF values that end a frame 650 * @start_poll: If not %NULL the ring will call this function when an 651 * interrupt is triggered and masked, instead of callback 652 * in each Rx frame. 653 * @poll_data: Optional data passed to @start_poll 654 */ 655 struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size, 656 unsigned int flags, int e2e_tx_hop, 657 u16 sof_mask, u16 eof_mask, 658 void (*start_poll)(void *), void *poll_data) 659 { 660 return tb_ring_alloc(nhi, hop, size, false, flags, e2e_tx_hop, sof_mask, eof_mask, 661 start_poll, poll_data); 662 } 663 EXPORT_SYMBOL_GPL(tb_ring_alloc_rx); 664 665 /** 666 * tb_ring_start() - enable a ring 667 * @ring: Ring to start 668 * 669 * Must not be invoked in parallel with tb_ring_stop(). 670 */ 671 void tb_ring_start(struct tb_ring *ring) 672 { 673 u16 frame_size; 674 u32 flags; 675 676 spin_lock_irq(&ring->nhi->lock); 677 spin_lock(&ring->lock); 678 if (ring->nhi->going_away) 679 goto err; 680 if (ring->running) { 681 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n"); 682 goto err; 683 } 684 dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n", 685 RING_TYPE(ring), ring->hop); 686 687 if (ring->flags & RING_FLAG_FRAME) { 688 /* Means 4096 */ 689 frame_size = 0; 690 flags = RING_FLAG_ENABLE; 691 } else { 692 frame_size = TB_FRAME_SIZE; 693 flags = RING_FLAG_ENABLE | RING_FLAG_RAW; 694 } 695 696 ring_iowrite64desc(ring, ring->descriptors_dma, 0); 697 if (ring->is_tx) { 698 ring_iowrite32desc(ring, ring->size, 12); 699 ring_iowrite32options(ring, 0, 4); /* time releated ? */ 700 ring_iowrite32options(ring, flags, 0); 701 } else { 702 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask; 703 704 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12); 705 ring_iowrite32options(ring, sof_eof_mask, 4); 706 ring_iowrite32options(ring, flags, 0); 707 } 708 709 /* 710 * Now that the ring valid bit is set we can configure E2E if 711 * enabled for the ring. 712 */ 713 if (ring->flags & RING_FLAG_E2E) { 714 if (!ring->is_tx) { 715 u32 hop; 716 717 hop = ring->e2e_tx_hop << REG_RX_OPTIONS_E2E_HOP_SHIFT; 718 hop &= REG_RX_OPTIONS_E2E_HOP_MASK; 719 flags |= hop; 720 721 dev_dbg(&ring->nhi->pdev->dev, 722 "enabling E2E for %s %d with TX HopID %d\n", 723 RING_TYPE(ring), ring->hop, ring->e2e_tx_hop); 724 } else { 725 dev_dbg(&ring->nhi->pdev->dev, "enabling E2E for %s %d\n", 726 RING_TYPE(ring), ring->hop); 727 } 728 729 flags |= RING_FLAG_E2E_FLOW_CONTROL; 730 ring_iowrite32options(ring, flags, 0); 731 } 732 733 ring_interrupt_active(ring, true); 734 ring->running = true; 735 err: 736 spin_unlock(&ring->lock); 737 spin_unlock_irq(&ring->nhi->lock); 738 } 739 EXPORT_SYMBOL_GPL(tb_ring_start); 740 741 /** 742 * tb_ring_stop() - shutdown a ring 743 * @ring: Ring to stop 744 * 745 * Must not be invoked from a callback. 746 * 747 * This method will disable the ring. Further calls to 748 * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been 749 * called. 750 * 751 * All enqueued frames will be canceled and their callbacks will be executed 752 * with frame->canceled set to true (on the callback thread). This method 753 * returns only after all callback invocations have finished. 754 */ 755 void tb_ring_stop(struct tb_ring *ring) 756 { 757 spin_lock_irq(&ring->nhi->lock); 758 spin_lock(&ring->lock); 759 dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n", 760 RING_TYPE(ring), ring->hop); 761 if (ring->nhi->going_away) 762 goto err; 763 if (!ring->running) { 764 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n", 765 RING_TYPE(ring), ring->hop); 766 goto err; 767 } 768 ring_interrupt_active(ring, false); 769 770 ring_iowrite32options(ring, 0, 0); 771 ring_iowrite64desc(ring, 0, 0); 772 ring_iowrite32desc(ring, 0, 8); 773 ring_iowrite32desc(ring, 0, 12); 774 ring->head = 0; 775 ring->tail = 0; 776 ring->running = false; 777 778 err: 779 spin_unlock(&ring->lock); 780 spin_unlock_irq(&ring->nhi->lock); 781 782 /* 783 * schedule ring->work to invoke callbacks on all remaining frames. 784 */ 785 schedule_work(&ring->work); 786 flush_work(&ring->work); 787 } 788 EXPORT_SYMBOL_GPL(tb_ring_stop); 789 790 /* 791 * tb_ring_free() - free ring 792 * 793 * When this method returns all invocations of ring->callback will have 794 * finished. 795 * 796 * Ring must be stopped. 797 * 798 * Must NOT be called from ring_frame->callback! 799 */ 800 void tb_ring_free(struct tb_ring *ring) 801 { 802 spin_lock_irq(&ring->nhi->lock); 803 /* 804 * Dissociate the ring from the NHI. This also ensures that 805 * nhi_interrupt_work cannot reschedule ring->work. 806 */ 807 if (ring->is_tx) 808 ring->nhi->tx_rings[ring->hop] = NULL; 809 else 810 ring->nhi->rx_rings[ring->hop] = NULL; 811 812 if (ring->running) { 813 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n", 814 RING_TYPE(ring), ring->hop); 815 } 816 spin_unlock_irq(&ring->nhi->lock); 817 818 ring_release_msix(ring); 819 820 dma_free_coherent(&ring->nhi->pdev->dev, 821 ring->size * sizeof(*ring->descriptors), 822 ring->descriptors, ring->descriptors_dma); 823 824 ring->descriptors = NULL; 825 ring->descriptors_dma = 0; 826 827 828 dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring), 829 ring->hop); 830 831 /* 832 * ring->work can no longer be scheduled (it is scheduled only 833 * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it 834 * to finish before freeing the ring. 835 */ 836 flush_work(&ring->work); 837 kfree(ring); 838 } 839 EXPORT_SYMBOL_GPL(tb_ring_free); 840 841 /** 842 * nhi_mailbox_cmd() - Send a command through NHI mailbox 843 * @nhi: Pointer to the NHI structure 844 * @cmd: Command to send 845 * @data: Data to be send with the command 846 * 847 * Sends mailbox command to the firmware running on NHI. Returns %0 in 848 * case of success and negative errno in case of failure. 849 */ 850 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data) 851 { 852 ktime_t timeout; 853 u32 val; 854 855 iowrite32(data, nhi->iobase + REG_INMAIL_DATA); 856 857 val = ioread32(nhi->iobase + REG_INMAIL_CMD); 858 val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR); 859 val |= REG_INMAIL_OP_REQUEST | cmd; 860 iowrite32(val, nhi->iobase + REG_INMAIL_CMD); 861 862 timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT); 863 do { 864 val = ioread32(nhi->iobase + REG_INMAIL_CMD); 865 if (!(val & REG_INMAIL_OP_REQUEST)) 866 break; 867 usleep_range(10, 20); 868 } while (ktime_before(ktime_get(), timeout)); 869 870 if (val & REG_INMAIL_OP_REQUEST) 871 return -ETIMEDOUT; 872 if (val & REG_INMAIL_ERROR) 873 return -EIO; 874 875 return 0; 876 } 877 878 /** 879 * nhi_mailbox_mode() - Return current firmware operation mode 880 * @nhi: Pointer to the NHI structure 881 * 882 * The function reads current firmware operation mode using NHI mailbox 883 * registers and returns it to the caller. 884 */ 885 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi) 886 { 887 u32 val; 888 889 val = ioread32(nhi->iobase + REG_OUTMAIL_CMD); 890 val &= REG_OUTMAIL_CMD_OPMODE_MASK; 891 val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT; 892 893 return (enum nhi_fw_mode)val; 894 } 895 896 static void nhi_interrupt_work(struct work_struct *work) 897 { 898 struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work); 899 int value = 0; /* Suppress uninitialized usage warning. */ 900 int bit; 901 int hop = -1; 902 int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */ 903 struct tb_ring *ring; 904 905 spin_lock_irq(&nhi->lock); 906 907 /* 908 * Starting at REG_RING_NOTIFY_BASE there are three status bitfields 909 * (TX, RX, RX overflow). We iterate over the bits and read a new 910 * dwords as required. The registers are cleared on read. 911 */ 912 for (bit = 0; bit < 3 * nhi->hop_count; bit++) { 913 if (bit % 32 == 0) 914 value = ioread32(nhi->iobase 915 + REG_RING_NOTIFY_BASE 916 + 4 * (bit / 32)); 917 if (++hop == nhi->hop_count) { 918 hop = 0; 919 type++; 920 } 921 if ((value & (1 << (bit % 32))) == 0) 922 continue; 923 if (type == 2) { 924 dev_warn(&nhi->pdev->dev, 925 "RX overflow for ring %d\n", 926 hop); 927 continue; 928 } 929 if (type == 0) 930 ring = nhi->tx_rings[hop]; 931 else 932 ring = nhi->rx_rings[hop]; 933 if (ring == NULL) { 934 dev_warn(&nhi->pdev->dev, 935 "got interrupt for inactive %s ring %d\n", 936 type ? "RX" : "TX", 937 hop); 938 continue; 939 } 940 941 spin_lock(&ring->lock); 942 __ring_interrupt(ring); 943 spin_unlock(&ring->lock); 944 } 945 spin_unlock_irq(&nhi->lock); 946 } 947 948 static irqreturn_t nhi_msi(int irq, void *data) 949 { 950 struct tb_nhi *nhi = data; 951 schedule_work(&nhi->interrupt_work); 952 return IRQ_HANDLED; 953 } 954 955 static int __nhi_suspend_noirq(struct device *dev, bool wakeup) 956 { 957 struct pci_dev *pdev = to_pci_dev(dev); 958 struct tb *tb = pci_get_drvdata(pdev); 959 struct tb_nhi *nhi = tb->nhi; 960 int ret; 961 962 ret = tb_domain_suspend_noirq(tb); 963 if (ret) 964 return ret; 965 966 if (nhi->ops && nhi->ops->suspend_noirq) { 967 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup); 968 if (ret) 969 return ret; 970 } 971 972 return 0; 973 } 974 975 static int nhi_suspend_noirq(struct device *dev) 976 { 977 return __nhi_suspend_noirq(dev, device_may_wakeup(dev)); 978 } 979 980 static int nhi_freeze_noirq(struct device *dev) 981 { 982 struct pci_dev *pdev = to_pci_dev(dev); 983 struct tb *tb = pci_get_drvdata(pdev); 984 985 return tb_domain_freeze_noirq(tb); 986 } 987 988 static int nhi_thaw_noirq(struct device *dev) 989 { 990 struct pci_dev *pdev = to_pci_dev(dev); 991 struct tb *tb = pci_get_drvdata(pdev); 992 993 return tb_domain_thaw_noirq(tb); 994 } 995 996 static bool nhi_wake_supported(struct pci_dev *pdev) 997 { 998 u8 val; 999 1000 /* 1001 * If power rails are sustainable for wakeup from S4 this 1002 * property is set by the BIOS. 1003 */ 1004 if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val)) 1005 return !!val; 1006 1007 return true; 1008 } 1009 1010 static int nhi_poweroff_noirq(struct device *dev) 1011 { 1012 struct pci_dev *pdev = to_pci_dev(dev); 1013 bool wakeup; 1014 1015 wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev); 1016 return __nhi_suspend_noirq(dev, wakeup); 1017 } 1018 1019 static void nhi_enable_int_throttling(struct tb_nhi *nhi) 1020 { 1021 /* Throttling is specified in 256ns increments */ 1022 u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256); 1023 unsigned int i; 1024 1025 /* 1026 * Configure interrupt throttling for all vectors even if we 1027 * only use few. 1028 */ 1029 for (i = 0; i < MSIX_MAX_VECS; i++) { 1030 u32 reg = REG_INT_THROTTLING_RATE + i * 4; 1031 iowrite32(throttle, nhi->iobase + reg); 1032 } 1033 } 1034 1035 static int nhi_resume_noirq(struct device *dev) 1036 { 1037 struct pci_dev *pdev = to_pci_dev(dev); 1038 struct tb *tb = pci_get_drvdata(pdev); 1039 struct tb_nhi *nhi = tb->nhi; 1040 int ret; 1041 1042 /* 1043 * Check that the device is still there. It may be that the user 1044 * unplugged last device which causes the host controller to go 1045 * away on PCs. 1046 */ 1047 if (!pci_device_is_present(pdev)) { 1048 nhi->going_away = true; 1049 } else { 1050 if (nhi->ops && nhi->ops->resume_noirq) { 1051 ret = nhi->ops->resume_noirq(nhi); 1052 if (ret) 1053 return ret; 1054 } 1055 nhi_enable_int_throttling(tb->nhi); 1056 } 1057 1058 return tb_domain_resume_noirq(tb); 1059 } 1060 1061 static int nhi_suspend(struct device *dev) 1062 { 1063 struct pci_dev *pdev = to_pci_dev(dev); 1064 struct tb *tb = pci_get_drvdata(pdev); 1065 1066 return tb_domain_suspend(tb); 1067 } 1068 1069 static void nhi_complete(struct device *dev) 1070 { 1071 struct pci_dev *pdev = to_pci_dev(dev); 1072 struct tb *tb = pci_get_drvdata(pdev); 1073 1074 /* 1075 * If we were runtime suspended when system suspend started, 1076 * schedule runtime resume now. It should bring the domain back 1077 * to functional state. 1078 */ 1079 if (pm_runtime_suspended(&pdev->dev)) 1080 pm_runtime_resume(&pdev->dev); 1081 else 1082 tb_domain_complete(tb); 1083 } 1084 1085 static int nhi_runtime_suspend(struct device *dev) 1086 { 1087 struct pci_dev *pdev = to_pci_dev(dev); 1088 struct tb *tb = pci_get_drvdata(pdev); 1089 struct tb_nhi *nhi = tb->nhi; 1090 int ret; 1091 1092 ret = tb_domain_runtime_suspend(tb); 1093 if (ret) 1094 return ret; 1095 1096 if (nhi->ops && nhi->ops->runtime_suspend) { 1097 ret = nhi->ops->runtime_suspend(tb->nhi); 1098 if (ret) 1099 return ret; 1100 } 1101 return 0; 1102 } 1103 1104 static int nhi_runtime_resume(struct device *dev) 1105 { 1106 struct pci_dev *pdev = to_pci_dev(dev); 1107 struct tb *tb = pci_get_drvdata(pdev); 1108 struct tb_nhi *nhi = tb->nhi; 1109 int ret; 1110 1111 if (nhi->ops && nhi->ops->runtime_resume) { 1112 ret = nhi->ops->runtime_resume(nhi); 1113 if (ret) 1114 return ret; 1115 } 1116 1117 nhi_enable_int_throttling(nhi); 1118 return tb_domain_runtime_resume(tb); 1119 } 1120 1121 static void nhi_shutdown(struct tb_nhi *nhi) 1122 { 1123 int i; 1124 1125 dev_dbg(&nhi->pdev->dev, "shutdown\n"); 1126 1127 for (i = 0; i < nhi->hop_count; i++) { 1128 if (nhi->tx_rings[i]) 1129 dev_WARN(&nhi->pdev->dev, 1130 "TX ring %d is still active\n", i); 1131 if (nhi->rx_rings[i]) 1132 dev_WARN(&nhi->pdev->dev, 1133 "RX ring %d is still active\n", i); 1134 } 1135 nhi_disable_interrupts(nhi); 1136 /* 1137 * We have to release the irq before calling flush_work. Otherwise an 1138 * already executing IRQ handler could call schedule_work again. 1139 */ 1140 if (!nhi->pdev->msix_enabled) { 1141 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi); 1142 flush_work(&nhi->interrupt_work); 1143 } 1144 ida_destroy(&nhi->msix_ida); 1145 1146 if (nhi->ops && nhi->ops->shutdown) 1147 nhi->ops->shutdown(nhi); 1148 } 1149 1150 static void nhi_check_quirks(struct tb_nhi *nhi) 1151 { 1152 if (nhi->pdev->vendor == PCI_VENDOR_ID_INTEL) { 1153 /* 1154 * Intel hardware supports auto clear of the interrupt 1155 * status register right after interrupt is being 1156 * issued. 1157 */ 1158 nhi->quirks |= QUIRK_AUTO_CLEAR_INT; 1159 1160 switch (nhi->pdev->device) { 1161 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI: 1162 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI: 1163 /* 1164 * Falcon Ridge controller needs the end-to-end 1165 * flow control workaround to avoid losing Rx 1166 * packets when RING_FLAG_E2E is set. 1167 */ 1168 nhi->quirks |= QUIRK_E2E; 1169 break; 1170 } 1171 } 1172 } 1173 1174 static int nhi_check_iommu_pdev(struct pci_dev *pdev, void *data) 1175 { 1176 if (!pdev->external_facing || 1177 !device_iommu_capable(&pdev->dev, IOMMU_CAP_PRE_BOOT_PROTECTION)) 1178 return 0; 1179 *(bool *)data = true; 1180 return 1; /* Stop walking */ 1181 } 1182 1183 static void nhi_check_iommu(struct tb_nhi *nhi) 1184 { 1185 struct pci_bus *bus = nhi->pdev->bus; 1186 bool port_ok = false; 1187 1188 /* 1189 * Ideally what we'd do here is grab every PCI device that 1190 * represents a tunnelling adapter for this NHI and check their 1191 * status directly, but unfortunately USB4 seems to make it 1192 * obnoxiously difficult to reliably make any correlation. 1193 * 1194 * So for now we'll have to bodge it... Hoping that the system 1195 * is at least sane enough that an adapter is in the same PCI 1196 * segment as its NHI, if we can find *something* on that segment 1197 * which meets the requirements for Kernel DMA Protection, we'll 1198 * take that to imply that firmware is aware and has (hopefully) 1199 * done the right thing in general. We need to know that the PCI 1200 * layer has seen the ExternalFacingPort property which will then 1201 * inform the IOMMU layer to enforce the complete "untrusted DMA" 1202 * flow, but also that the IOMMU driver itself can be trusted not 1203 * to have been subverted by a pre-boot DMA attack. 1204 */ 1205 while (bus->parent) 1206 bus = bus->parent; 1207 1208 pci_walk_bus(bus, nhi_check_iommu_pdev, &port_ok); 1209 1210 nhi->iommu_dma_protection = port_ok; 1211 dev_dbg(&nhi->pdev->dev, "IOMMU DMA protection is %s\n", 1212 str_enabled_disabled(port_ok)); 1213 } 1214 1215 static int nhi_init_msi(struct tb_nhi *nhi) 1216 { 1217 struct pci_dev *pdev = nhi->pdev; 1218 struct device *dev = &pdev->dev; 1219 int res, irq, nvec; 1220 1221 /* In case someone left them on. */ 1222 nhi_disable_interrupts(nhi); 1223 1224 nhi_enable_int_throttling(nhi); 1225 1226 ida_init(&nhi->msix_ida); 1227 1228 /* 1229 * The NHI has 16 MSI-X vectors or a single MSI. We first try to 1230 * get all MSI-X vectors and if we succeed, each ring will have 1231 * one MSI-X. If for some reason that does not work out, we 1232 * fallback to a single MSI. 1233 */ 1234 nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS, 1235 PCI_IRQ_MSIX); 1236 if (nvec < 0) { 1237 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1238 if (nvec < 0) 1239 return nvec; 1240 1241 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work); 1242 1243 irq = pci_irq_vector(nhi->pdev, 0); 1244 if (irq < 0) 1245 return irq; 1246 1247 res = devm_request_irq(&pdev->dev, irq, nhi_msi, 1248 IRQF_NO_SUSPEND, "thunderbolt", nhi); 1249 if (res) 1250 return dev_err_probe(dev, res, "request_irq failed, aborting\n"); 1251 } 1252 1253 return 0; 1254 } 1255 1256 static bool nhi_imr_valid(struct pci_dev *pdev) 1257 { 1258 u8 val; 1259 1260 if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val)) 1261 return !!val; 1262 1263 return true; 1264 } 1265 1266 static struct tb *nhi_select_cm(struct tb_nhi *nhi) 1267 { 1268 struct tb *tb; 1269 1270 /* 1271 * USB4 case is simple. If we got control of any of the 1272 * capabilities, we use software CM. 1273 */ 1274 if (tb_acpi_is_native()) 1275 return tb_probe(nhi); 1276 1277 /* 1278 * Either firmware based CM is running (we did not get control 1279 * from the firmware) or this is pre-USB4 PC so try first 1280 * firmware CM and then fallback to software CM. 1281 */ 1282 tb = icm_probe(nhi); 1283 if (!tb) 1284 tb = tb_probe(nhi); 1285 1286 return tb; 1287 } 1288 1289 static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1290 { 1291 struct device *dev = &pdev->dev; 1292 struct tb_nhi *nhi; 1293 struct tb *tb; 1294 int res; 1295 1296 if (!nhi_imr_valid(pdev)) 1297 return dev_err_probe(dev, -ENODEV, "firmware image not valid, aborting\n"); 1298 1299 res = pcim_enable_device(pdev); 1300 if (res) 1301 return dev_err_probe(dev, res, "cannot enable PCI device, aborting\n"); 1302 1303 res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt"); 1304 if (res) 1305 return dev_err_probe(dev, res, "cannot obtain PCI resources, aborting\n"); 1306 1307 nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL); 1308 if (!nhi) 1309 return -ENOMEM; 1310 1311 nhi->pdev = pdev; 1312 nhi->ops = (const struct tb_nhi_ops *)id->driver_data; 1313 /* cannot fail - table is allocated in pcim_iomap_regions */ 1314 nhi->iobase = pcim_iomap_table(pdev)[0]; 1315 nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff; 1316 dev_dbg(dev, "total paths: %d\n", nhi->hop_count); 1317 1318 nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count, 1319 sizeof(*nhi->tx_rings), GFP_KERNEL); 1320 nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count, 1321 sizeof(*nhi->rx_rings), GFP_KERNEL); 1322 if (!nhi->tx_rings || !nhi->rx_rings) 1323 return -ENOMEM; 1324 1325 nhi_check_quirks(nhi); 1326 nhi_check_iommu(nhi); 1327 1328 res = nhi_init_msi(nhi); 1329 if (res) 1330 return dev_err_probe(dev, res, "cannot enable MSI, aborting\n"); 1331 1332 spin_lock_init(&nhi->lock); 1333 1334 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1335 if (res) 1336 return dev_err_probe(dev, res, "failed to set DMA mask\n"); 1337 1338 pci_set_master(pdev); 1339 1340 if (nhi->ops && nhi->ops->init) { 1341 res = nhi->ops->init(nhi); 1342 if (res) 1343 return res; 1344 } 1345 1346 tb = nhi_select_cm(nhi); 1347 if (!tb) 1348 return dev_err_probe(dev, -ENODEV, 1349 "failed to determine connection manager, aborting\n"); 1350 1351 dev_dbg(dev, "NHI initialized, starting thunderbolt\n"); 1352 1353 res = tb_domain_add(tb); 1354 if (res) { 1355 /* 1356 * At this point the RX/TX rings might already have been 1357 * activated. Do a proper shutdown. 1358 */ 1359 tb_domain_put(tb); 1360 nhi_shutdown(nhi); 1361 return res; 1362 } 1363 pci_set_drvdata(pdev, tb); 1364 1365 device_wakeup_enable(&pdev->dev); 1366 1367 pm_runtime_allow(&pdev->dev); 1368 pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY); 1369 pm_runtime_use_autosuspend(&pdev->dev); 1370 pm_runtime_put_autosuspend(&pdev->dev); 1371 1372 return 0; 1373 } 1374 1375 static void nhi_remove(struct pci_dev *pdev) 1376 { 1377 struct tb *tb = pci_get_drvdata(pdev); 1378 struct tb_nhi *nhi = tb->nhi; 1379 1380 pm_runtime_get_sync(&pdev->dev); 1381 pm_runtime_dont_use_autosuspend(&pdev->dev); 1382 pm_runtime_forbid(&pdev->dev); 1383 1384 tb_domain_remove(tb); 1385 nhi_shutdown(nhi); 1386 } 1387 1388 /* 1389 * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable 1390 * the tunnels asap. A corresponding pci quirk blocks the downstream bridges 1391 * resume_noirq until we are done. 1392 */ 1393 static const struct dev_pm_ops nhi_pm_ops = { 1394 .suspend_noirq = nhi_suspend_noirq, 1395 .resume_noirq = nhi_resume_noirq, 1396 .freeze_noirq = nhi_freeze_noirq, /* 1397 * we just disable hotplug, the 1398 * pci-tunnels stay alive. 1399 */ 1400 .thaw_noirq = nhi_thaw_noirq, 1401 .restore_noirq = nhi_resume_noirq, 1402 .suspend = nhi_suspend, 1403 .poweroff_noirq = nhi_poweroff_noirq, 1404 .poweroff = nhi_suspend, 1405 .complete = nhi_complete, 1406 .runtime_suspend = nhi_runtime_suspend, 1407 .runtime_resume = nhi_runtime_resume, 1408 }; 1409 1410 static struct pci_device_id nhi_ids[] = { 1411 /* 1412 * We have to specify class, the TB bridges use the same device and 1413 * vendor (sub)id on gen 1 and gen 2 controllers. 1414 */ 1415 { 1416 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1417 .vendor = PCI_VENDOR_ID_INTEL, 1418 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 1419 .subvendor = 0x2222, .subdevice = 0x1111, 1420 }, 1421 { 1422 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1423 .vendor = PCI_VENDOR_ID_INTEL, 1424 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 1425 .subvendor = 0x2222, .subdevice = 0x1111, 1426 }, 1427 { 1428 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1429 .vendor = PCI_VENDOR_ID_INTEL, 1430 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI, 1431 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 1432 }, 1433 { 1434 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1435 .vendor = PCI_VENDOR_ID_INTEL, 1436 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI, 1437 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 1438 }, 1439 1440 /* Thunderbolt 3 */ 1441 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) }, 1442 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) }, 1443 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) }, 1444 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) }, 1445 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) }, 1446 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) }, 1447 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) }, 1448 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) }, 1449 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) }, 1450 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) }, 1451 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0), 1452 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1453 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1), 1454 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1455 /* Thunderbolt 4 */ 1456 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0), 1457 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1458 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1), 1459 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1460 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0), 1461 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1462 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1), 1463 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1464 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI0), 1465 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1466 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI1), 1467 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1468 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI0), 1469 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1470 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI1), 1471 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1472 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_M_NHI0), 1473 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1474 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI0), 1475 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1476 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI1), 1477 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1478 1479 /* Any USB4 compliant host */ 1480 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) }, 1481 1482 { 0,} 1483 }; 1484 1485 MODULE_DEVICE_TABLE(pci, nhi_ids); 1486 MODULE_LICENSE("GPL"); 1487 1488 static struct pci_driver nhi_driver = { 1489 .name = "thunderbolt", 1490 .id_table = nhi_ids, 1491 .probe = nhi_probe, 1492 .remove = nhi_remove, 1493 .shutdown = nhi_remove, 1494 .driver.pm = &nhi_pm_ops, 1495 }; 1496 1497 static int __init nhi_init(void) 1498 { 1499 int ret; 1500 1501 ret = tb_domain_init(); 1502 if (ret) 1503 return ret; 1504 ret = pci_register_driver(&nhi_driver); 1505 if (ret) 1506 tb_domain_exit(); 1507 return ret; 1508 } 1509 1510 static void __exit nhi_unload(void) 1511 { 1512 pci_unregister_driver(&nhi_driver); 1513 tb_domain_exit(); 1514 } 1515 1516 rootfs_initcall(nhi_init); 1517 module_exit(nhi_unload); 1518