1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Thunderbolt driver - NHI driver 4 * 5 * The NHI (native host interface) is the pci device that allows us to send and 6 * receive frames from the thunderbolt bus. 7 * 8 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> 9 * Copyright (C) 2018, Intel Corporation 10 */ 11 12 #include <linux/pm_runtime.h> 13 #include <linux/slab.h> 14 #include <linux/errno.h> 15 #include <linux/pci.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/interrupt.h> 18 #include <linux/iommu.h> 19 #include <linux/module.h> 20 #include <linux/delay.h> 21 #include <linux/property.h> 22 #include <linux/string_helpers.h> 23 24 #include "nhi.h" 25 #include "nhi_regs.h" 26 #include "tb.h" 27 28 #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring") 29 30 #define RING_FIRST_USABLE_HOPID 1 31 /* 32 * Used with QUIRK_E2E to specify an unused HopID the Rx credits are 33 * transferred. 34 */ 35 #define RING_E2E_RESERVED_HOPID RING_FIRST_USABLE_HOPID 36 /* 37 * Minimal number of vectors when we use MSI-X. Two for control channel 38 * Rx/Tx and the rest four are for cross domain DMA paths. 39 */ 40 #define MSIX_MIN_VECS 6 41 #define MSIX_MAX_VECS 16 42 43 #define NHI_MAILBOX_TIMEOUT 500 /* ms */ 44 45 /* Host interface quirks */ 46 #define QUIRK_AUTO_CLEAR_INT BIT(0) 47 #define QUIRK_E2E BIT(1) 48 49 static bool host_reset = true; 50 module_param(host_reset, bool, 0444); 51 MODULE_PARM_DESC(host_reset, "reset USBv2 host router (default: true)"); 52 ring_interrupt_index(const struct tb_ring * ring)53 static int ring_interrupt_index(const struct tb_ring *ring) 54 { 55 int bit = ring->hop; 56 if (!ring->is_tx) 57 bit += ring->nhi->hop_count; 58 return bit; 59 } 60 nhi_mask_interrupt(struct tb_nhi * nhi,int mask,int ring)61 static void nhi_mask_interrupt(struct tb_nhi *nhi, int mask, int ring) 62 { 63 if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) { 64 u32 val; 65 66 val = ioread32(nhi->iobase + REG_RING_INTERRUPT_BASE + ring); 67 iowrite32(val & ~mask, nhi->iobase + REG_RING_INTERRUPT_BASE + ring); 68 } else { 69 iowrite32(mask, nhi->iobase + REG_RING_INTERRUPT_MASK_CLEAR_BASE + ring); 70 } 71 } 72 nhi_clear_interrupt(struct tb_nhi * nhi,int ring)73 static void nhi_clear_interrupt(struct tb_nhi *nhi, int ring) 74 { 75 if (nhi->quirks & QUIRK_AUTO_CLEAR_INT) 76 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + ring); 77 else 78 iowrite32(~0, nhi->iobase + REG_RING_INT_CLEAR + ring); 79 } 80 81 /* 82 * ring_interrupt_active() - activate/deactivate interrupts for a single ring 83 * 84 * ring->nhi->lock must be held. 85 */ ring_interrupt_active(struct tb_ring * ring,bool active)86 static void ring_interrupt_active(struct tb_ring *ring, bool active) 87 { 88 int index = ring_interrupt_index(ring) / 32 * 4; 89 int reg = REG_RING_INTERRUPT_BASE + index; 90 int interrupt_bit = ring_interrupt_index(ring) & 31; 91 int mask = 1 << interrupt_bit; 92 u32 old, new; 93 94 if (ring->irq > 0) { 95 u32 step, shift, ivr, misc; 96 void __iomem *ivr_base; 97 int auto_clear_bit; 98 int index; 99 100 if (ring->is_tx) 101 index = ring->hop; 102 else 103 index = ring->hop + ring->nhi->hop_count; 104 105 /* 106 * Intel routers support a bit that isn't part of 107 * the USB4 spec to ask the hardware to clear 108 * interrupt status bits automatically since 109 * we already know which interrupt was triggered. 110 * 111 * Other routers explicitly disable auto-clear 112 * to prevent conditions that may occur where two 113 * MSIX interrupts are simultaneously active and 114 * reading the register clears both of them. 115 */ 116 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); 117 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT) 118 auto_clear_bit = REG_DMA_MISC_INT_AUTO_CLEAR; 119 else 120 auto_clear_bit = REG_DMA_MISC_DISABLE_AUTO_CLEAR; 121 if (!(misc & auto_clear_bit)) 122 iowrite32(misc | auto_clear_bit, 123 ring->nhi->iobase + REG_DMA_MISC); 124 125 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE; 126 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; 127 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; 128 ivr = ioread32(ivr_base + step); 129 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift); 130 if (active) 131 ivr |= ring->vector << shift; 132 iowrite32(ivr, ivr_base + step); 133 } 134 135 old = ioread32(ring->nhi->iobase + reg); 136 if (active) 137 new = old | mask; 138 else 139 new = old & ~mask; 140 141 dev_dbg(&ring->nhi->pdev->dev, 142 "%s interrupt at register %#x bit %d (%#x -> %#x)\n", 143 active ? "enabling" : "disabling", reg, interrupt_bit, old, new); 144 145 if (new == old) 146 dev_WARN(&ring->nhi->pdev->dev, 147 "interrupt for %s %d is already %s\n", 148 RING_TYPE(ring), ring->hop, 149 active ? "enabled" : "disabled"); 150 151 if (active) 152 iowrite32(new, ring->nhi->iobase + reg); 153 else 154 nhi_mask_interrupt(ring->nhi, mask, index); 155 } 156 157 /* 158 * nhi_disable_interrupts() - disable interrupts for all rings 159 * 160 * Use only during init and shutdown. 161 */ nhi_disable_interrupts(struct tb_nhi * nhi)162 static void nhi_disable_interrupts(struct tb_nhi *nhi) 163 { 164 int i = 0; 165 /* disable interrupts */ 166 for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++) 167 nhi_mask_interrupt(nhi, ~0, 4 * i); 168 169 /* clear interrupt status bits */ 170 for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++) 171 nhi_clear_interrupt(nhi, 4 * i); 172 } 173 174 /* ring helper methods */ 175 ring_desc_base(struct tb_ring * ring)176 static void __iomem *ring_desc_base(struct tb_ring *ring) 177 { 178 void __iomem *io = ring->nhi->iobase; 179 io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE; 180 io += ring->hop * 16; 181 return io; 182 } 183 ring_options_base(struct tb_ring * ring)184 static void __iomem *ring_options_base(struct tb_ring *ring) 185 { 186 void __iomem *io = ring->nhi->iobase; 187 io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE; 188 io += ring->hop * 32; 189 return io; 190 } 191 ring_iowrite_cons(struct tb_ring * ring,u16 cons)192 static void ring_iowrite_cons(struct tb_ring *ring, u16 cons) 193 { 194 /* 195 * The other 16-bits in the register is read-only and writes to it 196 * are ignored by the hardware so we can save one ioread32() by 197 * filling the read-only bits with zeroes. 198 */ 199 iowrite32(cons, ring_desc_base(ring) + 8); 200 } 201 ring_iowrite_prod(struct tb_ring * ring,u16 prod)202 static void ring_iowrite_prod(struct tb_ring *ring, u16 prod) 203 { 204 /* See ring_iowrite_cons() above for explanation */ 205 iowrite32(prod << 16, ring_desc_base(ring) + 8); 206 } 207 ring_iowrite32desc(struct tb_ring * ring,u32 value,u32 offset)208 static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset) 209 { 210 iowrite32(value, ring_desc_base(ring) + offset); 211 } 212 ring_iowrite64desc(struct tb_ring * ring,u64 value,u32 offset)213 static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset) 214 { 215 iowrite32(value, ring_desc_base(ring) + offset); 216 iowrite32(value >> 32, ring_desc_base(ring) + offset + 4); 217 } 218 ring_iowrite32options(struct tb_ring * ring,u32 value,u32 offset)219 static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset) 220 { 221 iowrite32(value, ring_options_base(ring) + offset); 222 } 223 ring_full(struct tb_ring * ring)224 static bool ring_full(struct tb_ring *ring) 225 { 226 return ((ring->head + 1) % ring->size) == ring->tail; 227 } 228 ring_empty(struct tb_ring * ring)229 static bool ring_empty(struct tb_ring *ring) 230 { 231 return ring->head == ring->tail; 232 } 233 234 /* 235 * ring_write_descriptors() - post frames from ring->queue to the controller 236 * 237 * ring->lock is held. 238 */ ring_write_descriptors(struct tb_ring * ring)239 static void ring_write_descriptors(struct tb_ring *ring) 240 { 241 struct ring_frame *frame, *n; 242 struct ring_desc *descriptor; 243 list_for_each_entry_safe(frame, n, &ring->queue, list) { 244 if (ring_full(ring)) 245 break; 246 list_move_tail(&frame->list, &ring->in_flight); 247 descriptor = &ring->descriptors[ring->head]; 248 descriptor->phys = frame->buffer_phy; 249 descriptor->time = 0; 250 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT; 251 if (ring->is_tx) { 252 descriptor->length = frame->size; 253 descriptor->eof = frame->eof; 254 descriptor->sof = frame->sof; 255 } 256 ring->head = (ring->head + 1) % ring->size; 257 if (ring->is_tx) 258 ring_iowrite_prod(ring, ring->head); 259 else 260 ring_iowrite_cons(ring, ring->head); 261 } 262 } 263 264 /* 265 * ring_work() - progress completed frames 266 * 267 * If the ring is shutting down then all frames are marked as canceled and 268 * their callbacks are invoked. 269 * 270 * Otherwise we collect all completed frame from the ring buffer, write new 271 * frame to the ring buffer and invoke the callbacks for the completed frames. 272 */ ring_work(struct work_struct * work)273 static void ring_work(struct work_struct *work) 274 { 275 struct tb_ring *ring = container_of(work, typeof(*ring), work); 276 struct ring_frame *frame; 277 bool canceled = false; 278 unsigned long flags; 279 LIST_HEAD(done); 280 281 spin_lock_irqsave(&ring->lock, flags); 282 283 if (!ring->running) { 284 /* Move all frames to done and mark them as canceled. */ 285 list_splice_tail_init(&ring->in_flight, &done); 286 list_splice_tail_init(&ring->queue, &done); 287 canceled = true; 288 goto invoke_callback; 289 } 290 291 while (!ring_empty(ring)) { 292 if (!(ring->descriptors[ring->tail].flags 293 & RING_DESC_COMPLETED)) 294 break; 295 frame = list_first_entry(&ring->in_flight, typeof(*frame), 296 list); 297 list_move_tail(&frame->list, &done); 298 if (!ring->is_tx) { 299 frame->size = ring->descriptors[ring->tail].length; 300 frame->eof = ring->descriptors[ring->tail].eof; 301 frame->sof = ring->descriptors[ring->tail].sof; 302 frame->flags = ring->descriptors[ring->tail].flags; 303 } 304 ring->tail = (ring->tail + 1) % ring->size; 305 } 306 ring_write_descriptors(ring); 307 308 invoke_callback: 309 /* allow callbacks to schedule new work */ 310 spin_unlock_irqrestore(&ring->lock, flags); 311 while (!list_empty(&done)) { 312 frame = list_first_entry(&done, typeof(*frame), list); 313 /* 314 * The callback may reenqueue or delete frame. 315 * Do not hold on to it. 316 */ 317 list_del_init(&frame->list); 318 if (frame->callback) 319 frame->callback(ring, frame, canceled); 320 } 321 } 322 __tb_ring_enqueue(struct tb_ring * ring,struct ring_frame * frame)323 int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame) 324 { 325 unsigned long flags; 326 int ret = 0; 327 328 spin_lock_irqsave(&ring->lock, flags); 329 if (ring->running) { 330 list_add_tail(&frame->list, &ring->queue); 331 ring_write_descriptors(ring); 332 } else { 333 ret = -ESHUTDOWN; 334 } 335 spin_unlock_irqrestore(&ring->lock, flags); 336 return ret; 337 } 338 EXPORT_SYMBOL_GPL(__tb_ring_enqueue); 339 340 /** 341 * tb_ring_poll() - Poll one completed frame from the ring 342 * @ring: Ring to poll 343 * 344 * This function can be called when @start_poll callback of the @ring 345 * has been called. It will read one completed frame from the ring and 346 * return it to the caller. Returns %NULL if there is no more completed 347 * frames. 348 */ tb_ring_poll(struct tb_ring * ring)349 struct ring_frame *tb_ring_poll(struct tb_ring *ring) 350 { 351 struct ring_frame *frame = NULL; 352 unsigned long flags; 353 354 spin_lock_irqsave(&ring->lock, flags); 355 if (!ring->running) 356 goto unlock; 357 if (ring_empty(ring)) 358 goto unlock; 359 360 if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) { 361 frame = list_first_entry(&ring->in_flight, typeof(*frame), 362 list); 363 list_del_init(&frame->list); 364 365 if (!ring->is_tx) { 366 frame->size = ring->descriptors[ring->tail].length; 367 frame->eof = ring->descriptors[ring->tail].eof; 368 frame->sof = ring->descriptors[ring->tail].sof; 369 frame->flags = ring->descriptors[ring->tail].flags; 370 } 371 372 ring->tail = (ring->tail + 1) % ring->size; 373 } 374 375 unlock: 376 spin_unlock_irqrestore(&ring->lock, flags); 377 return frame; 378 } 379 EXPORT_SYMBOL_GPL(tb_ring_poll); 380 __ring_interrupt_mask(struct tb_ring * ring,bool mask)381 static void __ring_interrupt_mask(struct tb_ring *ring, bool mask) 382 { 383 int idx = ring_interrupt_index(ring); 384 int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4; 385 int bit = idx % 32; 386 u32 val; 387 388 val = ioread32(ring->nhi->iobase + reg); 389 if (mask) 390 val &= ~BIT(bit); 391 else 392 val |= BIT(bit); 393 iowrite32(val, ring->nhi->iobase + reg); 394 } 395 396 /* Both @nhi->lock and @ring->lock should be held */ __ring_interrupt(struct tb_ring * ring)397 static void __ring_interrupt(struct tb_ring *ring) 398 { 399 if (!ring->running) 400 return; 401 402 if (ring->start_poll) { 403 __ring_interrupt_mask(ring, true); 404 ring->start_poll(ring->poll_data); 405 } else { 406 schedule_work(&ring->work); 407 } 408 } 409 410 /** 411 * tb_ring_poll_complete() - Re-start interrupt for the ring 412 * @ring: Ring to re-start the interrupt 413 * 414 * This will re-start (unmask) the ring interrupt once the user is done 415 * with polling. 416 */ tb_ring_poll_complete(struct tb_ring * ring)417 void tb_ring_poll_complete(struct tb_ring *ring) 418 { 419 unsigned long flags; 420 421 spin_lock_irqsave(&ring->nhi->lock, flags); 422 spin_lock(&ring->lock); 423 if (ring->start_poll) 424 __ring_interrupt_mask(ring, false); 425 spin_unlock(&ring->lock); 426 spin_unlock_irqrestore(&ring->nhi->lock, flags); 427 } 428 EXPORT_SYMBOL_GPL(tb_ring_poll_complete); 429 ring_clear_msix(const struct tb_ring * ring)430 static void ring_clear_msix(const struct tb_ring *ring) 431 { 432 int bit; 433 434 if (ring->nhi->quirks & QUIRK_AUTO_CLEAR_INT) 435 return; 436 437 bit = ring_interrupt_index(ring) & 31; 438 if (ring->is_tx) 439 iowrite32(BIT(bit), ring->nhi->iobase + REG_RING_INT_CLEAR); 440 else 441 iowrite32(BIT(bit), ring->nhi->iobase + REG_RING_INT_CLEAR + 442 4 * (ring->nhi->hop_count / 32)); 443 } 444 ring_msix(int irq,void * data)445 static irqreturn_t ring_msix(int irq, void *data) 446 { 447 struct tb_ring *ring = data; 448 449 spin_lock(&ring->nhi->lock); 450 ring_clear_msix(ring); 451 spin_lock(&ring->lock); 452 __ring_interrupt(ring); 453 spin_unlock(&ring->lock); 454 spin_unlock(&ring->nhi->lock); 455 456 return IRQ_HANDLED; 457 } 458 ring_request_msix(struct tb_ring * ring,bool no_suspend)459 static int ring_request_msix(struct tb_ring *ring, bool no_suspend) 460 { 461 struct tb_nhi *nhi = ring->nhi; 462 unsigned long irqflags; 463 int ret; 464 465 if (!nhi->pdev->msix_enabled) 466 return 0; 467 468 ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL); 469 if (ret < 0) 470 return ret; 471 472 ring->vector = ret; 473 474 ret = pci_irq_vector(ring->nhi->pdev, ring->vector); 475 if (ret < 0) 476 goto err_ida_remove; 477 478 ring->irq = ret; 479 480 irqflags = no_suspend ? IRQF_NO_SUSPEND : 0; 481 ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring); 482 if (ret) 483 goto err_ida_remove; 484 485 return 0; 486 487 err_ida_remove: 488 ida_simple_remove(&nhi->msix_ida, ring->vector); 489 490 return ret; 491 } 492 ring_release_msix(struct tb_ring * ring)493 static void ring_release_msix(struct tb_ring *ring) 494 { 495 if (ring->irq <= 0) 496 return; 497 498 free_irq(ring->irq, ring); 499 ida_simple_remove(&ring->nhi->msix_ida, ring->vector); 500 ring->vector = 0; 501 ring->irq = 0; 502 } 503 nhi_alloc_hop(struct tb_nhi * nhi,struct tb_ring * ring)504 static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring) 505 { 506 unsigned int start_hop = RING_FIRST_USABLE_HOPID; 507 int ret = 0; 508 509 if (nhi->quirks & QUIRK_E2E) { 510 start_hop = RING_FIRST_USABLE_HOPID + 1; 511 if (ring->flags & RING_FLAG_E2E && !ring->is_tx) { 512 dev_dbg(&nhi->pdev->dev, "quirking E2E TX HopID %u -> %u\n", 513 ring->e2e_tx_hop, RING_E2E_RESERVED_HOPID); 514 ring->e2e_tx_hop = RING_E2E_RESERVED_HOPID; 515 } 516 } 517 518 spin_lock_irq(&nhi->lock); 519 520 if (ring->hop < 0) { 521 unsigned int i; 522 523 /* 524 * Automatically allocate HopID from the non-reserved 525 * range 1 .. hop_count - 1. 526 */ 527 for (i = start_hop; i < nhi->hop_count; i++) { 528 if (ring->is_tx) { 529 if (!nhi->tx_rings[i]) { 530 ring->hop = i; 531 break; 532 } 533 } else { 534 if (!nhi->rx_rings[i]) { 535 ring->hop = i; 536 break; 537 } 538 } 539 } 540 } 541 542 if (ring->hop > 0 && ring->hop < start_hop) { 543 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop); 544 ret = -EINVAL; 545 goto err_unlock; 546 } 547 if (ring->hop < 0 || ring->hop >= nhi->hop_count) { 548 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop); 549 ret = -EINVAL; 550 goto err_unlock; 551 } 552 if (ring->is_tx && nhi->tx_rings[ring->hop]) { 553 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n", 554 ring->hop); 555 ret = -EBUSY; 556 goto err_unlock; 557 } 558 if (!ring->is_tx && nhi->rx_rings[ring->hop]) { 559 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n", 560 ring->hop); 561 ret = -EBUSY; 562 goto err_unlock; 563 } 564 565 if (ring->is_tx) 566 nhi->tx_rings[ring->hop] = ring; 567 else 568 nhi->rx_rings[ring->hop] = ring; 569 570 err_unlock: 571 spin_unlock_irq(&nhi->lock); 572 573 return ret; 574 } 575 tb_ring_alloc(struct tb_nhi * nhi,u32 hop,int size,bool transmit,unsigned int flags,int e2e_tx_hop,u16 sof_mask,u16 eof_mask,void (* start_poll)(void *),void * poll_data)576 static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size, 577 bool transmit, unsigned int flags, 578 int e2e_tx_hop, u16 sof_mask, u16 eof_mask, 579 void (*start_poll)(void *), 580 void *poll_data) 581 { 582 struct tb_ring *ring = NULL; 583 584 dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n", 585 transmit ? "TX" : "RX", hop, size); 586 587 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 588 if (!ring) 589 return NULL; 590 591 spin_lock_init(&ring->lock); 592 INIT_LIST_HEAD(&ring->queue); 593 INIT_LIST_HEAD(&ring->in_flight); 594 INIT_WORK(&ring->work, ring_work); 595 596 ring->nhi = nhi; 597 ring->hop = hop; 598 ring->is_tx = transmit; 599 ring->size = size; 600 ring->flags = flags; 601 ring->e2e_tx_hop = e2e_tx_hop; 602 ring->sof_mask = sof_mask; 603 ring->eof_mask = eof_mask; 604 ring->head = 0; 605 ring->tail = 0; 606 ring->running = false; 607 ring->start_poll = start_poll; 608 ring->poll_data = poll_data; 609 610 ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev, 611 size * sizeof(*ring->descriptors), 612 &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO); 613 if (!ring->descriptors) 614 goto err_free_ring; 615 616 if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND)) 617 goto err_free_descs; 618 619 if (nhi_alloc_hop(nhi, ring)) 620 goto err_release_msix; 621 622 return ring; 623 624 err_release_msix: 625 ring_release_msix(ring); 626 err_free_descs: 627 dma_free_coherent(&ring->nhi->pdev->dev, 628 ring->size * sizeof(*ring->descriptors), 629 ring->descriptors, ring->descriptors_dma); 630 err_free_ring: 631 kfree(ring); 632 633 return NULL; 634 } 635 636 /** 637 * tb_ring_alloc_tx() - Allocate DMA ring for transmit 638 * @nhi: Pointer to the NHI the ring is to be allocated 639 * @hop: HopID (ring) to allocate 640 * @size: Number of entries in the ring 641 * @flags: Flags for the ring 642 */ tb_ring_alloc_tx(struct tb_nhi * nhi,int hop,int size,unsigned int flags)643 struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size, 644 unsigned int flags) 645 { 646 return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, 0, NULL, NULL); 647 } 648 EXPORT_SYMBOL_GPL(tb_ring_alloc_tx); 649 650 /** 651 * tb_ring_alloc_rx() - Allocate DMA ring for receive 652 * @nhi: Pointer to the NHI the ring is to be allocated 653 * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation. 654 * @size: Number of entries in the ring 655 * @flags: Flags for the ring 656 * @e2e_tx_hop: Transmit HopID when E2E is enabled in @flags 657 * @sof_mask: Mask of PDF values that start a frame 658 * @eof_mask: Mask of PDF values that end a frame 659 * @start_poll: If not %NULL the ring will call this function when an 660 * interrupt is triggered and masked, instead of callback 661 * in each Rx frame. 662 * @poll_data: Optional data passed to @start_poll 663 */ tb_ring_alloc_rx(struct tb_nhi * nhi,int hop,int size,unsigned int flags,int e2e_tx_hop,u16 sof_mask,u16 eof_mask,void (* start_poll)(void *),void * poll_data)664 struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size, 665 unsigned int flags, int e2e_tx_hop, 666 u16 sof_mask, u16 eof_mask, 667 void (*start_poll)(void *), void *poll_data) 668 { 669 return tb_ring_alloc(nhi, hop, size, false, flags, e2e_tx_hop, sof_mask, eof_mask, 670 start_poll, poll_data); 671 } 672 EXPORT_SYMBOL_GPL(tb_ring_alloc_rx); 673 674 /** 675 * tb_ring_start() - enable a ring 676 * @ring: Ring to start 677 * 678 * Must not be invoked in parallel with tb_ring_stop(). 679 */ tb_ring_start(struct tb_ring * ring)680 void tb_ring_start(struct tb_ring *ring) 681 { 682 u16 frame_size; 683 u32 flags; 684 685 spin_lock_irq(&ring->nhi->lock); 686 spin_lock(&ring->lock); 687 if (ring->nhi->going_away) 688 goto err; 689 if (ring->running) { 690 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n"); 691 goto err; 692 } 693 dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n", 694 RING_TYPE(ring), ring->hop); 695 696 if (ring->flags & RING_FLAG_FRAME) { 697 /* Means 4096 */ 698 frame_size = 0; 699 flags = RING_FLAG_ENABLE; 700 } else { 701 frame_size = TB_FRAME_SIZE; 702 flags = RING_FLAG_ENABLE | RING_FLAG_RAW; 703 } 704 705 ring_iowrite64desc(ring, ring->descriptors_dma, 0); 706 if (ring->is_tx) { 707 ring_iowrite32desc(ring, ring->size, 12); 708 ring_iowrite32options(ring, 0, 4); /* time releated ? */ 709 ring_iowrite32options(ring, flags, 0); 710 } else { 711 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask; 712 713 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12); 714 ring_iowrite32options(ring, sof_eof_mask, 4); 715 ring_iowrite32options(ring, flags, 0); 716 } 717 718 /* 719 * Now that the ring valid bit is set we can configure E2E if 720 * enabled for the ring. 721 */ 722 if (ring->flags & RING_FLAG_E2E) { 723 if (!ring->is_tx) { 724 u32 hop; 725 726 hop = ring->e2e_tx_hop << REG_RX_OPTIONS_E2E_HOP_SHIFT; 727 hop &= REG_RX_OPTIONS_E2E_HOP_MASK; 728 flags |= hop; 729 730 dev_dbg(&ring->nhi->pdev->dev, 731 "enabling E2E for %s %d with TX HopID %d\n", 732 RING_TYPE(ring), ring->hop, ring->e2e_tx_hop); 733 } else { 734 dev_dbg(&ring->nhi->pdev->dev, "enabling E2E for %s %d\n", 735 RING_TYPE(ring), ring->hop); 736 } 737 738 flags |= RING_FLAG_E2E_FLOW_CONTROL; 739 ring_iowrite32options(ring, flags, 0); 740 } 741 742 ring_interrupt_active(ring, true); 743 ring->running = true; 744 err: 745 spin_unlock(&ring->lock); 746 spin_unlock_irq(&ring->nhi->lock); 747 } 748 EXPORT_SYMBOL_GPL(tb_ring_start); 749 750 /** 751 * tb_ring_stop() - shutdown a ring 752 * @ring: Ring to stop 753 * 754 * Must not be invoked from a callback. 755 * 756 * This method will disable the ring. Further calls to 757 * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been 758 * called. 759 * 760 * All enqueued frames will be canceled and their callbacks will be executed 761 * with frame->canceled set to true (on the callback thread). This method 762 * returns only after all callback invocations have finished. 763 */ tb_ring_stop(struct tb_ring * ring)764 void tb_ring_stop(struct tb_ring *ring) 765 { 766 spin_lock_irq(&ring->nhi->lock); 767 spin_lock(&ring->lock); 768 dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n", 769 RING_TYPE(ring), ring->hop); 770 if (ring->nhi->going_away) 771 goto err; 772 if (!ring->running) { 773 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n", 774 RING_TYPE(ring), ring->hop); 775 goto err; 776 } 777 ring_interrupt_active(ring, false); 778 779 ring_iowrite32options(ring, 0, 0); 780 ring_iowrite64desc(ring, 0, 0); 781 ring_iowrite32desc(ring, 0, 8); 782 ring_iowrite32desc(ring, 0, 12); 783 ring->head = 0; 784 ring->tail = 0; 785 ring->running = false; 786 787 err: 788 spin_unlock(&ring->lock); 789 spin_unlock_irq(&ring->nhi->lock); 790 791 /* 792 * schedule ring->work to invoke callbacks on all remaining frames. 793 */ 794 schedule_work(&ring->work); 795 flush_work(&ring->work); 796 } 797 EXPORT_SYMBOL_GPL(tb_ring_stop); 798 799 /* 800 * tb_ring_free() - free ring 801 * 802 * When this method returns all invocations of ring->callback will have 803 * finished. 804 * 805 * Ring must be stopped. 806 * 807 * Must NOT be called from ring_frame->callback! 808 */ tb_ring_free(struct tb_ring * ring)809 void tb_ring_free(struct tb_ring *ring) 810 { 811 spin_lock_irq(&ring->nhi->lock); 812 /* 813 * Dissociate the ring from the NHI. This also ensures that 814 * nhi_interrupt_work cannot reschedule ring->work. 815 */ 816 if (ring->is_tx) 817 ring->nhi->tx_rings[ring->hop] = NULL; 818 else 819 ring->nhi->rx_rings[ring->hop] = NULL; 820 821 if (ring->running) { 822 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n", 823 RING_TYPE(ring), ring->hop); 824 } 825 spin_unlock_irq(&ring->nhi->lock); 826 827 ring_release_msix(ring); 828 829 dma_free_coherent(&ring->nhi->pdev->dev, 830 ring->size * sizeof(*ring->descriptors), 831 ring->descriptors, ring->descriptors_dma); 832 833 ring->descriptors = NULL; 834 ring->descriptors_dma = 0; 835 836 837 dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring), 838 ring->hop); 839 840 /* 841 * ring->work can no longer be scheduled (it is scheduled only 842 * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it 843 * to finish before freeing the ring. 844 */ 845 flush_work(&ring->work); 846 kfree(ring); 847 } 848 EXPORT_SYMBOL_GPL(tb_ring_free); 849 850 /** 851 * nhi_mailbox_cmd() - Send a command through NHI mailbox 852 * @nhi: Pointer to the NHI structure 853 * @cmd: Command to send 854 * @data: Data to be send with the command 855 * 856 * Sends mailbox command to the firmware running on NHI. Returns %0 in 857 * case of success and negative errno in case of failure. 858 */ nhi_mailbox_cmd(struct tb_nhi * nhi,enum nhi_mailbox_cmd cmd,u32 data)859 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data) 860 { 861 ktime_t timeout; 862 u32 val; 863 864 iowrite32(data, nhi->iobase + REG_INMAIL_DATA); 865 866 val = ioread32(nhi->iobase + REG_INMAIL_CMD); 867 val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR); 868 val |= REG_INMAIL_OP_REQUEST | cmd; 869 iowrite32(val, nhi->iobase + REG_INMAIL_CMD); 870 871 timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT); 872 do { 873 val = ioread32(nhi->iobase + REG_INMAIL_CMD); 874 if (!(val & REG_INMAIL_OP_REQUEST)) 875 break; 876 usleep_range(10, 20); 877 } while (ktime_before(ktime_get(), timeout)); 878 879 if (val & REG_INMAIL_OP_REQUEST) 880 return -ETIMEDOUT; 881 if (val & REG_INMAIL_ERROR) 882 return -EIO; 883 884 return 0; 885 } 886 887 /** 888 * nhi_mailbox_mode() - Return current firmware operation mode 889 * @nhi: Pointer to the NHI structure 890 * 891 * The function reads current firmware operation mode using NHI mailbox 892 * registers and returns it to the caller. 893 */ nhi_mailbox_mode(struct tb_nhi * nhi)894 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi) 895 { 896 u32 val; 897 898 val = ioread32(nhi->iobase + REG_OUTMAIL_CMD); 899 val &= REG_OUTMAIL_CMD_OPMODE_MASK; 900 val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT; 901 902 return (enum nhi_fw_mode)val; 903 } 904 nhi_interrupt_work(struct work_struct * work)905 static void nhi_interrupt_work(struct work_struct *work) 906 { 907 struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work); 908 int value = 0; /* Suppress uninitialized usage warning. */ 909 int bit; 910 int hop = -1; 911 int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */ 912 struct tb_ring *ring; 913 914 spin_lock_irq(&nhi->lock); 915 916 /* 917 * Starting at REG_RING_NOTIFY_BASE there are three status bitfields 918 * (TX, RX, RX overflow). We iterate over the bits and read a new 919 * dwords as required. The registers are cleared on read. 920 */ 921 for (bit = 0; bit < 3 * nhi->hop_count; bit++) { 922 if (bit % 32 == 0) 923 value = ioread32(nhi->iobase 924 + REG_RING_NOTIFY_BASE 925 + 4 * (bit / 32)); 926 if (++hop == nhi->hop_count) { 927 hop = 0; 928 type++; 929 } 930 if ((value & (1 << (bit % 32))) == 0) 931 continue; 932 if (type == 2) { 933 dev_warn(&nhi->pdev->dev, 934 "RX overflow for ring %d\n", 935 hop); 936 continue; 937 } 938 if (type == 0) 939 ring = nhi->tx_rings[hop]; 940 else 941 ring = nhi->rx_rings[hop]; 942 if (ring == NULL) { 943 dev_warn(&nhi->pdev->dev, 944 "got interrupt for inactive %s ring %d\n", 945 type ? "RX" : "TX", 946 hop); 947 continue; 948 } 949 950 spin_lock(&ring->lock); 951 __ring_interrupt(ring); 952 spin_unlock(&ring->lock); 953 } 954 spin_unlock_irq(&nhi->lock); 955 } 956 nhi_msi(int irq,void * data)957 static irqreturn_t nhi_msi(int irq, void *data) 958 { 959 struct tb_nhi *nhi = data; 960 schedule_work(&nhi->interrupt_work); 961 return IRQ_HANDLED; 962 } 963 __nhi_suspend_noirq(struct device * dev,bool wakeup)964 static int __nhi_suspend_noirq(struct device *dev, bool wakeup) 965 { 966 struct pci_dev *pdev = to_pci_dev(dev); 967 struct tb *tb = pci_get_drvdata(pdev); 968 struct tb_nhi *nhi = tb->nhi; 969 int ret; 970 971 ret = tb_domain_suspend_noirq(tb); 972 if (ret) 973 return ret; 974 975 if (nhi->ops && nhi->ops->suspend_noirq) { 976 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup); 977 if (ret) 978 return ret; 979 } 980 981 return 0; 982 } 983 nhi_suspend_noirq(struct device * dev)984 static int nhi_suspend_noirq(struct device *dev) 985 { 986 return __nhi_suspend_noirq(dev, device_may_wakeup(dev)); 987 } 988 nhi_freeze_noirq(struct device * dev)989 static int nhi_freeze_noirq(struct device *dev) 990 { 991 struct pci_dev *pdev = to_pci_dev(dev); 992 struct tb *tb = pci_get_drvdata(pdev); 993 994 return tb_domain_freeze_noirq(tb); 995 } 996 nhi_thaw_noirq(struct device * dev)997 static int nhi_thaw_noirq(struct device *dev) 998 { 999 struct pci_dev *pdev = to_pci_dev(dev); 1000 struct tb *tb = pci_get_drvdata(pdev); 1001 1002 return tb_domain_thaw_noirq(tb); 1003 } 1004 nhi_wake_supported(struct pci_dev * pdev)1005 static bool nhi_wake_supported(struct pci_dev *pdev) 1006 { 1007 u8 val; 1008 1009 /* 1010 * If power rails are sustainable for wakeup from S4 this 1011 * property is set by the BIOS. 1012 */ 1013 if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val)) 1014 return !!val; 1015 1016 return true; 1017 } 1018 nhi_poweroff_noirq(struct device * dev)1019 static int nhi_poweroff_noirq(struct device *dev) 1020 { 1021 struct pci_dev *pdev = to_pci_dev(dev); 1022 bool wakeup; 1023 1024 wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev); 1025 return __nhi_suspend_noirq(dev, wakeup); 1026 } 1027 nhi_enable_int_throttling(struct tb_nhi * nhi)1028 static void nhi_enable_int_throttling(struct tb_nhi *nhi) 1029 { 1030 /* Throttling is specified in 256ns increments */ 1031 u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256); 1032 unsigned int i; 1033 1034 /* 1035 * Configure interrupt throttling for all vectors even if we 1036 * only use few. 1037 */ 1038 for (i = 0; i < MSIX_MAX_VECS; i++) { 1039 u32 reg = REG_INT_THROTTLING_RATE + i * 4; 1040 iowrite32(throttle, nhi->iobase + reg); 1041 } 1042 } 1043 nhi_resume_noirq(struct device * dev)1044 static int nhi_resume_noirq(struct device *dev) 1045 { 1046 struct pci_dev *pdev = to_pci_dev(dev); 1047 struct tb *tb = pci_get_drvdata(pdev); 1048 struct tb_nhi *nhi = tb->nhi; 1049 int ret; 1050 1051 /* 1052 * Check that the device is still there. It may be that the user 1053 * unplugged last device which causes the host controller to go 1054 * away on PCs. 1055 */ 1056 if (!pci_device_is_present(pdev)) { 1057 nhi->going_away = true; 1058 } else { 1059 if (nhi->ops && nhi->ops->resume_noirq) { 1060 ret = nhi->ops->resume_noirq(nhi); 1061 if (ret) 1062 return ret; 1063 } 1064 nhi_enable_int_throttling(tb->nhi); 1065 } 1066 1067 return tb_domain_resume_noirq(tb); 1068 } 1069 nhi_suspend(struct device * dev)1070 static int nhi_suspend(struct device *dev) 1071 { 1072 struct pci_dev *pdev = to_pci_dev(dev); 1073 struct tb *tb = pci_get_drvdata(pdev); 1074 1075 return tb_domain_suspend(tb); 1076 } 1077 nhi_complete(struct device * dev)1078 static void nhi_complete(struct device *dev) 1079 { 1080 struct pci_dev *pdev = to_pci_dev(dev); 1081 struct tb *tb = pci_get_drvdata(pdev); 1082 1083 /* 1084 * If we were runtime suspended when system suspend started, 1085 * schedule runtime resume now. It should bring the domain back 1086 * to functional state. 1087 */ 1088 if (pm_runtime_suspended(&pdev->dev)) 1089 pm_runtime_resume(&pdev->dev); 1090 else 1091 tb_domain_complete(tb); 1092 } 1093 nhi_runtime_suspend(struct device * dev)1094 static int nhi_runtime_suspend(struct device *dev) 1095 { 1096 struct pci_dev *pdev = to_pci_dev(dev); 1097 struct tb *tb = pci_get_drvdata(pdev); 1098 struct tb_nhi *nhi = tb->nhi; 1099 int ret; 1100 1101 ret = tb_domain_runtime_suspend(tb); 1102 if (ret) 1103 return ret; 1104 1105 if (nhi->ops && nhi->ops->runtime_suspend) { 1106 ret = nhi->ops->runtime_suspend(tb->nhi); 1107 if (ret) 1108 return ret; 1109 } 1110 return 0; 1111 } 1112 nhi_runtime_resume(struct device * dev)1113 static int nhi_runtime_resume(struct device *dev) 1114 { 1115 struct pci_dev *pdev = to_pci_dev(dev); 1116 struct tb *tb = pci_get_drvdata(pdev); 1117 struct tb_nhi *nhi = tb->nhi; 1118 int ret; 1119 1120 if (nhi->ops && nhi->ops->runtime_resume) { 1121 ret = nhi->ops->runtime_resume(nhi); 1122 if (ret) 1123 return ret; 1124 } 1125 1126 nhi_enable_int_throttling(nhi); 1127 return tb_domain_runtime_resume(tb); 1128 } 1129 nhi_shutdown(struct tb_nhi * nhi)1130 static void nhi_shutdown(struct tb_nhi *nhi) 1131 { 1132 int i; 1133 1134 dev_dbg(&nhi->pdev->dev, "shutdown\n"); 1135 1136 for (i = 0; i < nhi->hop_count; i++) { 1137 if (nhi->tx_rings[i]) 1138 dev_WARN(&nhi->pdev->dev, 1139 "TX ring %d is still active\n", i); 1140 if (nhi->rx_rings[i]) 1141 dev_WARN(&nhi->pdev->dev, 1142 "RX ring %d is still active\n", i); 1143 } 1144 nhi_disable_interrupts(nhi); 1145 /* 1146 * We have to release the irq before calling flush_work. Otherwise an 1147 * already executing IRQ handler could call schedule_work again. 1148 */ 1149 if (!nhi->pdev->msix_enabled) { 1150 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi); 1151 flush_work(&nhi->interrupt_work); 1152 } 1153 ida_destroy(&nhi->msix_ida); 1154 1155 if (nhi->ops && nhi->ops->shutdown) 1156 nhi->ops->shutdown(nhi); 1157 } 1158 nhi_check_quirks(struct tb_nhi * nhi)1159 static void nhi_check_quirks(struct tb_nhi *nhi) 1160 { 1161 if (nhi->pdev->vendor == PCI_VENDOR_ID_INTEL) { 1162 /* 1163 * Intel hardware supports auto clear of the interrupt 1164 * status register right after interrupt is being 1165 * issued. 1166 */ 1167 nhi->quirks |= QUIRK_AUTO_CLEAR_INT; 1168 1169 switch (nhi->pdev->device) { 1170 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI: 1171 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI: 1172 /* 1173 * Falcon Ridge controller needs the end-to-end 1174 * flow control workaround to avoid losing Rx 1175 * packets when RING_FLAG_E2E is set. 1176 */ 1177 nhi->quirks |= QUIRK_E2E; 1178 break; 1179 } 1180 } 1181 } 1182 nhi_check_iommu_pdev(struct pci_dev * pdev,void * data)1183 static int nhi_check_iommu_pdev(struct pci_dev *pdev, void *data) 1184 { 1185 if (!pdev->external_facing || 1186 !device_iommu_capable(&pdev->dev, IOMMU_CAP_PRE_BOOT_PROTECTION)) 1187 return 0; 1188 *(bool *)data = true; 1189 return 1; /* Stop walking */ 1190 } 1191 nhi_check_iommu(struct tb_nhi * nhi)1192 static void nhi_check_iommu(struct tb_nhi *nhi) 1193 { 1194 struct pci_bus *bus = nhi->pdev->bus; 1195 bool port_ok = false; 1196 1197 /* 1198 * Ideally what we'd do here is grab every PCI device that 1199 * represents a tunnelling adapter for this NHI and check their 1200 * status directly, but unfortunately USB4 seems to make it 1201 * obnoxiously difficult to reliably make any correlation. 1202 * 1203 * So for now we'll have to bodge it... Hoping that the system 1204 * is at least sane enough that an adapter is in the same PCI 1205 * segment as its NHI, if we can find *something* on that segment 1206 * which meets the requirements for Kernel DMA Protection, we'll 1207 * take that to imply that firmware is aware and has (hopefully) 1208 * done the right thing in general. We need to know that the PCI 1209 * layer has seen the ExternalFacingPort property which will then 1210 * inform the IOMMU layer to enforce the complete "untrusted DMA" 1211 * flow, but also that the IOMMU driver itself can be trusted not 1212 * to have been subverted by a pre-boot DMA attack. 1213 */ 1214 while (bus->parent) 1215 bus = bus->parent; 1216 1217 pci_walk_bus(bus, nhi_check_iommu_pdev, &port_ok); 1218 1219 nhi->iommu_dma_protection = port_ok; 1220 dev_dbg(&nhi->pdev->dev, "IOMMU DMA protection is %s\n", 1221 str_enabled_disabled(port_ok)); 1222 } 1223 nhi_reset(struct tb_nhi * nhi)1224 static bool nhi_reset(struct tb_nhi *nhi) 1225 { 1226 ktime_t timeout; 1227 u32 val; 1228 1229 val = ioread32(nhi->iobase + REG_CAPS); 1230 /* Reset only v2 and later routers */ 1231 if (FIELD_GET(REG_CAPS_VERSION_MASK, val) < REG_CAPS_VERSION_2) 1232 return false; 1233 1234 if (!host_reset) { 1235 dev_dbg(&nhi->pdev->dev, "skipping host router reset\n"); 1236 return false; 1237 } 1238 1239 iowrite32(REG_RESET_HRR, nhi->iobase + REG_RESET); 1240 msleep(100); 1241 1242 timeout = ktime_add_ms(ktime_get(), 500); 1243 do { 1244 val = ioread32(nhi->iobase + REG_RESET); 1245 if (!(val & REG_RESET_HRR)) { 1246 dev_warn(&nhi->pdev->dev, "host router reset successful\n"); 1247 return true; 1248 } 1249 usleep_range(10, 20); 1250 } while (ktime_before(ktime_get(), timeout)); 1251 1252 dev_warn(&nhi->pdev->dev, "timeout resetting host router\n"); 1253 1254 return false; 1255 } 1256 nhi_init_msi(struct tb_nhi * nhi)1257 static int nhi_init_msi(struct tb_nhi *nhi) 1258 { 1259 struct pci_dev *pdev = nhi->pdev; 1260 struct device *dev = &pdev->dev; 1261 int res, irq, nvec; 1262 1263 /* In case someone left them on. */ 1264 nhi_disable_interrupts(nhi); 1265 1266 nhi_enable_int_throttling(nhi); 1267 1268 ida_init(&nhi->msix_ida); 1269 1270 /* 1271 * The NHI has 16 MSI-X vectors or a single MSI. We first try to 1272 * get all MSI-X vectors and if we succeed, each ring will have 1273 * one MSI-X. If for some reason that does not work out, we 1274 * fallback to a single MSI. 1275 */ 1276 nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS, 1277 PCI_IRQ_MSIX); 1278 if (nvec < 0) { 1279 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1280 if (nvec < 0) 1281 return nvec; 1282 1283 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work); 1284 1285 irq = pci_irq_vector(nhi->pdev, 0); 1286 if (irq < 0) 1287 return irq; 1288 1289 res = devm_request_irq(&pdev->dev, irq, nhi_msi, 1290 IRQF_NO_SUSPEND, "thunderbolt", nhi); 1291 if (res) 1292 return dev_err_probe(dev, res, "request_irq failed, aborting\n"); 1293 } 1294 1295 return 0; 1296 } 1297 nhi_imr_valid(struct pci_dev * pdev)1298 static bool nhi_imr_valid(struct pci_dev *pdev) 1299 { 1300 u8 val; 1301 1302 if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val)) 1303 return !!val; 1304 1305 return true; 1306 } 1307 nhi_select_cm(struct tb_nhi * nhi)1308 static struct tb *nhi_select_cm(struct tb_nhi *nhi) 1309 { 1310 struct tb *tb; 1311 1312 /* 1313 * USB4 case is simple. If we got control of any of the 1314 * capabilities, we use software CM. 1315 */ 1316 if (tb_acpi_is_native()) 1317 return tb_probe(nhi); 1318 1319 /* 1320 * Either firmware based CM is running (we did not get control 1321 * from the firmware) or this is pre-USB4 PC so try first 1322 * firmware CM and then fallback to software CM. 1323 */ 1324 tb = icm_probe(nhi); 1325 if (!tb) 1326 tb = tb_probe(nhi); 1327 1328 return tb; 1329 } 1330 nhi_probe(struct pci_dev * pdev,const struct pci_device_id * id)1331 static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1332 { 1333 struct device *dev = &pdev->dev; 1334 struct tb_nhi *nhi; 1335 struct tb *tb; 1336 bool reset; 1337 int res; 1338 1339 if (!nhi_imr_valid(pdev)) 1340 return dev_err_probe(dev, -ENODEV, "firmware image not valid, aborting\n"); 1341 1342 res = pcim_enable_device(pdev); 1343 if (res) 1344 return dev_err_probe(dev, res, "cannot enable PCI device, aborting\n"); 1345 1346 res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt"); 1347 if (res) 1348 return dev_err_probe(dev, res, "cannot obtain PCI resources, aborting\n"); 1349 1350 nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL); 1351 if (!nhi) 1352 return -ENOMEM; 1353 1354 nhi->pdev = pdev; 1355 nhi->ops = (const struct tb_nhi_ops *)id->driver_data; 1356 /* cannot fail - table is allocated in pcim_iomap_regions */ 1357 nhi->iobase = pcim_iomap_table(pdev)[0]; 1358 nhi->hop_count = ioread32(nhi->iobase + REG_CAPS) & 0x3ff; 1359 dev_dbg(dev, "total paths: %d\n", nhi->hop_count); 1360 1361 nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count, 1362 sizeof(*nhi->tx_rings), GFP_KERNEL); 1363 nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count, 1364 sizeof(*nhi->rx_rings), GFP_KERNEL); 1365 if (!nhi->tx_rings || !nhi->rx_rings) 1366 return -ENOMEM; 1367 1368 nhi_check_quirks(nhi); 1369 nhi_check_iommu(nhi); 1370 1371 /* 1372 * Only USB4 v2 hosts support host reset so if we already did 1373 * that then don't do it again when the domain is initialized. 1374 */ 1375 reset = nhi_reset(nhi) ? false : host_reset; 1376 1377 res = nhi_init_msi(nhi); 1378 if (res) 1379 return dev_err_probe(dev, res, "cannot enable MSI, aborting\n"); 1380 1381 spin_lock_init(&nhi->lock); 1382 1383 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1384 if (res) 1385 return dev_err_probe(dev, res, "failed to set DMA mask\n"); 1386 1387 pci_set_master(pdev); 1388 1389 if (nhi->ops && nhi->ops->init) { 1390 res = nhi->ops->init(nhi); 1391 if (res) 1392 return res; 1393 } 1394 1395 tb = nhi_select_cm(nhi); 1396 if (!tb) 1397 return dev_err_probe(dev, -ENODEV, 1398 "failed to determine connection manager, aborting\n"); 1399 1400 dev_dbg(dev, "NHI initialized, starting thunderbolt\n"); 1401 1402 res = tb_domain_add(tb, reset); 1403 if (res) { 1404 /* 1405 * At this point the RX/TX rings might already have been 1406 * activated. Do a proper shutdown. 1407 */ 1408 tb_domain_put(tb); 1409 nhi_shutdown(nhi); 1410 return res; 1411 } 1412 pci_set_drvdata(pdev, tb); 1413 1414 device_wakeup_enable(&pdev->dev); 1415 1416 pm_runtime_allow(&pdev->dev); 1417 pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY); 1418 pm_runtime_use_autosuspend(&pdev->dev); 1419 pm_runtime_put_autosuspend(&pdev->dev); 1420 1421 return 0; 1422 } 1423 nhi_remove(struct pci_dev * pdev)1424 static void nhi_remove(struct pci_dev *pdev) 1425 { 1426 struct tb *tb = pci_get_drvdata(pdev); 1427 struct tb_nhi *nhi = tb->nhi; 1428 1429 pm_runtime_get_sync(&pdev->dev); 1430 pm_runtime_dont_use_autosuspend(&pdev->dev); 1431 pm_runtime_forbid(&pdev->dev); 1432 1433 tb_domain_remove(tb); 1434 nhi_shutdown(nhi); 1435 } 1436 1437 /* 1438 * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable 1439 * the tunnels asap. A corresponding pci quirk blocks the downstream bridges 1440 * resume_noirq until we are done. 1441 */ 1442 static const struct dev_pm_ops nhi_pm_ops = { 1443 .suspend_noirq = nhi_suspend_noirq, 1444 .resume_noirq = nhi_resume_noirq, 1445 .freeze_noirq = nhi_freeze_noirq, /* 1446 * we just disable hotplug, the 1447 * pci-tunnels stay alive. 1448 */ 1449 .thaw_noirq = nhi_thaw_noirq, 1450 .restore_noirq = nhi_resume_noirq, 1451 .suspend = nhi_suspend, 1452 .poweroff_noirq = nhi_poweroff_noirq, 1453 .poweroff = nhi_suspend, 1454 .complete = nhi_complete, 1455 .runtime_suspend = nhi_runtime_suspend, 1456 .runtime_resume = nhi_runtime_resume, 1457 }; 1458 1459 static struct pci_device_id nhi_ids[] = { 1460 /* 1461 * We have to specify class, the TB bridges use the same device and 1462 * vendor (sub)id on gen 1 and gen 2 controllers. 1463 */ 1464 { 1465 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1466 .vendor = PCI_VENDOR_ID_INTEL, 1467 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 1468 .subvendor = 0x2222, .subdevice = 0x1111, 1469 }, 1470 { 1471 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1472 .vendor = PCI_VENDOR_ID_INTEL, 1473 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 1474 .subvendor = 0x2222, .subdevice = 0x1111, 1475 }, 1476 { 1477 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1478 .vendor = PCI_VENDOR_ID_INTEL, 1479 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI, 1480 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 1481 }, 1482 { 1483 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1484 .vendor = PCI_VENDOR_ID_INTEL, 1485 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI, 1486 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 1487 }, 1488 1489 /* Thunderbolt 3 */ 1490 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) }, 1491 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) }, 1492 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) }, 1493 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) }, 1494 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) }, 1495 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) }, 1496 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) }, 1497 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) }, 1498 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) }, 1499 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) }, 1500 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0), 1501 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1502 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1), 1503 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1504 /* Thunderbolt 4 */ 1505 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0), 1506 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1507 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1), 1508 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1509 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0), 1510 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1511 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1), 1512 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1513 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI0), 1514 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1515 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ADL_NHI1), 1516 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1517 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI0), 1518 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1519 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_RPL_NHI1), 1520 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1521 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_M_NHI0), 1522 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1523 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI0), 1524 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1525 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MTL_P_NHI1), 1526 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1527 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI) }, 1528 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI) }, 1529 1530 /* Any USB4 compliant host */ 1531 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) }, 1532 1533 { 0,} 1534 }; 1535 1536 MODULE_DEVICE_TABLE(pci, nhi_ids); 1537 MODULE_DESCRIPTION("Thunderbolt/USB4 core driver"); 1538 MODULE_LICENSE("GPL"); 1539 1540 static struct pci_driver nhi_driver = { 1541 .name = "thunderbolt", 1542 .id_table = nhi_ids, 1543 .probe = nhi_probe, 1544 .remove = nhi_remove, 1545 .shutdown = nhi_remove, 1546 .driver.pm = &nhi_pm_ops, 1547 }; 1548 nhi_init(void)1549 static int __init nhi_init(void) 1550 { 1551 int ret; 1552 1553 ret = tb_domain_init(); 1554 if (ret) 1555 return ret; 1556 ret = pci_register_driver(&nhi_driver); 1557 if (ret) 1558 tb_domain_exit(); 1559 return ret; 1560 } 1561 nhi_unload(void)1562 static void __exit nhi_unload(void) 1563 { 1564 pci_unregister_driver(&nhi_driver); 1565 tb_domain_exit(); 1566 } 1567 1568 rootfs_initcall(nhi_init); 1569 module_exit(nhi_unload); 1570