1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Thunderbolt link controller support 4 * 5 * Copyright (C) 2019, Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 */ 8 9 #include "tb.h" 10 11 /** 12 * tb_lc_read_uuid() - Read switch UUID from link controller common register 13 * @sw: Switch whose UUID is read 14 * @uuid: UUID is placed here 15 */ 16 int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid) 17 { 18 if (!sw->cap_lc) 19 return -EINVAL; 20 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4); 21 } 22 23 static int read_lc_desc(struct tb_switch *sw, u32 *desc) 24 { 25 if (!sw->cap_lc) 26 return -EINVAL; 27 return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1); 28 } 29 30 static int find_port_lc_cap(struct tb_port *port) 31 { 32 struct tb_switch *sw = port->sw; 33 int start, phys, ret, size; 34 u32 desc; 35 36 ret = read_lc_desc(sw, &desc); 37 if (ret) 38 return ret; 39 40 /* Start of port LC registers */ 41 start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT; 42 size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT; 43 phys = tb_phy_port_from_link(port->port); 44 45 return sw->cap_lc + start + phys * size; 46 } 47 48 static int tb_lc_set_port_configured(struct tb_port *port, bool configured) 49 { 50 bool upstream = tb_is_upstream_port(port); 51 struct tb_switch *sw = port->sw; 52 u32 ctrl, lane; 53 int cap, ret; 54 55 if (sw->generation < 2) 56 return 0; 57 58 cap = find_port_lc_cap(port); 59 if (cap < 0) 60 return cap; 61 62 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1); 63 if (ret) 64 return ret; 65 66 /* Resolve correct lane */ 67 if (port->port % 2) 68 lane = TB_LC_SX_CTRL_L1C; 69 else 70 lane = TB_LC_SX_CTRL_L2C; 71 72 if (configured) { 73 ctrl |= lane; 74 if (upstream) 75 ctrl |= TB_LC_SX_CTRL_UPSTREAM; 76 } else { 77 ctrl &= ~lane; 78 if (upstream) 79 ctrl &= ~TB_LC_SX_CTRL_UPSTREAM; 80 } 81 82 return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1); 83 } 84 85 /** 86 * tb_lc_configure_port() - Let LC know about configured port 87 * @port: Port that is set as configured 88 * 89 * Sets the port configured for power management purposes. 90 */ 91 int tb_lc_configure_port(struct tb_port *port) 92 { 93 return tb_lc_set_port_configured(port, true); 94 } 95 96 /** 97 * tb_lc_unconfigure_port() - Let LC know about unconfigured port 98 * @port: Port that is set as configured 99 * 100 * Sets the port unconfigured for power management purposes. 101 */ 102 void tb_lc_unconfigure_port(struct tb_port *port) 103 { 104 tb_lc_set_port_configured(port, false); 105 } 106 107 /** 108 * tb_lc_set_sleep() - Inform LC that the switch is going to sleep 109 * @sw: Switch to set sleep 110 * 111 * Let the switch link controllers know that the switch is going to 112 * sleep. 113 */ 114 int tb_lc_set_sleep(struct tb_switch *sw) 115 { 116 int start, size, nlc, ret, i; 117 u32 desc; 118 119 if (sw->generation < 2) 120 return 0; 121 122 ret = read_lc_desc(sw, &desc); 123 if (ret) 124 return ret; 125 126 /* Figure out number of link controllers */ 127 nlc = desc & TB_LC_DESC_NLC_MASK; 128 start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT; 129 size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT; 130 131 /* For each link controller set sleep bit */ 132 for (i = 0; i < nlc; i++) { 133 unsigned int offset = sw->cap_lc + start + i * size; 134 u32 ctrl; 135 136 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, 137 offset + TB_LC_SX_CTRL, 1); 138 if (ret) 139 return ret; 140 141 ctrl |= TB_LC_SX_CTRL_SLP; 142 ret = tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, 143 offset + TB_LC_SX_CTRL, 1); 144 if (ret) 145 return ret; 146 } 147 148 return 0; 149 } 150 151 /** 152 * tb_lc_lane_bonding_possible() - Is lane bonding possible towards switch 153 * @sw: Switch to check 154 * 155 * Checks whether conditions for lane bonding from parent to @sw are 156 * possible. 157 */ 158 bool tb_lc_lane_bonding_possible(struct tb_switch *sw) 159 { 160 struct tb_port *up; 161 int cap, ret; 162 u32 val; 163 164 if (sw->generation < 2) 165 return false; 166 167 up = tb_upstream_port(sw); 168 cap = find_port_lc_cap(up); 169 if (cap < 0) 170 return false; 171 172 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_PORT_ATTR, 1); 173 if (ret) 174 return false; 175 176 return !!(val & TB_LC_PORT_ATTR_BE); 177 } 178 179 static int tb_lc_dp_sink_from_port(const struct tb_switch *sw, 180 struct tb_port *in) 181 { 182 struct tb_port *port; 183 184 /* The first DP IN port is sink 0 and second is sink 1 */ 185 tb_switch_for_each_port(sw, port) { 186 if (tb_port_is_dpin(port)) 187 return in != port; 188 } 189 190 return -EINVAL; 191 } 192 193 static int tb_lc_dp_sink_available(struct tb_switch *sw, int sink) 194 { 195 u32 val, alloc; 196 int ret; 197 198 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, 199 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1); 200 if (ret) 201 return ret; 202 203 /* 204 * Sink is available for CM/SW to use if the allocation valie is 205 * either 0 or 1. 206 */ 207 if (!sink) { 208 alloc = val & TB_LC_SNK_ALLOCATION_SNK0_MASK; 209 if (!alloc || alloc == TB_LC_SNK_ALLOCATION_SNK0_CM) 210 return 0; 211 } else { 212 alloc = (val & TB_LC_SNK_ALLOCATION_SNK1_MASK) >> 213 TB_LC_SNK_ALLOCATION_SNK1_SHIFT; 214 if (!alloc || alloc == TB_LC_SNK_ALLOCATION_SNK1_CM) 215 return 0; 216 } 217 218 return -EBUSY; 219 } 220 221 /** 222 * tb_lc_dp_sink_query() - Is DP sink available for DP IN port 223 * @sw: Switch whose DP sink is queried 224 * @in: DP IN port to check 225 * 226 * Queries through LC SNK_ALLOCATION registers whether DP sink is available 227 * for the given DP IN port or not. 228 */ 229 bool tb_lc_dp_sink_query(struct tb_switch *sw, struct tb_port *in) 230 { 231 int sink; 232 233 /* 234 * For older generations sink is always available as there is no 235 * allocation mechanism. 236 */ 237 if (sw->generation < 3) 238 return true; 239 240 sink = tb_lc_dp_sink_from_port(sw, in); 241 if (sink < 0) 242 return false; 243 244 return !tb_lc_dp_sink_available(sw, sink); 245 } 246 247 /** 248 * tb_lc_dp_sink_alloc() - Allocate DP sink 249 * @sw: Switch whose DP sink is allocated 250 * @in: DP IN port the DP sink is allocated for 251 * 252 * Allocate DP sink for @in via LC SNK_ALLOCATION registers. If the 253 * resource is available and allocation is successful returns %0. In all 254 * other cases returs negative errno. In particular %-EBUSY is returned if 255 * the resource was not available. 256 */ 257 int tb_lc_dp_sink_alloc(struct tb_switch *sw, struct tb_port *in) 258 { 259 int ret, sink; 260 u32 val; 261 262 if (sw->generation < 3) 263 return 0; 264 265 sink = tb_lc_dp_sink_from_port(sw, in); 266 if (sink < 0) 267 return sink; 268 269 ret = tb_lc_dp_sink_available(sw, sink); 270 if (ret) 271 return ret; 272 273 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, 274 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1); 275 if (ret) 276 return ret; 277 278 if (!sink) { 279 val &= ~TB_LC_SNK_ALLOCATION_SNK0_MASK; 280 val |= TB_LC_SNK_ALLOCATION_SNK0_CM; 281 } else { 282 val &= ~TB_LC_SNK_ALLOCATION_SNK1_MASK; 283 val |= TB_LC_SNK_ALLOCATION_SNK1_CM << 284 TB_LC_SNK_ALLOCATION_SNK1_SHIFT; 285 } 286 287 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, 288 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1); 289 290 if (ret) 291 return ret; 292 293 tb_port_dbg(in, "sink %d allocated\n", sink); 294 return 0; 295 } 296 297 /** 298 * tb_lc_dp_sink_dealloc() - De-allocate DP sink 299 * @sw: Switch whose DP sink is de-allocated 300 * @in: DP IN port whose DP sink is de-allocated 301 * 302 * De-allocate DP sink from @in using LC SNK_ALLOCATION registers. 303 */ 304 int tb_lc_dp_sink_dealloc(struct tb_switch *sw, struct tb_port *in) 305 { 306 int ret, sink; 307 u32 val; 308 309 if (sw->generation < 3) 310 return 0; 311 312 sink = tb_lc_dp_sink_from_port(sw, in); 313 if (sink < 0) 314 return sink; 315 316 /* Needs to be owned by CM/SW */ 317 ret = tb_lc_dp_sink_available(sw, sink); 318 if (ret) 319 return ret; 320 321 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, 322 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1); 323 if (ret) 324 return ret; 325 326 if (!sink) 327 val &= ~TB_LC_SNK_ALLOCATION_SNK0_MASK; 328 else 329 val &= ~TB_LC_SNK_ALLOCATION_SNK1_MASK; 330 331 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, 332 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1); 333 if (ret) 334 return ret; 335 336 tb_port_dbg(in, "sink %d de-allocated\n", sink); 337 return 0; 338 } 339 340 /** 341 * tb_lc_force_power() - Forces LC to be powered on 342 * @sw: Thunderbolt switch 343 * 344 * This is useful to let authentication cycle pass even without 345 * a Thunderbolt link present. 346 */ 347 int tb_lc_force_power(struct tb_switch *sw) 348 { 349 u32 in = 0xffff; 350 351 return tb_sw_write(sw, &in, TB_CFG_SWITCH, TB_LC_POWER, 1); 352 } 353