1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Thunderbolt link controller support 4 * 5 * Copyright (C) 2019, Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 */ 8 9 #include "tb.h" 10 11 /** 12 * tb_lc_read_uuid() - Read switch UUID from link controller common register 13 * @sw: Switch whose UUID is read 14 * @uuid: UUID is placed here 15 */ 16 int tb_lc_read_uuid(struct tb_switch *sw, u32 *uuid) 17 { 18 if (!sw->cap_lc) 19 return -EINVAL; 20 return tb_sw_read(sw, uuid, TB_CFG_SWITCH, sw->cap_lc + TB_LC_FUSE, 4); 21 } 22 23 static int read_lc_desc(struct tb_switch *sw, u32 *desc) 24 { 25 if (!sw->cap_lc) 26 return -EINVAL; 27 return tb_sw_read(sw, desc, TB_CFG_SWITCH, sw->cap_lc + TB_LC_DESC, 1); 28 } 29 30 static int find_port_lc_cap(struct tb_port *port) 31 { 32 struct tb_switch *sw = port->sw; 33 int start, phys, ret, size; 34 u32 desc; 35 36 ret = read_lc_desc(sw, &desc); 37 if (ret) 38 return ret; 39 40 /* Start of port LC registers */ 41 start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT; 42 size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT; 43 phys = tb_phy_port_from_link(port->port); 44 45 return sw->cap_lc + start + phys * size; 46 } 47 48 static int tb_lc_set_port_configured(struct tb_port *port, bool configured) 49 { 50 bool upstream = tb_is_upstream_port(port); 51 struct tb_switch *sw = port->sw; 52 u32 ctrl, lane; 53 int cap, ret; 54 55 if (sw->generation < 2) 56 return 0; 57 58 cap = find_port_lc_cap(port); 59 if (cap < 0) 60 return cap; 61 62 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1); 63 if (ret) 64 return ret; 65 66 /* Resolve correct lane */ 67 if (port->port % 2) 68 lane = TB_LC_SX_CTRL_L1C; 69 else 70 lane = TB_LC_SX_CTRL_L2C; 71 72 if (configured) { 73 ctrl |= lane; 74 if (upstream) 75 ctrl |= TB_LC_SX_CTRL_UPSTREAM; 76 } else { 77 ctrl &= ~lane; 78 if (upstream) 79 ctrl &= ~TB_LC_SX_CTRL_UPSTREAM; 80 } 81 82 return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1); 83 } 84 85 /** 86 * tb_lc_configure_port() - Let LC know about configured port 87 * @port: Port that is set as configured 88 * 89 * Sets the port configured for power management purposes. 90 */ 91 int tb_lc_configure_port(struct tb_port *port) 92 { 93 return tb_lc_set_port_configured(port, true); 94 } 95 96 /** 97 * tb_lc_unconfigure_port() - Let LC know about unconfigured port 98 * @port: Port that is set as configured 99 * 100 * Sets the port unconfigured for power management purposes. 101 */ 102 void tb_lc_unconfigure_port(struct tb_port *port) 103 { 104 tb_lc_set_port_configured(port, false); 105 } 106 107 static int tb_lc_set_xdomain_configured(struct tb_port *port, bool configure) 108 { 109 struct tb_switch *sw = port->sw; 110 u32 ctrl, lane; 111 int cap, ret; 112 113 if (sw->generation < 2) 114 return 0; 115 116 cap = find_port_lc_cap(port); 117 if (cap < 0) 118 return cap; 119 120 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1); 121 if (ret) 122 return ret; 123 124 /* Resolve correct lane */ 125 if (port->port % 2) 126 lane = TB_LC_SX_CTRL_L1D; 127 else 128 lane = TB_LC_SX_CTRL_L2D; 129 130 if (configure) 131 ctrl |= lane; 132 else 133 ctrl &= ~lane; 134 135 return tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, cap + TB_LC_SX_CTRL, 1); 136 } 137 138 /** 139 * tb_lc_configure_xdomain() - Inform LC that the link is XDomain 140 * @port: Switch downstream port connected to another host 141 * 142 * Sets the lane configured for XDomain accordingly so that the LC knows 143 * about this. Returns %0 in success and negative errno in failure. 144 */ 145 int tb_lc_configure_xdomain(struct tb_port *port) 146 { 147 return tb_lc_set_xdomain_configured(port, true); 148 } 149 150 /** 151 * tb_lc_unconfigure_xdomain() - Unconfigure XDomain from port 152 * @port: Switch downstream port that was connected to another host 153 * 154 * Unsets the lane XDomain configuration. 155 */ 156 void tb_lc_unconfigure_xdomain(struct tb_port *port) 157 { 158 tb_lc_set_xdomain_configured(port, false); 159 } 160 161 /** 162 * tb_lc_set_sleep() - Inform LC that the switch is going to sleep 163 * @sw: Switch to set sleep 164 * 165 * Let the switch link controllers know that the switch is going to 166 * sleep. 167 */ 168 int tb_lc_set_sleep(struct tb_switch *sw) 169 { 170 int start, size, nlc, ret, i; 171 u32 desc; 172 173 if (sw->generation < 2) 174 return 0; 175 176 ret = read_lc_desc(sw, &desc); 177 if (ret) 178 return ret; 179 180 /* Figure out number of link controllers */ 181 nlc = desc & TB_LC_DESC_NLC_MASK; 182 start = (desc & TB_LC_DESC_SIZE_MASK) >> TB_LC_DESC_SIZE_SHIFT; 183 size = (desc & TB_LC_DESC_PORT_SIZE_MASK) >> TB_LC_DESC_PORT_SIZE_SHIFT; 184 185 /* For each link controller set sleep bit */ 186 for (i = 0; i < nlc; i++) { 187 unsigned int offset = sw->cap_lc + start + i * size; 188 u32 ctrl; 189 190 ret = tb_sw_read(sw, &ctrl, TB_CFG_SWITCH, 191 offset + TB_LC_SX_CTRL, 1); 192 if (ret) 193 return ret; 194 195 ctrl |= TB_LC_SX_CTRL_SLP; 196 ret = tb_sw_write(sw, &ctrl, TB_CFG_SWITCH, 197 offset + TB_LC_SX_CTRL, 1); 198 if (ret) 199 return ret; 200 } 201 202 return 0; 203 } 204 205 /** 206 * tb_lc_lane_bonding_possible() - Is lane bonding possible towards switch 207 * @sw: Switch to check 208 * 209 * Checks whether conditions for lane bonding from parent to @sw are 210 * possible. 211 */ 212 bool tb_lc_lane_bonding_possible(struct tb_switch *sw) 213 { 214 struct tb_port *up; 215 int cap, ret; 216 u32 val; 217 218 if (sw->generation < 2) 219 return false; 220 221 up = tb_upstream_port(sw); 222 cap = find_port_lc_cap(up); 223 if (cap < 0) 224 return false; 225 226 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, cap + TB_LC_PORT_ATTR, 1); 227 if (ret) 228 return false; 229 230 return !!(val & TB_LC_PORT_ATTR_BE); 231 } 232 233 static int tb_lc_dp_sink_from_port(const struct tb_switch *sw, 234 struct tb_port *in) 235 { 236 struct tb_port *port; 237 238 /* The first DP IN port is sink 0 and second is sink 1 */ 239 tb_switch_for_each_port(sw, port) { 240 if (tb_port_is_dpin(port)) 241 return in != port; 242 } 243 244 return -EINVAL; 245 } 246 247 static int tb_lc_dp_sink_available(struct tb_switch *sw, int sink) 248 { 249 u32 val, alloc; 250 int ret; 251 252 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, 253 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1); 254 if (ret) 255 return ret; 256 257 /* 258 * Sink is available for CM/SW to use if the allocation valie is 259 * either 0 or 1. 260 */ 261 if (!sink) { 262 alloc = val & TB_LC_SNK_ALLOCATION_SNK0_MASK; 263 if (!alloc || alloc == TB_LC_SNK_ALLOCATION_SNK0_CM) 264 return 0; 265 } else { 266 alloc = (val & TB_LC_SNK_ALLOCATION_SNK1_MASK) >> 267 TB_LC_SNK_ALLOCATION_SNK1_SHIFT; 268 if (!alloc || alloc == TB_LC_SNK_ALLOCATION_SNK1_CM) 269 return 0; 270 } 271 272 return -EBUSY; 273 } 274 275 /** 276 * tb_lc_dp_sink_query() - Is DP sink available for DP IN port 277 * @sw: Switch whose DP sink is queried 278 * @in: DP IN port to check 279 * 280 * Queries through LC SNK_ALLOCATION registers whether DP sink is available 281 * for the given DP IN port or not. 282 */ 283 bool tb_lc_dp_sink_query(struct tb_switch *sw, struct tb_port *in) 284 { 285 int sink; 286 287 /* 288 * For older generations sink is always available as there is no 289 * allocation mechanism. 290 */ 291 if (sw->generation < 3) 292 return true; 293 294 sink = tb_lc_dp_sink_from_port(sw, in); 295 if (sink < 0) 296 return false; 297 298 return !tb_lc_dp_sink_available(sw, sink); 299 } 300 301 /** 302 * tb_lc_dp_sink_alloc() - Allocate DP sink 303 * @sw: Switch whose DP sink is allocated 304 * @in: DP IN port the DP sink is allocated for 305 * 306 * Allocate DP sink for @in via LC SNK_ALLOCATION registers. If the 307 * resource is available and allocation is successful returns %0. In all 308 * other cases returs negative errno. In particular %-EBUSY is returned if 309 * the resource was not available. 310 */ 311 int tb_lc_dp_sink_alloc(struct tb_switch *sw, struct tb_port *in) 312 { 313 int ret, sink; 314 u32 val; 315 316 if (sw->generation < 3) 317 return 0; 318 319 sink = tb_lc_dp_sink_from_port(sw, in); 320 if (sink < 0) 321 return sink; 322 323 ret = tb_lc_dp_sink_available(sw, sink); 324 if (ret) 325 return ret; 326 327 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, 328 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1); 329 if (ret) 330 return ret; 331 332 if (!sink) { 333 val &= ~TB_LC_SNK_ALLOCATION_SNK0_MASK; 334 val |= TB_LC_SNK_ALLOCATION_SNK0_CM; 335 } else { 336 val &= ~TB_LC_SNK_ALLOCATION_SNK1_MASK; 337 val |= TB_LC_SNK_ALLOCATION_SNK1_CM << 338 TB_LC_SNK_ALLOCATION_SNK1_SHIFT; 339 } 340 341 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, 342 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1); 343 344 if (ret) 345 return ret; 346 347 tb_port_dbg(in, "sink %d allocated\n", sink); 348 return 0; 349 } 350 351 /** 352 * tb_lc_dp_sink_dealloc() - De-allocate DP sink 353 * @sw: Switch whose DP sink is de-allocated 354 * @in: DP IN port whose DP sink is de-allocated 355 * 356 * De-allocate DP sink from @in using LC SNK_ALLOCATION registers. 357 */ 358 int tb_lc_dp_sink_dealloc(struct tb_switch *sw, struct tb_port *in) 359 { 360 int ret, sink; 361 u32 val; 362 363 if (sw->generation < 3) 364 return 0; 365 366 sink = tb_lc_dp_sink_from_port(sw, in); 367 if (sink < 0) 368 return sink; 369 370 /* Needs to be owned by CM/SW */ 371 ret = tb_lc_dp_sink_available(sw, sink); 372 if (ret) 373 return ret; 374 375 ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, 376 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1); 377 if (ret) 378 return ret; 379 380 if (!sink) 381 val &= ~TB_LC_SNK_ALLOCATION_SNK0_MASK; 382 else 383 val &= ~TB_LC_SNK_ALLOCATION_SNK1_MASK; 384 385 ret = tb_sw_write(sw, &val, TB_CFG_SWITCH, 386 sw->cap_lc + TB_LC_SNK_ALLOCATION, 1); 387 if (ret) 388 return ret; 389 390 tb_port_dbg(in, "sink %d de-allocated\n", sink); 391 return 0; 392 } 393 394 /** 395 * tb_lc_force_power() - Forces LC to be powered on 396 * @sw: Thunderbolt switch 397 * 398 * This is useful to let authentication cycle pass even without 399 * a Thunderbolt link present. 400 */ 401 int tb_lc_force_power(struct tb_switch *sw) 402 { 403 u32 in = 0xffff; 404 405 return tb_sw_write(sw, &in, TB_CFG_SWITCH, TB_LC_POWER, 1); 406 } 407