1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * DRA752 bandgap registers, bitfields and temperature definitions 4 * 5 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 6 * Contact: 7 * Eduardo Valentin <eduardo.valentin@ti.com> 8 * Tero Kristo <t-kristo@ti.com> 9 * 10 * This is an auto generated file. 11 */ 12 #ifndef __DRA752_BANDGAP_H 13 #define __DRA752_BANDGAP_H 14 15 /** 16 * *** DRA752 *** 17 * 18 * Below, in sequence, are the Register definitions, 19 * the bitfields and the temperature definitions for DRA752. 20 */ 21 22 /** 23 * DRA752 register definitions 24 * 25 * Registers are defined as offsets. The offsets are 26 * relative to FUSE_OPP_BGAP_GPU on DRA752. 27 * DRA752_BANDGAP_BASE 0x4a0021e0 28 * 29 * Register below are grouped by domain (not necessarily in offset order) 30 */ 31 32 33 /* DRA752.common register offsets */ 34 #define DRA752_BANDGAP_CTRL_1_OFFSET 0x1a0 35 #define DRA752_BANDGAP_STATUS_1_OFFSET 0x1c8 36 #define DRA752_BANDGAP_CTRL_2_OFFSET 0x39c 37 #define DRA752_BANDGAP_STATUS_2_OFFSET 0x3b8 38 39 /* DRA752.core register offsets */ 40 #define DRA752_STD_FUSE_OPP_BGAP_CORE_OFFSET 0x8 41 #define DRA752_TEMP_SENSOR_CORE_OFFSET 0x154 42 #define DRA752_BANDGAP_THRESHOLD_CORE_OFFSET 0x1ac 43 #define DRA752_DTEMP_CORE_1_OFFSET 0x20c 44 #define DRA752_DTEMP_CORE_2_OFFSET 0x210 45 46 /* DRA752.iva register offsets */ 47 #define DRA752_STD_FUSE_OPP_BGAP_IVA_OFFSET 0x388 48 #define DRA752_TEMP_SENSOR_IVA_OFFSET 0x398 49 #define DRA752_BANDGAP_THRESHOLD_IVA_OFFSET 0x3a4 50 #define DRA752_DTEMP_IVA_1_OFFSET 0x3d4 51 #define DRA752_DTEMP_IVA_2_OFFSET 0x3d8 52 53 /* DRA752.mpu register offsets */ 54 #define DRA752_STD_FUSE_OPP_BGAP_MPU_OFFSET 0x4 55 #define DRA752_TEMP_SENSOR_MPU_OFFSET 0x14c 56 #define DRA752_BANDGAP_THRESHOLD_MPU_OFFSET 0x1a4 57 #define DRA752_DTEMP_MPU_1_OFFSET 0x1e4 58 #define DRA752_DTEMP_MPU_2_OFFSET 0x1e8 59 60 /* DRA752.dspeve register offsets */ 61 #define DRA752_STD_FUSE_OPP_BGAP_DSPEVE_OFFSET 0x384 62 #define DRA752_TEMP_SENSOR_DSPEVE_OFFSET 0x394 63 #define DRA752_BANDGAP_THRESHOLD_DSPEVE_OFFSET 0x3a0 64 #define DRA752_DTEMP_DSPEVE_1_OFFSET 0x3c0 65 #define DRA752_DTEMP_DSPEVE_2_OFFSET 0x3c4 66 67 /* DRA752.gpu register offsets */ 68 #define DRA752_STD_FUSE_OPP_BGAP_GPU_OFFSET 0x0 69 #define DRA752_TEMP_SENSOR_GPU_OFFSET 0x150 70 #define DRA752_BANDGAP_THRESHOLD_GPU_OFFSET 0x1a8 71 #define DRA752_DTEMP_GPU_1_OFFSET 0x1f8 72 #define DRA752_DTEMP_GPU_2_OFFSET 0x1fc 73 74 /** 75 * Register bitfields for DRA752 76 * 77 * All the macros bellow define the required bits for 78 * controlling temperature on DRA752. Bit defines are 79 * grouped by register. 80 */ 81 82 /* DRA752.BANDGAP_STATUS_1 */ 83 #define DRA752_BANDGAP_STATUS_1_HOT_CORE_MASK BIT(5) 84 #define DRA752_BANDGAP_STATUS_1_COLD_CORE_MASK BIT(4) 85 #define DRA752_BANDGAP_STATUS_1_HOT_GPU_MASK BIT(3) 86 #define DRA752_BANDGAP_STATUS_1_COLD_GPU_MASK BIT(2) 87 #define DRA752_BANDGAP_STATUS_1_HOT_MPU_MASK BIT(1) 88 #define DRA752_BANDGAP_STATUS_1_COLD_MPU_MASK BIT(0) 89 90 /* DRA752.BANDGAP_CTRL_2 */ 91 #define DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK BIT(22) 92 #define DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK BIT(21) 93 #define DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK BIT(3) 94 #define DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK BIT(2) 95 #define DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK BIT(1) 96 #define DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK BIT(0) 97 98 /* DRA752.BANDGAP_STATUS_2 */ 99 #define DRA752_BANDGAP_STATUS_2_HOT_IVA_MASK BIT(3) 100 #define DRA752_BANDGAP_STATUS_2_COLD_IVA_MASK BIT(2) 101 #define DRA752_BANDGAP_STATUS_2_HOT_DSPEVE_MASK BIT(1) 102 #define DRA752_BANDGAP_STATUS_2_COLD_DSPEVE_MASK BIT(0) 103 104 /* DRA752.BANDGAP_CTRL_1 */ 105 #define DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK (0x7 << 27) 106 #define DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK BIT(23) 107 #define DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK BIT(22) 108 #define DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK BIT(21) 109 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK BIT(5) 110 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK BIT(4) 111 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK BIT(3) 112 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK BIT(2) 113 #define DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK BIT(1) 114 #define DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK BIT(0) 115 116 /* DRA752.TEMP_SENSOR */ 117 #define DRA752_TEMP_SENSOR_TMPSOFF_MASK BIT(11) 118 #define DRA752_TEMP_SENSOR_EOCZ_MASK BIT(10) 119 #define DRA752_TEMP_SENSOR_DTEMP_MASK (0x3ff << 0) 120 121 /* DRA752.BANDGAP_THRESHOLD */ 122 #define DRA752_BANDGAP_THRESHOLD_HOT_MASK (0x3ff << 16) 123 #define DRA752_BANDGAP_THRESHOLD_COLD_MASK (0x3ff << 0) 124 125 /** 126 * Temperature limits and thresholds for DRA752 127 * 128 * All the macros bellow are definitions for handling the 129 * ADC conversions and representation of temperature limits 130 * and thresholds for DRA752. Definitions are grouped 131 * by temperature domain. 132 */ 133 134 /* DRA752.common temperature definitions */ 135 /* ADC conversion table limits */ 136 #define DRA752_ADC_START_VALUE 540 137 #define DRA752_ADC_END_VALUE 945 138 139 /* DRA752.GPU temperature definitions */ 140 /* bandgap clock limits */ 141 #define DRA752_GPU_MAX_FREQ 1500000 142 #define DRA752_GPU_MIN_FREQ 1000000 143 /* interrupts thresholds */ 144 #define DRA752_GPU_T_HOT 800 145 #define DRA752_GPU_T_COLD 795 146 147 /* DRA752.MPU temperature definitions */ 148 /* bandgap clock limits */ 149 #define DRA752_MPU_MAX_FREQ 1500000 150 #define DRA752_MPU_MIN_FREQ 1000000 151 /* interrupts thresholds */ 152 #define DRA752_MPU_T_HOT 800 153 #define DRA752_MPU_T_COLD 795 154 155 /* DRA752.CORE temperature definitions */ 156 /* bandgap clock limits */ 157 #define DRA752_CORE_MAX_FREQ 1500000 158 #define DRA752_CORE_MIN_FREQ 1000000 159 /* interrupts thresholds */ 160 #define DRA752_CORE_T_HOT 800 161 #define DRA752_CORE_T_COLD 795 162 163 /* DRA752.DSPEVE temperature definitions */ 164 /* bandgap clock limits */ 165 #define DRA752_DSPEVE_MAX_FREQ 1500000 166 #define DRA752_DSPEVE_MIN_FREQ 1000000 167 /* interrupts thresholds */ 168 #define DRA752_DSPEVE_T_HOT 800 169 #define DRA752_DSPEVE_T_COLD 795 170 171 /* DRA752.IVA temperature definitions */ 172 /* bandgap clock limits */ 173 #define DRA752_IVA_MAX_FREQ 1500000 174 #define DRA752_IVA_MIN_FREQ 1000000 175 /* interrupts thresholds */ 176 #define DRA752_IVA_T_HOT 800 177 #define DRA752_IVA_T_COLD 795 178 179 #endif /* __DRA752_BANDGAP_H */ 180