1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Tegra30 SoC Thermal Sensor driver 4 * 5 * Based on downstream HWMON driver from NVIDIA. 6 * Copyright (C) 2011 NVIDIA Corporation 7 * 8 * Author: Dmitry Osipenko <digetx@gmail.com> 9 * Copyright (C) 2021 GRATE-DRIVER project 10 */ 11 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/delay.h> 15 #include <linux/errno.h> 16 #include <linux/interrupt.h> 17 #include <linux/io.h> 18 #include <linux/iopoll.h> 19 #include <linux/math.h> 20 #include <linux/module.h> 21 #include <linux/of_device.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm.h> 24 #include <linux/reset.h> 25 #include <linux/slab.h> 26 #include <linux/thermal.h> 27 #include <linux/types.h> 28 29 #include <soc/tegra/fuse.h> 30 31 #include "../thermal_core.h" 32 #include "../thermal_hwmon.h" 33 34 #define TSENSOR_SENSOR0_CONFIG0 0x0 35 #define TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP BIT(0) 36 #define TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN BIT(1) 37 #define TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN BIT(2) 38 #define TSENSOR_SENSOR0_CONFIG0_DVFS_EN BIT(3) 39 #define TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN BIT(4) 40 #define TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN BIT(5) 41 #define TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN BIT(6) 42 #define TSENSOR_SENSOR0_CONFIG0_M GENMASK(23, 8) 43 #define TSENSOR_SENSOR0_CONFIG0_N GENMASK(31, 24) 44 45 #define TSENSOR_SENSOR0_CONFIG1 0x8 46 #define TSENSOR_SENSOR0_CONFIG1_TH1 GENMASK(15, 0) 47 #define TSENSOR_SENSOR0_CONFIG1_TH2 GENMASK(31, 16) 48 49 #define TSENSOR_SENSOR0_CONFIG2 0xc 50 #define TSENSOR_SENSOR0_CONFIG2_TH3 GENMASK(15, 0) 51 52 #define TSENSOR_SENSOR0_STATUS0 0x18 53 #define TSENSOR_SENSOR0_STATUS0_STATE GENMASK(2, 0) 54 #define TSENSOR_SENSOR0_STATUS0_INTR BIT(8) 55 #define TSENSOR_SENSOR0_STATUS0_CURRENT_VALID BIT(9) 56 57 #define TSENSOR_SENSOR0_TS_STATUS1 0x1c 58 #define TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT GENMASK(31, 16) 59 60 #define TEGRA30_FUSE_TEST_PROG_VER 0x28 61 62 #define TEGRA30_FUSE_TSENSOR_CALIB 0x98 63 #define TEGRA30_FUSE_TSENSOR_CALIB_LOW GENMASK(15, 0) 64 #define TEGRA30_FUSE_TSENSOR_CALIB_HIGH GENMASK(31, 16) 65 66 #define TEGRA30_FUSE_SPARE_BIT 0x144 67 68 struct tegra_tsensor; 69 70 struct tegra_tsensor_calibration_data { 71 int a, b, m, n, p, r; 72 }; 73 74 struct tegra_tsensor_channel { 75 void __iomem *regs; 76 unsigned int id; 77 struct tegra_tsensor *ts; 78 struct thermal_zone_device *tzd; 79 }; 80 81 struct tegra_tsensor { 82 void __iomem *regs; 83 bool swap_channels; 84 struct clk *clk; 85 struct device *dev; 86 struct reset_control *rst; 87 struct tegra_tsensor_channel ch[2]; 88 struct tegra_tsensor_calibration_data calib; 89 }; 90 91 static int tegra_tsensor_hw_enable(const struct tegra_tsensor *ts) 92 { 93 u32 val; 94 int err; 95 96 err = reset_control_assert(ts->rst); 97 if (err) { 98 dev_err(ts->dev, "failed to assert hardware reset: %d\n", err); 99 return err; 100 } 101 102 err = clk_prepare_enable(ts->clk); 103 if (err) { 104 dev_err(ts->dev, "failed to enable clock: %d\n", err); 105 return err; 106 } 107 108 fsleep(1000); 109 110 err = reset_control_deassert(ts->rst); 111 if (err) { 112 dev_err(ts->dev, "failed to deassert hardware reset: %d\n", err); 113 goto disable_clk; 114 } 115 116 /* 117 * Sensors are enabled after reset by default, but not gauging 118 * until clock counter is programmed. 119 * 120 * M: number of reference clock pulses after which every 121 * temperature / voltage measurement is made 122 * 123 * N: number of reference clock counts for which the counter runs 124 */ 125 val = FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_M, 12500); 126 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_N, 255); 127 128 /* apply the same configuration to both channels */ 129 writel_relaxed(val, ts->regs + 0x40 + TSENSOR_SENSOR0_CONFIG0); 130 writel_relaxed(val, ts->regs + 0x80 + TSENSOR_SENSOR0_CONFIG0); 131 132 return 0; 133 134 disable_clk: 135 clk_disable_unprepare(ts->clk); 136 137 return err; 138 } 139 140 static int tegra_tsensor_hw_disable(const struct tegra_tsensor *ts) 141 { 142 int err; 143 144 err = reset_control_assert(ts->rst); 145 if (err) { 146 dev_err(ts->dev, "failed to assert hardware reset: %d\n", err); 147 return err; 148 } 149 150 clk_disable_unprepare(ts->clk); 151 152 return 0; 153 } 154 155 static void devm_tegra_tsensor_hw_disable(void *data) 156 { 157 const struct tegra_tsensor *ts = data; 158 159 tegra_tsensor_hw_disable(ts); 160 } 161 162 static int tegra_tsensor_get_temp(struct thermal_zone_device *tz, int *temp) 163 { 164 const struct tegra_tsensor_channel *tsc = tz->devdata; 165 const struct tegra_tsensor *ts = tsc->ts; 166 int err, c1, c2, c3, c4, counter; 167 u32 val; 168 169 /* 170 * Counter will be invalid if hardware is misprogrammed or not enough 171 * time passed since the time when sensor was enabled. 172 */ 173 err = readl_relaxed_poll_timeout(tsc->regs + TSENSOR_SENSOR0_STATUS0, val, 174 val & TSENSOR_SENSOR0_STATUS0_CURRENT_VALID, 175 21 * USEC_PER_MSEC, 176 21 * USEC_PER_MSEC * 50); 177 if (err) { 178 dev_err_once(ts->dev, "ch%u: counter invalid\n", tsc->id); 179 return err; 180 } 181 182 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_TS_STATUS1); 183 counter = FIELD_GET(TSENSOR_SENSOR0_TS_STATUS1_CURRENT_COUNT, val); 184 185 /* 186 * This shouldn't happen with a valid counter status, nevertheless 187 * lets verify the value since it's in a separate (from status) 188 * register. 189 */ 190 if (counter == 0xffff) { 191 dev_err_once(ts->dev, "ch%u: counter overflow\n", tsc->id); 192 return -EINVAL; 193 } 194 195 /* 196 * temperature = a * counter + b 197 * temperature = m * (temperature ^ 2) + n * temperature + p 198 */ 199 c1 = DIV_ROUND_CLOSEST(ts->calib.a * counter + ts->calib.b, 1000000); 200 c1 = c1 ?: 1; 201 c2 = DIV_ROUND_CLOSEST(ts->calib.p, c1); 202 c3 = c1 * ts->calib.m; 203 c4 = ts->calib.n; 204 205 *temp = DIV_ROUND_CLOSEST(c1 * (c2 + c3 + c4), 1000); 206 207 return 0; 208 } 209 210 static int tegra_tsensor_temp_to_counter(const struct tegra_tsensor *ts, int temp) 211 { 212 int c1, c2; 213 214 c1 = DIV_ROUND_CLOSEST(ts->calib.p - temp * 1000, ts->calib.m); 215 c2 = -ts->calib.r - int_sqrt(ts->calib.r * ts->calib.r - c1); 216 217 return DIV_ROUND_CLOSEST(c2 * 1000000 - ts->calib.b, ts->calib.a); 218 } 219 220 static int tegra_tsensor_set_trips(struct thermal_zone_device *tz, int low, int high) 221 { 222 const struct tegra_tsensor_channel *tsc = tz->devdata; 223 const struct tegra_tsensor *ts = tsc->ts; 224 u32 val; 225 226 /* 227 * TSENSOR doesn't trigger interrupt on the "low" temperature breach, 228 * hence bail out if high temperature is unspecified. 229 */ 230 if (high == INT_MAX) 231 return 0; 232 233 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1); 234 val &= ~TSENSOR_SENSOR0_CONFIG1_TH1; 235 236 high = tegra_tsensor_temp_to_counter(ts, high); 237 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH1, high); 238 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1); 239 240 return 0; 241 } 242 243 static const struct thermal_zone_device_ops ops = { 244 .get_temp = tegra_tsensor_get_temp, 245 .set_trips = tegra_tsensor_set_trips, 246 }; 247 248 static bool 249 tegra_tsensor_handle_channel_interrupt(const struct tegra_tsensor *ts, 250 unsigned int id) 251 { 252 const struct tegra_tsensor_channel *tsc = &ts->ch[id]; 253 u32 val; 254 255 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_STATUS0); 256 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_STATUS0); 257 258 if (FIELD_GET(TSENSOR_SENSOR0_STATUS0_STATE, val) == 5) 259 dev_err_ratelimited(ts->dev, "ch%u: counter overflowed\n", id); 260 261 if (!FIELD_GET(TSENSOR_SENSOR0_STATUS0_INTR, val)) 262 return false; 263 264 thermal_zone_device_update(tsc->tzd, THERMAL_EVENT_UNSPECIFIED); 265 266 return true; 267 } 268 269 static irqreturn_t tegra_tsensor_isr(int irq, void *data) 270 { 271 const struct tegra_tsensor *ts = data; 272 bool handled = false; 273 unsigned int i; 274 275 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) 276 handled |= tegra_tsensor_handle_channel_interrupt(ts, i); 277 278 return handled ? IRQ_HANDLED : IRQ_NONE; 279 } 280 281 static int tegra_tsensor_disable_hw_channel(const struct tegra_tsensor *ts, 282 unsigned int id) 283 { 284 const struct tegra_tsensor_channel *tsc = &ts->ch[id]; 285 struct thermal_zone_device *tzd = tsc->tzd; 286 u32 val; 287 int err; 288 289 if (!tzd) 290 goto stop_channel; 291 292 err = thermal_zone_device_disable(tzd); 293 if (err) { 294 dev_err(ts->dev, "ch%u: failed to disable zone: %d\n", id, err); 295 return err; 296 } 297 298 stop_channel: 299 /* stop channel gracefully */ 300 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0); 301 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP, 1); 302 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0); 303 304 return 0; 305 } 306 307 static void tegra_tsensor_get_hw_channel_trips(struct thermal_zone_device *tzd, 308 int *hot_trip, int *crit_trip) 309 { 310 unsigned int i; 311 312 /* 313 * 90C is the maximal critical temperature of all Tegra30 SoC variants, 314 * use it for the default trip if unspecified in a device-tree. 315 */ 316 *hot_trip = 85000; 317 *crit_trip = 90000; 318 319 for (i = 0; i < thermal_zone_get_num_trips(tzd); i++) { 320 321 struct thermal_trip trip; 322 323 thermal_zone_get_trip(tzd, i, &trip); 324 325 if (trip.type == THERMAL_TRIP_HOT) 326 *hot_trip = trip.temperature; 327 328 if (trip.type == THERMAL_TRIP_CRITICAL) 329 *crit_trip = trip.temperature; 330 } 331 332 /* clamp hardware trips to the calibration limits */ 333 *hot_trip = clamp(*hot_trip, 25000, 90000); 334 335 /* 336 * Kernel will perform a normal system shut down if it will 337 * see that critical temperature is breached, hence set the 338 * hardware limit by 5C higher in order to allow system to 339 * shut down gracefully before sending signal to the Power 340 * Management controller. 341 */ 342 *crit_trip = clamp(*crit_trip + 5000, 25000, 90000); 343 } 344 345 static int tegra_tsensor_enable_hw_channel(const struct tegra_tsensor *ts, 346 unsigned int id) 347 { 348 const struct tegra_tsensor_channel *tsc = &ts->ch[id]; 349 struct thermal_zone_device *tzd = tsc->tzd; 350 int err, hot_trip = 0, crit_trip = 0; 351 u32 val; 352 353 if (!tzd) { 354 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0); 355 val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP; 356 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0); 357 358 return 0; 359 } 360 361 tegra_tsensor_get_hw_channel_trips(tzd, &hot_trip, &crit_trip); 362 363 /* prevent potential racing with tegra_tsensor_set_trips() */ 364 mutex_lock(&tzd->lock); 365 366 dev_info_once(ts->dev, "ch%u: PMC emergency shutdown trip set to %dC\n", 367 id, DIV_ROUND_CLOSEST(crit_trip, 1000)); 368 369 hot_trip = tegra_tsensor_temp_to_counter(ts, hot_trip); 370 crit_trip = tegra_tsensor_temp_to_counter(ts, crit_trip); 371 372 /* program LEVEL2 counter threshold */ 373 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG1); 374 val &= ~TSENSOR_SENSOR0_CONFIG1_TH2; 375 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG1_TH2, hot_trip); 376 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG1); 377 378 /* program LEVEL3 counter threshold */ 379 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG2); 380 val &= ~TSENSOR_SENSOR0_CONFIG2_TH3; 381 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG2_TH3, crit_trip); 382 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG2); 383 384 /* 385 * Enable sensor, emergency shutdown, interrupts for level 1/2/3 386 * breaches and counter overflow condition. 387 * 388 * Disable DIV2 throttle for now since we need to figure out how 389 * to integrate it properly with the thermal framework. 390 * 391 * Thermal levels supported by hardware: 392 * 393 * Level 0 = cold 394 * Level 1 = passive cooling (cpufreq DVFS) 395 * Level 2 = passive cooling assisted by hardware (DIV2) 396 * Level 3 = emergency shutdown assisted by hardware (PMC) 397 */ 398 val = readl_relaxed(tsc->regs + TSENSOR_SENSOR0_CONFIG0); 399 val &= ~TSENSOR_SENSOR0_CONFIG0_SENSOR_STOP; 400 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_DVFS_EN, 1); 401 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_HW_FREQ_DIV_EN, 0); 402 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_THERMAL_RST_EN, 1); 403 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_OVERFLOW_EN, 1); 404 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_HW_FREQ_DIV_EN, 1); 405 val |= FIELD_PREP(TSENSOR_SENSOR0_CONFIG0_INTR_THERMAL_RST_EN, 1); 406 writel_relaxed(val, tsc->regs + TSENSOR_SENSOR0_CONFIG0); 407 408 mutex_unlock(&tzd->lock); 409 410 err = thermal_zone_device_enable(tzd); 411 if (err) { 412 dev_err(ts->dev, "ch%u: failed to enable zone: %d\n", id, err); 413 return err; 414 } 415 416 return 0; 417 } 418 419 static bool tegra_tsensor_fuse_read_spare(unsigned int spare) 420 { 421 u32 val = 0; 422 423 tegra_fuse_readl(TEGRA30_FUSE_SPARE_BIT + spare * 4, &val); 424 425 return !!val; 426 } 427 428 static int tegra_tsensor_nvmem_setup(struct tegra_tsensor *ts) 429 { 430 u32 i, ate_ver = 0, cal = 0, t1_25C = 0, t2_90C = 0; 431 int err, c1_25C, c2_90C; 432 433 err = tegra_fuse_readl(TEGRA30_FUSE_TEST_PROG_VER, &ate_ver); 434 if (err) { 435 dev_err_probe(ts->dev, err, "failed to get ATE version\n"); 436 return err; 437 } 438 439 if (ate_ver < 8) { 440 dev_info(ts->dev, "unsupported ATE version: %u\n", ate_ver); 441 return -ENODEV; 442 } 443 444 /* 445 * We have two TSENSOR channels in a two different spots on SoC. 446 * Second channel provides more accurate data on older SoC versions, 447 * use it as a primary channel. 448 */ 449 if (ate_ver <= 21) { 450 dev_info_once(ts->dev, 451 "older ATE version detected, channels remapped\n"); 452 ts->swap_channels = true; 453 } 454 455 err = tegra_fuse_readl(TEGRA30_FUSE_TSENSOR_CALIB, &cal); 456 if (err) { 457 dev_err(ts->dev, "failed to get calibration data: %d\n", err); 458 return err; 459 } 460 461 /* get calibrated counter values for 25C/90C thresholds */ 462 c1_25C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_LOW, cal); 463 c2_90C = FIELD_GET(TEGRA30_FUSE_TSENSOR_CALIB_HIGH, cal); 464 465 /* and calibrated temperatures corresponding to the counter values */ 466 for (i = 0; i < 7; i++) { 467 t1_25C |= tegra_tsensor_fuse_read_spare(14 + i) << i; 468 t1_25C |= tegra_tsensor_fuse_read_spare(21 + i) << i; 469 470 t2_90C |= tegra_tsensor_fuse_read_spare(0 + i) << i; 471 t2_90C |= tegra_tsensor_fuse_read_spare(7 + i) << i; 472 } 473 474 if (c2_90C - c1_25C <= t2_90C - t1_25C) { 475 dev_err(ts->dev, "invalid calibration data: %d %d %u %u\n", 476 c2_90C, c1_25C, t2_90C, t1_25C); 477 return -EINVAL; 478 } 479 480 /* all calibration coefficients are premultiplied by 1000000 */ 481 482 ts->calib.a = DIV_ROUND_CLOSEST((t2_90C - t1_25C) * 1000000, 483 (c2_90C - c1_25C)); 484 485 ts->calib.b = t1_25C * 1000000 - ts->calib.a * c1_25C; 486 487 if (tegra_sku_info.revision == TEGRA_REVISION_A01) { 488 ts->calib.m = -2775; 489 ts->calib.n = 1338811; 490 ts->calib.p = -7300000; 491 } else { 492 ts->calib.m = -3512; 493 ts->calib.n = 1528943; 494 ts->calib.p = -11100000; 495 } 496 497 /* except the coefficient of a reduced quadratic equation */ 498 ts->calib.r = DIV_ROUND_CLOSEST(ts->calib.n, ts->calib.m * 2); 499 500 dev_info_once(ts->dev, 501 "calibration: %d %d %u %u ATE ver: %u SoC rev: %u\n", 502 c2_90C, c1_25C, t2_90C, t1_25C, ate_ver, 503 tegra_sku_info.revision); 504 505 return 0; 506 } 507 508 static int tegra_tsensor_register_channel(struct tegra_tsensor *ts, 509 unsigned int id) 510 { 511 struct tegra_tsensor_channel *tsc = &ts->ch[id]; 512 unsigned int hw_id = ts->swap_channels ? !id : id; 513 514 tsc->ts = ts; 515 tsc->id = id; 516 tsc->regs = ts->regs + 0x40 * (hw_id + 1); 517 518 tsc->tzd = devm_thermal_of_zone_register(ts->dev, id, tsc, &ops); 519 if (IS_ERR(tsc->tzd)) { 520 if (PTR_ERR(tsc->tzd) != -ENODEV) 521 return dev_err_probe(ts->dev, PTR_ERR(tsc->tzd), 522 "failed to register thermal zone\n"); 523 524 /* 525 * It's okay if sensor isn't assigned to any thermal zone 526 * in a device-tree. 527 */ 528 tsc->tzd = NULL; 529 return 0; 530 } 531 532 if (devm_thermal_add_hwmon_sysfs(tsc->tzd)) 533 dev_warn(ts->dev, "failed to add hwmon sysfs attributes\n"); 534 535 return 0; 536 } 537 538 static int tegra_tsensor_probe(struct platform_device *pdev) 539 { 540 struct tegra_tsensor *ts; 541 unsigned int i; 542 int err, irq; 543 544 ts = devm_kzalloc(&pdev->dev, sizeof(*ts), GFP_KERNEL); 545 if (!ts) 546 return -ENOMEM; 547 548 irq = platform_get_irq(pdev, 0); 549 if (irq < 0) 550 return irq; 551 552 ts->dev = &pdev->dev; 553 platform_set_drvdata(pdev, ts); 554 555 ts->regs = devm_platform_ioremap_resource(pdev, 0); 556 if (IS_ERR(ts->regs)) 557 return PTR_ERR(ts->regs); 558 559 ts->clk = devm_clk_get(&pdev->dev, NULL); 560 if (IS_ERR(ts->clk)) 561 return dev_err_probe(&pdev->dev, PTR_ERR(ts->clk), 562 "failed to get clock\n"); 563 564 ts->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL); 565 if (IS_ERR(ts->rst)) 566 return dev_err_probe(&pdev->dev, PTR_ERR(ts->rst), 567 "failed to get reset control\n"); 568 569 err = tegra_tsensor_nvmem_setup(ts); 570 if (err) 571 return err; 572 573 err = tegra_tsensor_hw_enable(ts); 574 if (err) 575 return err; 576 577 err = devm_add_action_or_reset(&pdev->dev, 578 devm_tegra_tsensor_hw_disable, 579 ts); 580 if (err) 581 return err; 582 583 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { 584 err = tegra_tsensor_register_channel(ts, i); 585 if (err) 586 return err; 587 } 588 589 err = devm_request_threaded_irq(&pdev->dev, irq, NULL, 590 tegra_tsensor_isr, IRQF_ONESHOT, 591 "tegra_tsensor", ts); 592 if (err) 593 return dev_err_probe(&pdev->dev, err, 594 "failed to request interrupt\n"); 595 596 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { 597 err = tegra_tsensor_enable_hw_channel(ts, i); 598 if (err) 599 return err; 600 } 601 602 return 0; 603 } 604 605 static int __maybe_unused tegra_tsensor_suspend(struct device *dev) 606 { 607 struct tegra_tsensor *ts = dev_get_drvdata(dev); 608 unsigned int i; 609 int err; 610 611 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { 612 err = tegra_tsensor_disable_hw_channel(ts, i); 613 if (err) 614 goto enable_channel; 615 } 616 617 err = tegra_tsensor_hw_disable(ts); 618 if (err) 619 goto enable_channel; 620 621 return 0; 622 623 enable_channel: 624 while (i--) 625 tegra_tsensor_enable_hw_channel(ts, i); 626 627 return err; 628 } 629 630 static int __maybe_unused tegra_tsensor_resume(struct device *dev) 631 { 632 struct tegra_tsensor *ts = dev_get_drvdata(dev); 633 unsigned int i; 634 int err; 635 636 err = tegra_tsensor_hw_enable(ts); 637 if (err) 638 return err; 639 640 for (i = 0; i < ARRAY_SIZE(ts->ch); i++) { 641 err = tegra_tsensor_enable_hw_channel(ts, i); 642 if (err) 643 return err; 644 } 645 646 return 0; 647 } 648 649 static const struct dev_pm_ops tegra_tsensor_pm_ops = { 650 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_tsensor_suspend, 651 tegra_tsensor_resume) 652 }; 653 654 static const struct of_device_id tegra_tsensor_of_match[] = { 655 { .compatible = "nvidia,tegra30-tsensor", }, 656 {}, 657 }; 658 MODULE_DEVICE_TABLE(of, tegra_tsensor_of_match); 659 660 static struct platform_driver tegra_tsensor_driver = { 661 .probe = tegra_tsensor_probe, 662 .driver = { 663 .name = "tegra30-tsensor", 664 .of_match_table = tegra_tsensor_of_match, 665 .pm = &tegra_tsensor_pm_ops, 666 }, 667 }; 668 module_platform_driver(tegra_tsensor_driver); 669 670 MODULE_DESCRIPTION("NVIDIA Tegra30 Thermal Sensor driver"); 671 MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>"); 672 MODULE_LICENSE("GPL"); 673