1 /* 2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #include <linux/module.h> 16 #include <linux/platform_device.h> 17 #include <soc/tegra/fuse.h> 18 19 #include <dt-bindings/thermal/tegra124-soctherm.h> 20 21 #include "soctherm.h" 22 23 #define TEGRA210_THERMTRIP_ANY_EN_MASK (0x1 << 31) 24 #define TEGRA210_THERMTRIP_MEM_EN_MASK (0x1 << 30) 25 #define TEGRA210_THERMTRIP_GPU_EN_MASK (0x1 << 29) 26 #define TEGRA210_THERMTRIP_CPU_EN_MASK (0x1 << 28) 27 #define TEGRA210_THERMTRIP_TSENSE_EN_MASK (0x1 << 27) 28 #define TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK (0x1ff << 18) 29 #define TEGRA210_THERMTRIP_CPU_THRESH_MASK (0x1ff << 9) 30 #define TEGRA210_THERMTRIP_TSENSE_THRESH_MASK 0x1ff 31 32 #define TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK (0x1ff << 18) 33 #define TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK (0x1ff << 9) 34 35 #define TEGRA210_THRESH_GRAIN 500 36 #define TEGRA210_BPTT 9 37 38 static const struct tegra_tsensor_configuration tegra210_tsensor_config = { 39 .tall = 16300, 40 .tiddq_en = 1, 41 .ten_count = 1, 42 .tsample = 120, 43 .tsample_ate = 480, 44 }; 45 46 static const struct tegra_tsensor_group tegra210_tsensor_group_cpu = { 47 .id = TEGRA124_SOCTHERM_SENSOR_CPU, 48 .name = "cpu", 49 .sensor_temp_offset = SENSOR_TEMP1, 50 .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK, 51 .pdiv = 8, 52 .pdiv_ate = 8, 53 .pdiv_mask = SENSOR_PDIV_CPU_MASK, 54 .pllx_hotspot_diff = 10, 55 .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK, 56 .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK, 57 .thermtrip_enable_mask = TEGRA210_THERMTRIP_CPU_EN_MASK, 58 .thermtrip_threshold_mask = TEGRA210_THERMTRIP_CPU_THRESH_MASK, 59 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU, 60 .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK, 61 .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK, 62 }; 63 64 static const struct tegra_tsensor_group tegra210_tsensor_group_gpu = { 65 .id = TEGRA124_SOCTHERM_SENSOR_GPU, 66 .name = "gpu", 67 .sensor_temp_offset = SENSOR_TEMP1, 68 .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK, 69 .pdiv = 8, 70 .pdiv_ate = 8, 71 .pdiv_mask = SENSOR_PDIV_GPU_MASK, 72 .pllx_hotspot_diff = 5, 73 .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK, 74 .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK, 75 .thermtrip_enable_mask = TEGRA210_THERMTRIP_GPU_EN_MASK, 76 .thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK, 77 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU, 78 .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK, 79 .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK, 80 }; 81 82 static const struct tegra_tsensor_group tegra210_tsensor_group_pll = { 83 .id = TEGRA124_SOCTHERM_SENSOR_PLLX, 84 .name = "pll", 85 .sensor_temp_offset = SENSOR_TEMP2, 86 .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK, 87 .pdiv = 8, 88 .pdiv_ate = 8, 89 .pdiv_mask = SENSOR_PDIV_PLLX_MASK, 90 .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK, 91 .thermtrip_enable_mask = TEGRA210_THERMTRIP_TSENSE_EN_MASK, 92 .thermtrip_threshold_mask = TEGRA210_THERMTRIP_TSENSE_THRESH_MASK, 93 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE, 94 .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK, 95 .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK, 96 }; 97 98 static const struct tegra_tsensor_group tegra210_tsensor_group_mem = { 99 .id = TEGRA124_SOCTHERM_SENSOR_MEM, 100 .name = "mem", 101 .sensor_temp_offset = SENSOR_TEMP2, 102 .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK, 103 .pdiv = 8, 104 .pdiv_ate = 8, 105 .pdiv_mask = SENSOR_PDIV_MEM_MASK, 106 .pllx_hotspot_diff = 0, 107 .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK, 108 .thermtrip_any_en_mask = TEGRA210_THERMTRIP_ANY_EN_MASK, 109 .thermtrip_enable_mask = TEGRA210_THERMTRIP_MEM_EN_MASK, 110 .thermtrip_threshold_mask = TEGRA210_THERMTRIP_GPUMEM_THRESH_MASK, 111 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM, 112 .thermctl_lvl0_up_thresh_mask = TEGRA210_THERMCTL_LVL0_UP_THRESH_MASK, 113 .thermctl_lvl0_dn_thresh_mask = TEGRA210_THERMCTL_LVL0_DN_THRESH_MASK, 114 }; 115 116 static const struct tegra_tsensor_group *tegra210_tsensor_groups[] = { 117 &tegra210_tsensor_group_cpu, 118 &tegra210_tsensor_group_gpu, 119 &tegra210_tsensor_group_pll, 120 &tegra210_tsensor_group_mem, 121 }; 122 123 static const struct tegra_tsensor tegra210_tsensors[] = { 124 { 125 .name = "cpu0", 126 .base = 0xc0, 127 .config = &tegra210_tsensor_config, 128 .calib_fuse_offset = 0x098, 129 .fuse_corr_alpha = 1085000, 130 .fuse_corr_beta = 3244200, 131 .group = &tegra210_tsensor_group_cpu, 132 }, { 133 .name = "cpu1", 134 .base = 0xe0, 135 .config = &tegra210_tsensor_config, 136 .calib_fuse_offset = 0x084, 137 .fuse_corr_alpha = 1126200, 138 .fuse_corr_beta = -67500, 139 .group = &tegra210_tsensor_group_cpu, 140 }, { 141 .name = "cpu2", 142 .base = 0x100, 143 .config = &tegra210_tsensor_config, 144 .calib_fuse_offset = 0x088, 145 .fuse_corr_alpha = 1098400, 146 .fuse_corr_beta = 2251100, 147 .group = &tegra210_tsensor_group_cpu, 148 }, { 149 .name = "cpu3", 150 .base = 0x120, 151 .config = &tegra210_tsensor_config, 152 .calib_fuse_offset = 0x12c, 153 .fuse_corr_alpha = 1108000, 154 .fuse_corr_beta = 602700, 155 .group = &tegra210_tsensor_group_cpu, 156 }, { 157 .name = "mem0", 158 .base = 0x140, 159 .config = &tegra210_tsensor_config, 160 .calib_fuse_offset = 0x158, 161 .fuse_corr_alpha = 1069200, 162 .fuse_corr_beta = 3549900, 163 .group = &tegra210_tsensor_group_mem, 164 }, { 165 .name = "mem1", 166 .base = 0x160, 167 .config = &tegra210_tsensor_config, 168 .calib_fuse_offset = 0x15c, 169 .fuse_corr_alpha = 1173700, 170 .fuse_corr_beta = -6263600, 171 .group = &tegra210_tsensor_group_mem, 172 }, { 173 .name = "gpu", 174 .base = 0x180, 175 .config = &tegra210_tsensor_config, 176 .calib_fuse_offset = 0x154, 177 .fuse_corr_alpha = 1074300, 178 .fuse_corr_beta = 2734900, 179 .group = &tegra210_tsensor_group_gpu, 180 }, { 181 .name = "pllx", 182 .base = 0x1a0, 183 .config = &tegra210_tsensor_config, 184 .calib_fuse_offset = 0x160, 185 .fuse_corr_alpha = 1039700, 186 .fuse_corr_beta = 6829100, 187 .group = &tegra210_tsensor_group_pll, 188 }, 189 }; 190 191 /* 192 * Mask/shift bits in FUSE_TSENSOR_COMMON and 193 * FUSE_TSENSOR_COMMON, which are described in 194 * tegra_soctherm_fuse.c 195 */ 196 static const struct tegra_soctherm_fuse tegra210_soctherm_fuse = { 197 .fuse_base_cp_mask = 0x3ff << 11, 198 .fuse_base_cp_shift = 11, 199 .fuse_base_ft_mask = 0x7ff << 21, 200 .fuse_base_ft_shift = 21, 201 .fuse_shift_ft_mask = 0x1f << 6, 202 .fuse_shift_ft_shift = 6, 203 .fuse_spare_realignment = 0, 204 }; 205 206 const struct tegra_soctherm_soc tegra210_soctherm = { 207 .tsensors = tegra210_tsensors, 208 .num_tsensors = ARRAY_SIZE(tegra210_tsensors), 209 .ttgs = tegra210_tsensor_groups, 210 .num_ttgs = ARRAY_SIZE(tegra210_tsensor_groups), 211 .tfuse = &tegra210_soctherm_fuse, 212 .thresh_grain = TEGRA210_THRESH_GRAIN, 213 .bptt = TEGRA210_BPTT, 214 .use_ccroc = false, 215 }; 216