165b6d57cSWei Ni /* 265b6d57cSWei Ni * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. 365b6d57cSWei Ni * 465b6d57cSWei Ni * This software is licensed under the terms of the GNU General Public 565b6d57cSWei Ni * License version 2, as published by the Free Software Foundation, and 665b6d57cSWei Ni * may be copied, distributed, and modified under those terms. 765b6d57cSWei Ni * 865b6d57cSWei Ni * This program is distributed in the hope that it will be useful, 965b6d57cSWei Ni * but WITHOUT ANY WARRANTY; without even the implied warranty of 1065b6d57cSWei Ni * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1165b6d57cSWei Ni * GNU General Public License for more details. 1265b6d57cSWei Ni * 1365b6d57cSWei Ni */ 1465b6d57cSWei Ni 1565b6d57cSWei Ni #include <linux/module.h> 1665b6d57cSWei Ni #include <linux/platform_device.h> 1765b6d57cSWei Ni 1865b6d57cSWei Ni #include <dt-bindings/thermal/tegra124-soctherm.h> 1965b6d57cSWei Ni 2065b6d57cSWei Ni #include "soctherm.h" 2165b6d57cSWei Ni 222a895871SWei Ni #define TEGRA124_THERMTRIP_ANY_EN_MASK (0x1 << 28) 232a895871SWei Ni #define TEGRA124_THERMTRIP_MEM_EN_MASK (0x1 << 27) 242a895871SWei Ni #define TEGRA124_THERMTRIP_GPU_EN_MASK (0x1 << 26) 252a895871SWei Ni #define TEGRA124_THERMTRIP_CPU_EN_MASK (0x1 << 25) 262a895871SWei Ni #define TEGRA124_THERMTRIP_TSENSE_EN_MASK (0x1 << 24) 272a895871SWei Ni #define TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16) 282a895871SWei Ni #define TEGRA124_THERMTRIP_CPU_THRESH_MASK (0xff << 8) 292a895871SWei Ni #define TEGRA124_THERMTRIP_TSENSE_THRESH_MASK 0xff 302a895871SWei Ni 312a895871SWei Ni #define TEGRA124_THRESH_GRAIN 1000 322a895871SWei Ni 3365b6d57cSWei Ni static const struct tegra_tsensor_configuration tegra124_tsensor_config = { 3465b6d57cSWei Ni .tall = 16300, 3565b6d57cSWei Ni .tiddq_en = 1, 3665b6d57cSWei Ni .ten_count = 1, 3765b6d57cSWei Ni .tsample = 120, 3865b6d57cSWei Ni .tsample_ate = 480, 3965b6d57cSWei Ni }; 4065b6d57cSWei Ni 4165b6d57cSWei Ni static const struct tegra_tsensor_group tegra124_tsensor_group_cpu = { 4265b6d57cSWei Ni .id = TEGRA124_SOCTHERM_SENSOR_CPU, 4365b6d57cSWei Ni .name = "cpu", 4465b6d57cSWei Ni .sensor_temp_offset = SENSOR_TEMP1, 4565b6d57cSWei Ni .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK, 4665b6d57cSWei Ni .pdiv = 8, 4765b6d57cSWei Ni .pdiv_ate = 8, 4865b6d57cSWei Ni .pdiv_mask = SENSOR_PDIV_CPU_MASK, 4965b6d57cSWei Ni .pllx_hotspot_diff = 10, 5065b6d57cSWei Ni .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK, 512a895871SWei Ni .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK, 522a895871SWei Ni .thermtrip_enable_mask = TEGRA124_THERMTRIP_CPU_EN_MASK, 532a895871SWei Ni .thermtrip_threshold_mask = TEGRA124_THERMTRIP_CPU_THRESH_MASK, 5465b6d57cSWei Ni }; 5565b6d57cSWei Ni 5665b6d57cSWei Ni static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = { 5765b6d57cSWei Ni .id = TEGRA124_SOCTHERM_SENSOR_GPU, 5865b6d57cSWei Ni .name = "gpu", 5965b6d57cSWei Ni .sensor_temp_offset = SENSOR_TEMP1, 6065b6d57cSWei Ni .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK, 6165b6d57cSWei Ni .pdiv = 8, 6265b6d57cSWei Ni .pdiv_ate = 8, 6365b6d57cSWei Ni .pdiv_mask = SENSOR_PDIV_GPU_MASK, 6465b6d57cSWei Ni .pllx_hotspot_diff = 5, 6565b6d57cSWei Ni .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK, 662a895871SWei Ni .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK, 672a895871SWei Ni .thermtrip_enable_mask = TEGRA124_THERMTRIP_GPU_EN_MASK, 682a895871SWei Ni .thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK, 6965b6d57cSWei Ni }; 7065b6d57cSWei Ni 7165b6d57cSWei Ni static const struct tegra_tsensor_group tegra124_tsensor_group_pll = { 7265b6d57cSWei Ni .id = TEGRA124_SOCTHERM_SENSOR_PLLX, 7365b6d57cSWei Ni .name = "pll", 7465b6d57cSWei Ni .sensor_temp_offset = SENSOR_TEMP2, 7565b6d57cSWei Ni .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK, 7665b6d57cSWei Ni .pdiv = 8, 7765b6d57cSWei Ni .pdiv_ate = 8, 7865b6d57cSWei Ni .pdiv_mask = SENSOR_PDIV_PLLX_MASK, 792a895871SWei Ni .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK, 802a895871SWei Ni .thermtrip_enable_mask = TEGRA124_THERMTRIP_TSENSE_EN_MASK, 812a895871SWei Ni .thermtrip_threshold_mask = TEGRA124_THERMTRIP_TSENSE_THRESH_MASK, 8265b6d57cSWei Ni }; 8365b6d57cSWei Ni 8465b6d57cSWei Ni static const struct tegra_tsensor_group tegra124_tsensor_group_mem = { 8565b6d57cSWei Ni .id = TEGRA124_SOCTHERM_SENSOR_MEM, 8665b6d57cSWei Ni .name = "mem", 8765b6d57cSWei Ni .sensor_temp_offset = SENSOR_TEMP2, 8865b6d57cSWei Ni .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK, 8965b6d57cSWei Ni .pdiv = 8, 9065b6d57cSWei Ni .pdiv_ate = 8, 9165b6d57cSWei Ni .pdiv_mask = SENSOR_PDIV_MEM_MASK, 9265b6d57cSWei Ni .pllx_hotspot_diff = 0, 9365b6d57cSWei Ni .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK, 942a895871SWei Ni .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK, 952a895871SWei Ni .thermtrip_enable_mask = TEGRA124_THERMTRIP_MEM_EN_MASK, 962a895871SWei Ni .thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK, 9765b6d57cSWei Ni }; 9865b6d57cSWei Ni 9965b6d57cSWei Ni static const struct tegra_tsensor_group *tegra124_tsensor_groups[] = { 10065b6d57cSWei Ni &tegra124_tsensor_group_cpu, 10165b6d57cSWei Ni &tegra124_tsensor_group_gpu, 10265b6d57cSWei Ni &tegra124_tsensor_group_pll, 10365b6d57cSWei Ni &tegra124_tsensor_group_mem, 10465b6d57cSWei Ni }; 10565b6d57cSWei Ni 10665b6d57cSWei Ni static const struct tegra_tsensor tegra124_tsensors[] = { 10765b6d57cSWei Ni { 10865b6d57cSWei Ni .name = "cpu0", 10965b6d57cSWei Ni .base = 0xc0, 11065b6d57cSWei Ni .config = &tegra124_tsensor_config, 11165b6d57cSWei Ni .calib_fuse_offset = 0x098, 11265b6d57cSWei Ni .fuse_corr_alpha = 1135400, 11365b6d57cSWei Ni .fuse_corr_beta = -6266900, 11465b6d57cSWei Ni .group = &tegra124_tsensor_group_cpu, 11565b6d57cSWei Ni }, { 11665b6d57cSWei Ni .name = "cpu1", 11765b6d57cSWei Ni .base = 0xe0, 11865b6d57cSWei Ni .config = &tegra124_tsensor_config, 11965b6d57cSWei Ni .calib_fuse_offset = 0x084, 12065b6d57cSWei Ni .fuse_corr_alpha = 1122220, 12165b6d57cSWei Ni .fuse_corr_beta = -5700700, 12265b6d57cSWei Ni .group = &tegra124_tsensor_group_cpu, 12365b6d57cSWei Ni }, { 12465b6d57cSWei Ni .name = "cpu2", 12565b6d57cSWei Ni .base = 0x100, 12665b6d57cSWei Ni .config = &tegra124_tsensor_config, 12765b6d57cSWei Ni .calib_fuse_offset = 0x088, 12865b6d57cSWei Ni .fuse_corr_alpha = 1127000, 12965b6d57cSWei Ni .fuse_corr_beta = -6768200, 13065b6d57cSWei Ni .group = &tegra124_tsensor_group_cpu, 13165b6d57cSWei Ni }, { 13265b6d57cSWei Ni .name = "cpu3", 13365b6d57cSWei Ni .base = 0x120, 13465b6d57cSWei Ni .config = &tegra124_tsensor_config, 13565b6d57cSWei Ni .calib_fuse_offset = 0x12c, 13665b6d57cSWei Ni .fuse_corr_alpha = 1110900, 13765b6d57cSWei Ni .fuse_corr_beta = -6232000, 13865b6d57cSWei Ni .group = &tegra124_tsensor_group_cpu, 13965b6d57cSWei Ni }, { 14065b6d57cSWei Ni .name = "mem0", 14165b6d57cSWei Ni .base = 0x140, 14265b6d57cSWei Ni .config = &tegra124_tsensor_config, 14365b6d57cSWei Ni .calib_fuse_offset = 0x158, 14465b6d57cSWei Ni .fuse_corr_alpha = 1122300, 14565b6d57cSWei Ni .fuse_corr_beta = -5936400, 14665b6d57cSWei Ni .group = &tegra124_tsensor_group_mem, 14765b6d57cSWei Ni }, { 14865b6d57cSWei Ni .name = "mem1", 14965b6d57cSWei Ni .base = 0x160, 15065b6d57cSWei Ni .config = &tegra124_tsensor_config, 15165b6d57cSWei Ni .calib_fuse_offset = 0x15c, 15265b6d57cSWei Ni .fuse_corr_alpha = 1145700, 15365b6d57cSWei Ni .fuse_corr_beta = -7124600, 15465b6d57cSWei Ni .group = &tegra124_tsensor_group_mem, 15565b6d57cSWei Ni }, { 15665b6d57cSWei Ni .name = "gpu", 15765b6d57cSWei Ni .base = 0x180, 15865b6d57cSWei Ni .config = &tegra124_tsensor_config, 15965b6d57cSWei Ni .calib_fuse_offset = 0x154, 16065b6d57cSWei Ni .fuse_corr_alpha = 1120100, 16165b6d57cSWei Ni .fuse_corr_beta = -6000500, 16265b6d57cSWei Ni .group = &tegra124_tsensor_group_gpu, 16365b6d57cSWei Ni }, { 16465b6d57cSWei Ni .name = "pllx", 16565b6d57cSWei Ni .base = 0x1a0, 16665b6d57cSWei Ni .config = &tegra124_tsensor_config, 16765b6d57cSWei Ni .calib_fuse_offset = 0x160, 16865b6d57cSWei Ni .fuse_corr_alpha = 1106500, 16965b6d57cSWei Ni .fuse_corr_beta = -6729300, 17065b6d57cSWei Ni .group = &tegra124_tsensor_group_pll, 17165b6d57cSWei Ni }, 17265b6d57cSWei Ni }; 17365b6d57cSWei Ni 17465b6d57cSWei Ni /* 17565b6d57cSWei Ni * Mask/shift bits in FUSE_TSENSOR_COMMON and 17665b6d57cSWei Ni * FUSE_TSENSOR_COMMON, which are described in 17765b6d57cSWei Ni * tegra_soctherm_fuse.c 17865b6d57cSWei Ni */ 17965b6d57cSWei Ni static const struct tegra_soctherm_fuse tegra124_soctherm_fuse = { 18065b6d57cSWei Ni .fuse_base_cp_mask = 0x3ff, 18165b6d57cSWei Ni .fuse_base_cp_shift = 0, 18265b6d57cSWei Ni .fuse_base_ft_mask = 0x7ff << 10, 18365b6d57cSWei Ni .fuse_base_ft_shift = 10, 18465b6d57cSWei Ni .fuse_shift_ft_mask = 0x1f << 21, 18565b6d57cSWei Ni .fuse_shift_ft_shift = 21, 18665b6d57cSWei Ni .fuse_spare_realignment = 0x1fc, 18765b6d57cSWei Ni }; 18865b6d57cSWei Ni 18965b6d57cSWei Ni const struct tegra_soctherm_soc tegra124_soctherm = { 19065b6d57cSWei Ni .tsensors = tegra124_tsensors, 19165b6d57cSWei Ni .num_tsensors = ARRAY_SIZE(tegra124_tsensors), 19265b6d57cSWei Ni .ttgs = tegra124_tsensor_groups, 19365b6d57cSWei Ni .num_ttgs = ARRAY_SIZE(tegra124_tsensor_groups), 19465b6d57cSWei Ni .tfuse = &tegra124_soctherm_fuse, 1952a895871SWei Ni .thresh_grain = TEGRA124_THRESH_GRAIN, 19665b6d57cSWei Ni }; 197