1 /* 2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This software is licensed under the terms of the GNU General Public 5 * License version 2, as published by the Free Software Foundation, and 6 * may be copied, distributed, and modified under those terms. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 */ 14 15 #ifndef __DRIVERS_THERMAL_TEGRA_SOCTHERM_H 16 #define __DRIVERS_THERMAL_TEGRA_SOCTHERM_H 17 18 #define SENSOR_CONFIG2 8 19 #define SENSOR_CONFIG2_THERMA_MASK (0xffff << 16) 20 #define SENSOR_CONFIG2_THERMA_SHIFT 16 21 #define SENSOR_CONFIG2_THERMB_MASK 0xffff 22 #define SENSOR_CONFIG2_THERMB_SHIFT 0 23 24 #define THERMCTL_THERMTRIP_CTL 0x80 25 /* BITs are defined in device file */ 26 27 #define SENSOR_PDIV 0x1c0 28 #define SENSOR_PDIV_CPU_MASK (0xf << 12) 29 #define SENSOR_PDIV_GPU_MASK (0xf << 8) 30 #define SENSOR_PDIV_MEM_MASK (0xf << 4) 31 #define SENSOR_PDIV_PLLX_MASK (0xf << 0) 32 33 #define SENSOR_HOTSPOT_OFF 0x1c4 34 #define SENSOR_HOTSPOT_CPU_MASK (0xff << 16) 35 #define SENSOR_HOTSPOT_GPU_MASK (0xff << 8) 36 #define SENSOR_HOTSPOT_MEM_MASK (0xff << 0) 37 38 #define SENSOR_TEMP1 0x1c8 39 #define SENSOR_TEMP1_CPU_TEMP_MASK (0xffff << 16) 40 #define SENSOR_TEMP1_GPU_TEMP_MASK 0xffff 41 #define SENSOR_TEMP2 0x1cc 42 #define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16) 43 #define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff 44 45 /** 46 * struct tegra_tsensor_group - SOC_THERM sensor group data 47 * @name: short name of the temperature sensor group 48 * @id: numeric ID of the temperature sensor group 49 * @sensor_temp_offset: offset of the SENSOR_TEMP* register 50 * @sensor_temp_mask: bit mask for this sensor group in SENSOR_TEMP* register 51 * @pdiv: the sensor count post-divider to use during runtime 52 * @pdiv_ate: the sensor count post-divider used during automated test 53 * @pdiv_mask: register bitfield mask for the PDIV field for this sensor 54 * @pllx_hotspot_diff: hotspot offset from the PLLX sensor, must be 0 for 55 PLLX sensor group 56 * @pllx_hotspot_mask: register bitfield mask for the HOTSPOT field 57 */ 58 struct tegra_tsensor_group { 59 const char *name; 60 u8 id; 61 u16 sensor_temp_offset; 62 u32 sensor_temp_mask; 63 u32 pdiv, pdiv_ate, pdiv_mask; 64 u32 pllx_hotspot_diff, pllx_hotspot_mask; 65 u32 thermtrip_enable_mask; 66 u32 thermtrip_any_en_mask; 67 u32 thermtrip_threshold_mask; 68 }; 69 70 struct tegra_tsensor_configuration { 71 u32 tall, tiddq_en, ten_count, pdiv, pdiv_ate, tsample, tsample_ate; 72 }; 73 74 struct tegra_tsensor { 75 const char *name; 76 const u32 base; 77 const struct tegra_tsensor_configuration *config; 78 const u32 calib_fuse_offset; 79 /* 80 * Correction values used to modify values read from 81 * calibration fuses 82 */ 83 const s32 fuse_corr_alpha, fuse_corr_beta; 84 const struct tegra_tsensor_group *group; 85 }; 86 87 struct tegra_soctherm_fuse { 88 u32 fuse_base_cp_mask, fuse_base_cp_shift; 89 u32 fuse_base_ft_mask, fuse_base_ft_shift; 90 u32 fuse_shift_ft_mask, fuse_shift_ft_shift; 91 u32 fuse_spare_realignment; 92 }; 93 94 struct tsensor_shared_calib { 95 u32 base_cp, base_ft; 96 u32 actual_temp_cp, actual_temp_ft; 97 }; 98 99 struct tegra_soctherm_soc { 100 const struct tegra_tsensor *tsensors; 101 const unsigned int num_tsensors; 102 const struct tegra_tsensor_group **ttgs; 103 const unsigned int num_ttgs; 104 const struct tegra_soctherm_fuse *tfuse; 105 const int thresh_grain; 106 }; 107 108 int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse, 109 struct tsensor_shared_calib *shared); 110 int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor, 111 const struct tsensor_shared_calib *shared, 112 u32 *calib); 113 114 #ifdef CONFIG_ARCH_TEGRA_124_SOC 115 extern const struct tegra_soctherm_soc tegra124_soctherm; 116 #endif 117 118 #ifdef CONFIG_ARCH_TEGRA_132_SOC 119 extern const struct tegra_soctherm_soc tegra132_soctherm; 120 #endif 121 122 #ifdef CONFIG_ARCH_TEGRA_210_SOC 123 extern const struct tegra_soctherm_soc tegra210_soctherm; 124 #endif 125 126 #endif 127 128