19c92ab61SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
265b6d57cSWei Ni /*
365b6d57cSWei Ni * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
465b6d57cSWei Ni */
565b6d57cSWei Ni
665b6d57cSWei Ni #include <linux/module.h>
765b6d57cSWei Ni #include <linux/platform_device.h>
865b6d57cSWei Ni #include <soc/tegra/fuse.h>
965b6d57cSWei Ni
1065b6d57cSWei Ni #include "soctherm.h"
1165b6d57cSWei Ni
1265b6d57cSWei Ni #define NOMINAL_CALIB_FT 105
1365b6d57cSWei Ni #define NOMINAL_CALIB_CP 25
1465b6d57cSWei Ni
1565b6d57cSWei Ni #define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff
1665b6d57cSWei Ni #define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13)
1765b6d57cSWei Ni #define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13
1865b6d57cSWei Ni
1965b6d57cSWei Ni #define FUSE_TSENSOR_COMMON 0x180
2065b6d57cSWei Ni
2165b6d57cSWei Ni /*
228204104fSWei Ni * Tegra210: Layout of bits in FUSE_TSENSOR_COMMON:
238204104fSWei Ni * 3 2 1 0
248204104fSWei Ni * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
258204104fSWei Ni * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
268204104fSWei Ni * | BASE_FT | BASE_CP | SHFT_FT | SHIFT_CP |
278204104fSWei Ni * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
288204104fSWei Ni *
2965b6d57cSWei Ni * Tegra12x, etc:
308204104fSWei Ni * In chips prior to Tegra210, this fuse was incorrectly sized as 26 bits,
318204104fSWei Ni * and didn't hold SHIFT_CP in [31:26]. Therefore these missing six bits
328204104fSWei Ni * were obtained via the FUSE_SPARE_REALIGNMENT_REG register [5:0].
338204104fSWei Ni *
3465b6d57cSWei Ni * FUSE_TSENSOR_COMMON:
3565b6d57cSWei Ni * 3 2 1 0
3665b6d57cSWei Ni * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
3765b6d57cSWei Ni * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
3865b6d57cSWei Ni * |-----------| SHFT_FT | BASE_FT | BASE_CP |
3965b6d57cSWei Ni * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
4065b6d57cSWei Ni *
4165b6d57cSWei Ni * FUSE_SPARE_REALIGNMENT_REG:
4265b6d57cSWei Ni * 3 2 1 0
4365b6d57cSWei Ni * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
4465b6d57cSWei Ni * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
4565b6d57cSWei Ni * |---------------------------------------------------| SHIFT_CP |
4665b6d57cSWei Ni * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
4765b6d57cSWei Ni */
4865b6d57cSWei Ni
4965b6d57cSWei Ni #define CALIB_COEFFICIENT 1000000LL
5065b6d57cSWei Ni
5165b6d57cSWei Ni /**
5265b6d57cSWei Ni * div64_s64_precise() - wrapper for div64_s64()
5365b6d57cSWei Ni * @a: the dividend
5465b6d57cSWei Ni * @b: the divisor
5565b6d57cSWei Ni *
5665b6d57cSWei Ni * Implements division with fairly accurate rounding instead of truncation by
5765b6d57cSWei Ni * shifting the dividend to the left by 16 so that the quotient has a
5865b6d57cSWei Ni * much higher precision.
5965b6d57cSWei Ni *
6065b6d57cSWei Ni * Return: the quotient of a / b.
6165b6d57cSWei Ni */
div64_s64_precise(s64 a,s32 b)6265b6d57cSWei Ni static s64 div64_s64_precise(s64 a, s32 b)
6365b6d57cSWei Ni {
6465b6d57cSWei Ni s64 r, al;
6565b6d57cSWei Ni
6665b6d57cSWei Ni /* Scale up for increased precision division */
6765b6d57cSWei Ni al = a << 16;
6865b6d57cSWei Ni
6965b6d57cSWei Ni r = div64_s64(al * 2 + 1, 2 * b);
7065b6d57cSWei Ni return r >> 16;
7165b6d57cSWei Ni }
7265b6d57cSWei Ni
tegra_calc_shared_calib(const struct tegra_soctherm_fuse * tfuse,struct tsensor_shared_calib * shared)7365b6d57cSWei Ni int tegra_calc_shared_calib(const struct tegra_soctherm_fuse *tfuse,
7465b6d57cSWei Ni struct tsensor_shared_calib *shared)
7565b6d57cSWei Ni {
7665b6d57cSWei Ni u32 val;
7765b6d57cSWei Ni s32 shifted_cp, shifted_ft;
7865b6d57cSWei Ni int err;
7965b6d57cSWei Ni
8065b6d57cSWei Ni err = tegra_fuse_readl(FUSE_TSENSOR_COMMON, &val);
8165b6d57cSWei Ni if (err)
8265b6d57cSWei Ni return err;
8365b6d57cSWei Ni
8465b6d57cSWei Ni shared->base_cp = (val & tfuse->fuse_base_cp_mask) >>
8565b6d57cSWei Ni tfuse->fuse_base_cp_shift;
8665b6d57cSWei Ni shared->base_ft = (val & tfuse->fuse_base_ft_mask) >>
8765b6d57cSWei Ni tfuse->fuse_base_ft_shift;
8865b6d57cSWei Ni
8965b6d57cSWei Ni shifted_ft = (val & tfuse->fuse_shift_ft_mask) >>
9065b6d57cSWei Ni tfuse->fuse_shift_ft_shift;
9165b6d57cSWei Ni shifted_ft = sign_extend32(shifted_ft, 4);
9265b6d57cSWei Ni
9365b6d57cSWei Ni if (tfuse->fuse_spare_realignment) {
9465b6d57cSWei Ni err = tegra_fuse_readl(tfuse->fuse_spare_realignment, &val);
9565b6d57cSWei Ni if (err)
9665b6d57cSWei Ni return err;
9765b6d57cSWei Ni }
9865b6d57cSWei Ni
9965b6d57cSWei Ni shifted_cp = sign_extend32(val, 5);
10065b6d57cSWei Ni
10165b6d57cSWei Ni shared->actual_temp_cp = 2 * NOMINAL_CALIB_CP + shifted_cp;
10265b6d57cSWei Ni shared->actual_temp_ft = 2 * NOMINAL_CALIB_FT + shifted_ft;
10365b6d57cSWei Ni
10465b6d57cSWei Ni return 0;
10565b6d57cSWei Ni }
10665b6d57cSWei Ni
tegra_calc_tsensor_calib(const struct tegra_tsensor * sensor,const struct tsensor_shared_calib * shared,u32 * calibration)10765b6d57cSWei Ni int tegra_calc_tsensor_calib(const struct tegra_tsensor *sensor,
10865b6d57cSWei Ni const struct tsensor_shared_calib *shared,
10965b6d57cSWei Ni u32 *calibration)
11065b6d57cSWei Ni {
11165b6d57cSWei Ni const struct tegra_tsensor_group *sensor_group;
11265b6d57cSWei Ni u32 val, calib;
11365b6d57cSWei Ni s32 actual_tsensor_ft, actual_tsensor_cp;
11465b6d57cSWei Ni s32 delta_sens, delta_temp;
11565b6d57cSWei Ni s32 mult, div;
11665b6d57cSWei Ni s16 therma, thermb;
11765b6d57cSWei Ni s64 temp;
11865b6d57cSWei Ni int err;
11965b6d57cSWei Ni
12065b6d57cSWei Ni sensor_group = sensor->group;
12165b6d57cSWei Ni
12265b6d57cSWei Ni err = tegra_fuse_readl(sensor->calib_fuse_offset, &val);
12365b6d57cSWei Ni if (err)
12465b6d57cSWei Ni return err;
12565b6d57cSWei Ni
12665b6d57cSWei Ni actual_tsensor_cp = (shared->base_cp * 64) + sign_extend32(val, 12);
12765b6d57cSWei Ni val = (val & FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK) >>
12865b6d57cSWei Ni FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT;
12965b6d57cSWei Ni actual_tsensor_ft = (shared->base_ft * 32) + sign_extend32(val, 12);
13065b6d57cSWei Ni
13165b6d57cSWei Ni delta_sens = actual_tsensor_ft - actual_tsensor_cp;
13265b6d57cSWei Ni delta_temp = shared->actual_temp_ft - shared->actual_temp_cp;
13365b6d57cSWei Ni
13465b6d57cSWei Ni mult = sensor_group->pdiv * sensor->config->tsample_ate;
13565b6d57cSWei Ni div = sensor->config->tsample * sensor_group->pdiv_ate;
13665b6d57cSWei Ni
13765b6d57cSWei Ni temp = (s64)delta_temp * (1LL << 13) * mult;
13865b6d57cSWei Ni therma = div64_s64_precise(temp, (s64)delta_sens * div);
13965b6d57cSWei Ni
14065b6d57cSWei Ni temp = ((s64)actual_tsensor_ft * shared->actual_temp_cp) -
14165b6d57cSWei Ni ((s64)actual_tsensor_cp * shared->actual_temp_ft);
14265b6d57cSWei Ni thermb = div64_s64_precise(temp, delta_sens);
14365b6d57cSWei Ni
14465b6d57cSWei Ni temp = (s64)therma * sensor->fuse_corr_alpha;
14565b6d57cSWei Ni therma = div64_s64_precise(temp, CALIB_COEFFICIENT);
14665b6d57cSWei Ni
14765b6d57cSWei Ni temp = (s64)thermb * sensor->fuse_corr_alpha + sensor->fuse_corr_beta;
14865b6d57cSWei Ni thermb = div64_s64_precise(temp, CALIB_COEFFICIENT);
14965b6d57cSWei Ni
15065b6d57cSWei Ni calib = ((u16)therma << SENSOR_CONFIG2_THERMA_SHIFT) |
15165b6d57cSWei Ni ((u16)thermb << SENSOR_CONFIG2_THERMB_SHIFT);
15265b6d57cSWei Ni
15365b6d57cSWei Ni *calibration = calib;
15465b6d57cSWei Ni
15565b6d57cSWei Ni return 0;
15665b6d57cSWei Ni }
15765b6d57cSWei Ni
15865b6d57cSWei Ni MODULE_AUTHOR("Wei Ni <wni@nvidia.com>");
15965b6d57cSWei Ni MODULE_DESCRIPTION("Tegra SOCTHERM fuse management");
16065b6d57cSWei Ni MODULE_LICENSE("GPL v2");
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