1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd 4 * Caesar Wang <wxt@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/of_irq.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 #include <linux/thermal.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/pinctrl/consumer.h> 21 22 /** 23 * If the temperature over a period of time High, 24 * the resulting TSHUT gave CRU module,let it reset the entire chip, 25 * or via GPIO give PMIC. 26 */ 27 enum tshut_mode { 28 TSHUT_MODE_CRU = 0, 29 TSHUT_MODE_GPIO, 30 }; 31 32 /** 33 * The system Temperature Sensors tshut(tshut) polarity 34 * the bit 8 is tshut polarity. 35 * 0: low active, 1: high active 36 */ 37 enum tshut_polarity { 38 TSHUT_LOW_ACTIVE = 0, 39 TSHUT_HIGH_ACTIVE, 40 }; 41 42 /** 43 * The system has two Temperature Sensors. 44 * sensor0 is for CPU, and sensor1 is for GPU. 45 */ 46 enum sensor_id { 47 SENSOR_CPU = 0, 48 SENSOR_GPU, 49 }; 50 51 /** 52 * The conversion table has the adc value and temperature. 53 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) 54 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) 55 */ 56 enum adc_sort_mode { 57 ADC_DECREMENT = 0, 58 ADC_INCREMENT, 59 }; 60 61 /** 62 * The max sensors is two in rockchip SoCs. 63 * Two sensors: CPU and GPU sensor. 64 */ 65 #define SOC_MAX_SENSORS 2 66 67 /** 68 * struct chip_tsadc_table - hold information about chip-specific differences 69 * @id: conversion table 70 * @length: size of conversion table 71 * @data_mask: mask to apply on data inputs 72 * @mode: sort mode of this adc variant (incrementing or decrementing) 73 */ 74 struct chip_tsadc_table { 75 const struct tsadc_table *id; 76 unsigned int length; 77 u32 data_mask; 78 enum adc_sort_mode mode; 79 }; 80 81 /** 82 * struct rockchip_tsadc_chip - hold the private data of tsadc chip 83 * @chn_id[SOC_MAX_SENSORS]: the sensor id of chip correspond to the channel 84 * @chn_num: the channel number of tsadc chip 85 * @tshut_temp: the hardware-controlled shutdown temperature value 86 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) 87 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) 88 * @initialize: SoC special initialize tsadc controller method 89 * @irq_ack: clear the interrupt 90 * @get_temp: get the temperature 91 * @set_alarm_temp: set the high temperature interrupt 92 * @set_tshut_temp: set the hardware-controlled shutdown temperature 93 * @set_tshut_mode: set the hardware-controlled shutdown mode 94 * @table: the chip-specific conversion table 95 */ 96 struct rockchip_tsadc_chip { 97 /* The sensor id of chip correspond to the ADC channel */ 98 int chn_id[SOC_MAX_SENSORS]; 99 int chn_num; 100 101 /* The hardware-controlled tshut property */ 102 int tshut_temp; 103 enum tshut_mode tshut_mode; 104 enum tshut_polarity tshut_polarity; 105 106 /* Chip-wide methods */ 107 void (*initialize)(struct regmap *grf, 108 void __iomem *reg, enum tshut_polarity p); 109 void (*irq_ack)(void __iomem *reg); 110 void (*control)(void __iomem *reg, bool on); 111 112 /* Per-sensor methods */ 113 int (*get_temp)(const struct chip_tsadc_table *table, 114 int chn, void __iomem *reg, int *temp); 115 int (*set_alarm_temp)(const struct chip_tsadc_table *table, 116 int chn, void __iomem *reg, int temp); 117 int (*set_tshut_temp)(const struct chip_tsadc_table *table, 118 int chn, void __iomem *reg, int temp); 119 void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); 120 121 /* Per-table methods */ 122 struct chip_tsadc_table table; 123 }; 124 125 /** 126 * struct rockchip_thermal_sensor - hold the information of thermal sensor 127 * @thermal: pointer to the platform/configuration data 128 * @tzd: pointer to a thermal zone 129 * @id: identifier of the thermal sensor 130 */ 131 struct rockchip_thermal_sensor { 132 struct rockchip_thermal_data *thermal; 133 struct thermal_zone_device *tzd; 134 int id; 135 }; 136 137 /** 138 * struct rockchip_thermal_data - hold the private data of thermal driver 139 * @chip: pointer to the platform/configuration data 140 * @pdev: platform device of thermal 141 * @reset: the reset controller of tsadc 142 * @sensors[SOC_MAX_SENSORS]: the thermal sensor 143 * @clk: the controller clock is divided by the exteral 24MHz 144 * @pclk: the advanced peripherals bus clock 145 * @grf: the general register file will be used to do static set by software 146 * @regs: the base address of tsadc controller 147 * @tshut_temp: the hardware-controlled shutdown temperature value 148 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) 149 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) 150 */ 151 struct rockchip_thermal_data { 152 const struct rockchip_tsadc_chip *chip; 153 struct platform_device *pdev; 154 struct reset_control *reset; 155 156 struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS]; 157 158 struct clk *clk; 159 struct clk *pclk; 160 161 struct regmap *grf; 162 void __iomem *regs; 163 164 int tshut_temp; 165 enum tshut_mode tshut_mode; 166 enum tshut_polarity tshut_polarity; 167 }; 168 169 /** 170 * TSADC Sensor Register description: 171 * 172 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it. 173 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399) 174 * 175 */ 176 #define TSADCV2_USER_CON 0x00 177 #define TSADCV2_AUTO_CON 0x04 178 #define TSADCV2_INT_EN 0x08 179 #define TSADCV2_INT_PD 0x0c 180 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) 181 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) 182 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) 183 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 184 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 185 #define TSADCV2_AUTO_PERIOD 0x68 186 #define TSADCV2_AUTO_PERIOD_HT 0x6c 187 188 #define TSADCV2_AUTO_EN BIT(0) 189 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) 190 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) 191 192 #define TSADCV3_AUTO_Q_SEL_EN BIT(1) 193 194 #define TSADCV2_INT_SRC_EN(chn) BIT(chn) 195 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) 196 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) 197 198 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) 199 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) 200 201 #define TSADCV2_DATA_MASK 0xfff 202 #define TSADCV3_DATA_MASK 0x3ff 203 204 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 205 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 206 #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */ 207 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */ 208 #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */ 209 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */ 210 211 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ 212 213 #define GRF_SARADC_TESTBIT 0x0e644 214 #define GRF_TSADC_TESTBIT_L 0x0e648 215 #define GRF_TSADC_TESTBIT_H 0x0e64c 216 217 #define PX30_GRF_SOC_CON2 0x0408 218 219 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) 220 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) 221 #define GRF_TSADC_VCM_EN_L (0x10001 << 7) 222 #define GRF_TSADC_VCM_EN_H (0x10001 << 7) 223 224 #define GRF_CON_TSADC_CH_INV (0x10001 << 1) 225 226 /** 227 * struct tsadc_table - code to temperature conversion table 228 * @code: the value of adc channel 229 * @temp: the temperature 230 * Note: 231 * code to temperature mapping of the temperature sensor is a piece wise linear 232 * curve.Any temperature, code faling between to 2 give temperatures can be 233 * linearly interpolated. 234 * Code to Temperature mapping should be updated based on manufacturer results. 235 */ 236 struct tsadc_table { 237 u32 code; 238 int temp; 239 }; 240 241 static const struct tsadc_table rv1108_table[] = { 242 {0, -40000}, 243 {374, -40000}, 244 {382, -35000}, 245 {389, -30000}, 246 {397, -25000}, 247 {405, -20000}, 248 {413, -15000}, 249 {421, -10000}, 250 {429, -5000}, 251 {436, 0}, 252 {444, 5000}, 253 {452, 10000}, 254 {460, 15000}, 255 {468, 20000}, 256 {476, 25000}, 257 {483, 30000}, 258 {491, 35000}, 259 {499, 40000}, 260 {507, 45000}, 261 {515, 50000}, 262 {523, 55000}, 263 {531, 60000}, 264 {539, 65000}, 265 {547, 70000}, 266 {555, 75000}, 267 {562, 80000}, 268 {570, 85000}, 269 {578, 90000}, 270 {586, 95000}, 271 {594, 100000}, 272 {602, 105000}, 273 {610, 110000}, 274 {618, 115000}, 275 {626, 120000}, 276 {634, 125000}, 277 {TSADCV2_DATA_MASK, 125000}, 278 }; 279 280 static const struct tsadc_table rk3228_code_table[] = { 281 {0, -40000}, 282 {588, -40000}, 283 {593, -35000}, 284 {598, -30000}, 285 {603, -25000}, 286 {608, -20000}, 287 {613, -15000}, 288 {618, -10000}, 289 {623, -5000}, 290 {629, 0}, 291 {634, 5000}, 292 {639, 10000}, 293 {644, 15000}, 294 {649, 20000}, 295 {654, 25000}, 296 {660, 30000}, 297 {665, 35000}, 298 {670, 40000}, 299 {675, 45000}, 300 {681, 50000}, 301 {686, 55000}, 302 {691, 60000}, 303 {696, 65000}, 304 {702, 70000}, 305 {707, 75000}, 306 {712, 80000}, 307 {717, 85000}, 308 {723, 90000}, 309 {728, 95000}, 310 {733, 100000}, 311 {738, 105000}, 312 {744, 110000}, 313 {749, 115000}, 314 {754, 120000}, 315 {760, 125000}, 316 {TSADCV2_DATA_MASK, 125000}, 317 }; 318 319 static const struct tsadc_table rk3288_code_table[] = { 320 {TSADCV2_DATA_MASK, -40000}, 321 {3800, -40000}, 322 {3792, -35000}, 323 {3783, -30000}, 324 {3774, -25000}, 325 {3765, -20000}, 326 {3756, -15000}, 327 {3747, -10000}, 328 {3737, -5000}, 329 {3728, 0}, 330 {3718, 5000}, 331 {3708, 10000}, 332 {3698, 15000}, 333 {3688, 20000}, 334 {3678, 25000}, 335 {3667, 30000}, 336 {3656, 35000}, 337 {3645, 40000}, 338 {3634, 45000}, 339 {3623, 50000}, 340 {3611, 55000}, 341 {3600, 60000}, 342 {3588, 65000}, 343 {3575, 70000}, 344 {3563, 75000}, 345 {3550, 80000}, 346 {3537, 85000}, 347 {3524, 90000}, 348 {3510, 95000}, 349 {3496, 100000}, 350 {3482, 105000}, 351 {3467, 110000}, 352 {3452, 115000}, 353 {3437, 120000}, 354 {3421, 125000}, 355 {0, 125000}, 356 }; 357 358 static const struct tsadc_table rk3328_code_table[] = { 359 {0, -40000}, 360 {296, -40000}, 361 {304, -35000}, 362 {313, -30000}, 363 {331, -20000}, 364 {340, -15000}, 365 {349, -10000}, 366 {359, -5000}, 367 {368, 0}, 368 {378, 5000}, 369 {388, 10000}, 370 {398, 15000}, 371 {408, 20000}, 372 {418, 25000}, 373 {429, 30000}, 374 {440, 35000}, 375 {451, 40000}, 376 {462, 45000}, 377 {473, 50000}, 378 {485, 55000}, 379 {496, 60000}, 380 {508, 65000}, 381 {521, 70000}, 382 {533, 75000}, 383 {546, 80000}, 384 {559, 85000}, 385 {572, 90000}, 386 {586, 95000}, 387 {600, 100000}, 388 {614, 105000}, 389 {629, 110000}, 390 {644, 115000}, 391 {659, 120000}, 392 {675, 125000}, 393 {TSADCV2_DATA_MASK, 125000}, 394 }; 395 396 static const struct tsadc_table rk3368_code_table[] = { 397 {0, -40000}, 398 {106, -40000}, 399 {108, -35000}, 400 {110, -30000}, 401 {112, -25000}, 402 {114, -20000}, 403 {116, -15000}, 404 {118, -10000}, 405 {120, -5000}, 406 {122, 0}, 407 {124, 5000}, 408 {126, 10000}, 409 {128, 15000}, 410 {130, 20000}, 411 {132, 25000}, 412 {134, 30000}, 413 {136, 35000}, 414 {138, 40000}, 415 {140, 45000}, 416 {142, 50000}, 417 {144, 55000}, 418 {146, 60000}, 419 {148, 65000}, 420 {150, 70000}, 421 {152, 75000}, 422 {154, 80000}, 423 {156, 85000}, 424 {158, 90000}, 425 {160, 95000}, 426 {162, 100000}, 427 {163, 105000}, 428 {165, 110000}, 429 {167, 115000}, 430 {169, 120000}, 431 {171, 125000}, 432 {TSADCV3_DATA_MASK, 125000}, 433 }; 434 435 static const struct tsadc_table rk3399_code_table[] = { 436 {0, -40000}, 437 {402, -40000}, 438 {410, -35000}, 439 {419, -30000}, 440 {427, -25000}, 441 {436, -20000}, 442 {444, -15000}, 443 {453, -10000}, 444 {461, -5000}, 445 {470, 0}, 446 {478, 5000}, 447 {487, 10000}, 448 {496, 15000}, 449 {504, 20000}, 450 {513, 25000}, 451 {521, 30000}, 452 {530, 35000}, 453 {538, 40000}, 454 {547, 45000}, 455 {555, 50000}, 456 {564, 55000}, 457 {573, 60000}, 458 {581, 65000}, 459 {590, 70000}, 460 {599, 75000}, 461 {607, 80000}, 462 {616, 85000}, 463 {624, 90000}, 464 {633, 95000}, 465 {642, 100000}, 466 {650, 105000}, 467 {659, 110000}, 468 {668, 115000}, 469 {677, 120000}, 470 {685, 125000}, 471 {TSADCV3_DATA_MASK, 125000}, 472 }; 473 474 static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table, 475 int temp) 476 { 477 int high, low, mid; 478 unsigned long num; 479 unsigned int denom; 480 u32 error = table->data_mask; 481 482 low = 0; 483 high = (table->length - 1) - 1; /* ignore the last check for table */ 484 mid = (high + low) / 2; 485 486 /* Return mask code data when the temp is over table range */ 487 if (temp < table->id[low].temp || temp > table->id[high].temp) 488 goto exit; 489 490 while (low <= high) { 491 if (temp == table->id[mid].temp) 492 return table->id[mid].code; 493 else if (temp < table->id[mid].temp) 494 high = mid - 1; 495 else 496 low = mid + 1; 497 mid = (low + high) / 2; 498 } 499 500 /* 501 * The conversion code granularity provided by the table. Let's 502 * assume that the relationship between temperature and 503 * analog value between 2 table entries is linear and interpolate 504 * to produce less granular result. 505 */ 506 num = abs(table->id[mid + 1].code - table->id[mid].code); 507 num *= temp - table->id[mid].temp; 508 denom = table->id[mid + 1].temp - table->id[mid].temp; 509 510 switch (table->mode) { 511 case ADC_DECREMENT: 512 return table->id[mid].code - (num / denom); 513 case ADC_INCREMENT: 514 return table->id[mid].code + (num / denom); 515 default: 516 pr_err("%s: unknown table mode: %d\n", __func__, table->mode); 517 return error; 518 } 519 520 exit: 521 pr_err("%s: invalid temperature, temp=%d error=%d\n", 522 __func__, temp, error); 523 return error; 524 } 525 526 static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table, 527 u32 code, int *temp) 528 { 529 unsigned int low = 1; 530 unsigned int high = table->length - 1; 531 unsigned int mid = (low + high) / 2; 532 unsigned int num; 533 unsigned long denom; 534 535 WARN_ON(table->length < 2); 536 537 switch (table->mode) { 538 case ADC_DECREMENT: 539 code &= table->data_mask; 540 if (code <= table->id[high].code) 541 return -EAGAIN; /* Incorrect reading */ 542 543 while (low <= high) { 544 if (code >= table->id[mid].code && 545 code < table->id[mid - 1].code) 546 break; 547 else if (code < table->id[mid].code) 548 low = mid + 1; 549 else 550 high = mid - 1; 551 552 mid = (low + high) / 2; 553 } 554 break; 555 case ADC_INCREMENT: 556 code &= table->data_mask; 557 if (code < table->id[low].code) 558 return -EAGAIN; /* Incorrect reading */ 559 560 while (low <= high) { 561 if (code <= table->id[mid].code && 562 code > table->id[mid - 1].code) 563 break; 564 else if (code > table->id[mid].code) 565 low = mid + 1; 566 else 567 high = mid - 1; 568 569 mid = (low + high) / 2; 570 } 571 break; 572 default: 573 pr_err("%s: unknown table mode: %d\n", __func__, table->mode); 574 return -EINVAL; 575 } 576 577 /* 578 * The 5C granularity provided by the table is too much. Let's 579 * assume that the relationship between sensor readings and 580 * temperature between 2 table entries is linear and interpolate 581 * to produce less granular result. 582 */ 583 num = table->id[mid].temp - table->id[mid - 1].temp; 584 num *= abs(table->id[mid - 1].code - code); 585 denom = abs(table->id[mid - 1].code - table->id[mid].code); 586 *temp = table->id[mid - 1].temp + (num / denom); 587 588 return 0; 589 } 590 591 /** 592 * rk_tsadcv2_initialize - initialize TASDC Controller. 593 * 594 * (1) Set TSADC_V2_AUTO_PERIOD: 595 * Configure the interleave between every two accessing of 596 * TSADC in normal operation. 597 * 598 * (2) Set TSADCV2_AUTO_PERIOD_HT: 599 * Configure the interleave between every two accessing of 600 * TSADC after the temperature is higher than COM_SHUT or COM_INT. 601 * 602 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: 603 * If the temperature is higher than COMP_INT or COMP_SHUT for 604 * "debounce" times, TSADC controller will generate interrupt or TSHUT. 605 */ 606 static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs, 607 enum tshut_polarity tshut_polarity) 608 { 609 if (tshut_polarity == TSHUT_HIGH_ACTIVE) 610 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 611 regs + TSADCV2_AUTO_CON); 612 else 613 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 614 regs + TSADCV2_AUTO_CON); 615 616 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); 617 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 618 regs + TSADCV2_HIGHT_INT_DEBOUNCE); 619 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, 620 regs + TSADCV2_AUTO_PERIOD_HT); 621 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 622 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 623 } 624 625 /** 626 * rk_tsadcv3_initialize - initialize TASDC Controller. 627 * 628 * (1) The tsadc control power sequence. 629 * 630 * (2) Set TSADC_V2_AUTO_PERIOD: 631 * Configure the interleave between every two accessing of 632 * TSADC in normal operation. 633 * 634 * (2) Set TSADCV2_AUTO_PERIOD_HT: 635 * Configure the interleave between every two accessing of 636 * TSADC after the temperature is higher than COM_SHUT or COM_INT. 637 * 638 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: 639 * If the temperature is higher than COMP_INT or COMP_SHUT for 640 * "debounce" times, TSADC controller will generate interrupt or TSHUT. 641 */ 642 static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs, 643 enum tshut_polarity tshut_polarity) 644 { 645 /* The tsadc control power sequence */ 646 if (IS_ERR(grf)) { 647 /* Set interleave value to workround ic time sync issue */ 648 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs + 649 TSADCV2_USER_CON); 650 651 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, 652 regs + TSADCV2_AUTO_PERIOD); 653 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 654 regs + TSADCV2_HIGHT_INT_DEBOUNCE); 655 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, 656 regs + TSADCV2_AUTO_PERIOD_HT); 657 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 658 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 659 660 } else { 661 /* Enable the voltage common mode feature */ 662 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L); 663 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H); 664 665 usleep_range(15, 100); /* The spec note says at least 15 us */ 666 regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON); 667 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON); 668 usleep_range(90, 200); /* The spec note says at least 90 us */ 669 670 writel_relaxed(TSADCV3_AUTO_PERIOD_TIME, 671 regs + TSADCV2_AUTO_PERIOD); 672 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 673 regs + TSADCV2_HIGHT_INT_DEBOUNCE); 674 writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME, 675 regs + TSADCV2_AUTO_PERIOD_HT); 676 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 677 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 678 } 679 680 if (tshut_polarity == TSHUT_HIGH_ACTIVE) 681 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 682 regs + TSADCV2_AUTO_CON); 683 else 684 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 685 regs + TSADCV2_AUTO_CON); 686 } 687 688 static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs, 689 enum tshut_polarity tshut_polarity) 690 { 691 rk_tsadcv2_initialize(grf, regs, tshut_polarity); 692 regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV); 693 } 694 695 static void rk_tsadcv2_irq_ack(void __iomem *regs) 696 { 697 u32 val; 698 699 val = readl_relaxed(regs + TSADCV2_INT_PD); 700 writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); 701 } 702 703 static void rk_tsadcv3_irq_ack(void __iomem *regs) 704 { 705 u32 val; 706 707 val = readl_relaxed(regs + TSADCV2_INT_PD); 708 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); 709 } 710 711 static void rk_tsadcv2_control(void __iomem *regs, bool enable) 712 { 713 u32 val; 714 715 val = readl_relaxed(regs + TSADCV2_AUTO_CON); 716 if (enable) 717 val |= TSADCV2_AUTO_EN; 718 else 719 val &= ~TSADCV2_AUTO_EN; 720 721 writel_relaxed(val, regs + TSADCV2_AUTO_CON); 722 } 723 724 /** 725 * rk_tsadcv3_control - the tsadc controller is enabled or disabled. 726 * 727 * NOTE: TSADC controller works at auto mode, and some SoCs need set the 728 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output 729 * adc value if setting this bit to enable. 730 */ 731 static void rk_tsadcv3_control(void __iomem *regs, bool enable) 732 { 733 u32 val; 734 735 val = readl_relaxed(regs + TSADCV2_AUTO_CON); 736 if (enable) 737 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; 738 else 739 val &= ~TSADCV2_AUTO_EN; 740 741 writel_relaxed(val, regs + TSADCV2_AUTO_CON); 742 } 743 744 static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table, 745 int chn, void __iomem *regs, int *temp) 746 { 747 u32 val; 748 749 val = readl_relaxed(regs + TSADCV2_DATA(chn)); 750 751 return rk_tsadcv2_code_to_temp(table, val, temp); 752 } 753 754 static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table, 755 int chn, void __iomem *regs, int temp) 756 { 757 u32 alarm_value; 758 u32 int_en, int_clr; 759 760 /* 761 * In some cases, some sensors didn't need the trip points, the 762 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm 763 * in the end, ignore this case and disable the high temperature 764 * interrupt. 765 */ 766 if (temp == INT_MAX) { 767 int_clr = readl_relaxed(regs + TSADCV2_INT_EN); 768 int_clr &= ~TSADCV2_INT_SRC_EN(chn); 769 writel_relaxed(int_clr, regs + TSADCV2_INT_EN); 770 return 0; 771 } 772 773 /* Make sure the value is valid */ 774 alarm_value = rk_tsadcv2_temp_to_code(table, temp); 775 if (alarm_value == table->data_mask) 776 return -ERANGE; 777 778 writel_relaxed(alarm_value & table->data_mask, 779 regs + TSADCV2_COMP_INT(chn)); 780 781 int_en = readl_relaxed(regs + TSADCV2_INT_EN); 782 int_en |= TSADCV2_INT_SRC_EN(chn); 783 writel_relaxed(int_en, regs + TSADCV2_INT_EN); 784 785 return 0; 786 } 787 788 static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table, 789 int chn, void __iomem *regs, int temp) 790 { 791 u32 tshut_value, val; 792 793 /* Make sure the value is valid */ 794 tshut_value = rk_tsadcv2_temp_to_code(table, temp); 795 if (tshut_value == table->data_mask) 796 return -ERANGE; 797 798 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn)); 799 800 /* TSHUT will be valid */ 801 val = readl_relaxed(regs + TSADCV2_AUTO_CON); 802 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON); 803 804 return 0; 805 } 806 807 static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, 808 enum tshut_mode mode) 809 { 810 u32 val; 811 812 val = readl_relaxed(regs + TSADCV2_INT_EN); 813 if (mode == TSHUT_MODE_GPIO) { 814 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); 815 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); 816 } else { 817 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); 818 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); 819 } 820 821 writel_relaxed(val, regs + TSADCV2_INT_EN); 822 } 823 824 static const struct rockchip_tsadc_chip px30_tsadc_data = { 825 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 826 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 827 .chn_num = 2, /* 2 channels for tsadc */ 828 829 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 830 .tshut_temp = 95000, 831 832 .initialize = rk_tsadcv4_initialize, 833 .irq_ack = rk_tsadcv3_irq_ack, 834 .control = rk_tsadcv3_control, 835 .get_temp = rk_tsadcv2_get_temp, 836 .set_alarm_temp = rk_tsadcv2_alarm_temp, 837 .set_tshut_temp = rk_tsadcv2_tshut_temp, 838 .set_tshut_mode = rk_tsadcv2_tshut_mode, 839 840 .table = { 841 .id = rk3328_code_table, 842 .length = ARRAY_SIZE(rk3328_code_table), 843 .data_mask = TSADCV2_DATA_MASK, 844 .mode = ADC_INCREMENT, 845 }, 846 }; 847 848 static const struct rockchip_tsadc_chip rv1108_tsadc_data = { 849 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 850 .chn_num = 1, /* one channel for tsadc */ 851 852 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 853 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 854 .tshut_temp = 95000, 855 856 .initialize = rk_tsadcv2_initialize, 857 .irq_ack = rk_tsadcv3_irq_ack, 858 .control = rk_tsadcv3_control, 859 .get_temp = rk_tsadcv2_get_temp, 860 .set_alarm_temp = rk_tsadcv2_alarm_temp, 861 .set_tshut_temp = rk_tsadcv2_tshut_temp, 862 .set_tshut_mode = rk_tsadcv2_tshut_mode, 863 864 .table = { 865 .id = rv1108_table, 866 .length = ARRAY_SIZE(rv1108_table), 867 .data_mask = TSADCV2_DATA_MASK, 868 .mode = ADC_INCREMENT, 869 }, 870 }; 871 872 static const struct rockchip_tsadc_chip rk3228_tsadc_data = { 873 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 874 .chn_num = 1, /* one channel for tsadc */ 875 876 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 877 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 878 .tshut_temp = 95000, 879 880 .initialize = rk_tsadcv2_initialize, 881 .irq_ack = rk_tsadcv3_irq_ack, 882 .control = rk_tsadcv3_control, 883 .get_temp = rk_tsadcv2_get_temp, 884 .set_alarm_temp = rk_tsadcv2_alarm_temp, 885 .set_tshut_temp = rk_tsadcv2_tshut_temp, 886 .set_tshut_mode = rk_tsadcv2_tshut_mode, 887 888 .table = { 889 .id = rk3228_code_table, 890 .length = ARRAY_SIZE(rk3228_code_table), 891 .data_mask = TSADCV3_DATA_MASK, 892 .mode = ADC_INCREMENT, 893 }, 894 }; 895 896 static const struct rockchip_tsadc_chip rk3288_tsadc_data = { 897 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ 898 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ 899 .chn_num = 2, /* two channels for tsadc */ 900 901 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 902 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 903 .tshut_temp = 95000, 904 905 .initialize = rk_tsadcv2_initialize, 906 .irq_ack = rk_tsadcv2_irq_ack, 907 .control = rk_tsadcv2_control, 908 .get_temp = rk_tsadcv2_get_temp, 909 .set_alarm_temp = rk_tsadcv2_alarm_temp, 910 .set_tshut_temp = rk_tsadcv2_tshut_temp, 911 .set_tshut_mode = rk_tsadcv2_tshut_mode, 912 913 .table = { 914 .id = rk3288_code_table, 915 .length = ARRAY_SIZE(rk3288_code_table), 916 .data_mask = TSADCV2_DATA_MASK, 917 .mode = ADC_DECREMENT, 918 }, 919 }; 920 921 static const struct rockchip_tsadc_chip rk3328_tsadc_data = { 922 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 923 .chn_num = 1, /* one channels for tsadc */ 924 925 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 926 .tshut_temp = 95000, 927 928 .initialize = rk_tsadcv2_initialize, 929 .irq_ack = rk_tsadcv3_irq_ack, 930 .control = rk_tsadcv3_control, 931 .get_temp = rk_tsadcv2_get_temp, 932 .set_alarm_temp = rk_tsadcv2_alarm_temp, 933 .set_tshut_temp = rk_tsadcv2_tshut_temp, 934 .set_tshut_mode = rk_tsadcv2_tshut_mode, 935 936 .table = { 937 .id = rk3328_code_table, 938 .length = ARRAY_SIZE(rk3328_code_table), 939 .data_mask = TSADCV2_DATA_MASK, 940 .mode = ADC_INCREMENT, 941 }, 942 }; 943 944 static const struct rockchip_tsadc_chip rk3366_tsadc_data = { 945 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 946 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 947 .chn_num = 2, /* two channels for tsadc */ 948 949 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 950 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 951 .tshut_temp = 95000, 952 953 .initialize = rk_tsadcv3_initialize, 954 .irq_ack = rk_tsadcv3_irq_ack, 955 .control = rk_tsadcv3_control, 956 .get_temp = rk_tsadcv2_get_temp, 957 .set_alarm_temp = rk_tsadcv2_alarm_temp, 958 .set_tshut_temp = rk_tsadcv2_tshut_temp, 959 .set_tshut_mode = rk_tsadcv2_tshut_mode, 960 961 .table = { 962 .id = rk3228_code_table, 963 .length = ARRAY_SIZE(rk3228_code_table), 964 .data_mask = TSADCV3_DATA_MASK, 965 .mode = ADC_INCREMENT, 966 }, 967 }; 968 969 static const struct rockchip_tsadc_chip rk3368_tsadc_data = { 970 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 971 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 972 .chn_num = 2, /* two channels for tsadc */ 973 974 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 975 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 976 .tshut_temp = 95000, 977 978 .initialize = rk_tsadcv2_initialize, 979 .irq_ack = rk_tsadcv2_irq_ack, 980 .control = rk_tsadcv2_control, 981 .get_temp = rk_tsadcv2_get_temp, 982 .set_alarm_temp = rk_tsadcv2_alarm_temp, 983 .set_tshut_temp = rk_tsadcv2_tshut_temp, 984 .set_tshut_mode = rk_tsadcv2_tshut_mode, 985 986 .table = { 987 .id = rk3368_code_table, 988 .length = ARRAY_SIZE(rk3368_code_table), 989 .data_mask = TSADCV3_DATA_MASK, 990 .mode = ADC_INCREMENT, 991 }, 992 }; 993 994 static const struct rockchip_tsadc_chip rk3399_tsadc_data = { 995 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 996 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 997 .chn_num = 2, /* two channels for tsadc */ 998 999 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1000 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1001 .tshut_temp = 95000, 1002 1003 .initialize = rk_tsadcv3_initialize, 1004 .irq_ack = rk_tsadcv3_irq_ack, 1005 .control = rk_tsadcv3_control, 1006 .get_temp = rk_tsadcv2_get_temp, 1007 .set_alarm_temp = rk_tsadcv2_alarm_temp, 1008 .set_tshut_temp = rk_tsadcv2_tshut_temp, 1009 .set_tshut_mode = rk_tsadcv2_tshut_mode, 1010 1011 .table = { 1012 .id = rk3399_code_table, 1013 .length = ARRAY_SIZE(rk3399_code_table), 1014 .data_mask = TSADCV3_DATA_MASK, 1015 .mode = ADC_INCREMENT, 1016 }, 1017 }; 1018 1019 static const struct of_device_id of_rockchip_thermal_match[] = { 1020 { .compatible = "rockchip,px30-tsadc", 1021 .data = (void *)&px30_tsadc_data, 1022 }, 1023 { 1024 .compatible = "rockchip,rv1108-tsadc", 1025 .data = (void *)&rv1108_tsadc_data, 1026 }, 1027 { 1028 .compatible = "rockchip,rk3228-tsadc", 1029 .data = (void *)&rk3228_tsadc_data, 1030 }, 1031 { 1032 .compatible = "rockchip,rk3288-tsadc", 1033 .data = (void *)&rk3288_tsadc_data, 1034 }, 1035 { 1036 .compatible = "rockchip,rk3328-tsadc", 1037 .data = (void *)&rk3328_tsadc_data, 1038 }, 1039 { 1040 .compatible = "rockchip,rk3366-tsadc", 1041 .data = (void *)&rk3366_tsadc_data, 1042 }, 1043 { 1044 .compatible = "rockchip,rk3368-tsadc", 1045 .data = (void *)&rk3368_tsadc_data, 1046 }, 1047 { 1048 .compatible = "rockchip,rk3399-tsadc", 1049 .data = (void *)&rk3399_tsadc_data, 1050 }, 1051 { /* end */ }, 1052 }; 1053 MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match); 1054 1055 static void 1056 rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on) 1057 { 1058 struct thermal_zone_device *tzd = sensor->tzd; 1059 1060 tzd->ops->set_mode(tzd, 1061 on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED); 1062 } 1063 1064 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev) 1065 { 1066 struct rockchip_thermal_data *thermal = dev; 1067 int i; 1068 1069 dev_dbg(&thermal->pdev->dev, "thermal alarm\n"); 1070 1071 thermal->chip->irq_ack(thermal->regs); 1072 1073 for (i = 0; i < thermal->chip->chn_num; i++) 1074 thermal_zone_device_update(thermal->sensors[i].tzd, 1075 THERMAL_EVENT_UNSPECIFIED); 1076 1077 return IRQ_HANDLED; 1078 } 1079 1080 static int rockchip_thermal_set_trips(void *_sensor, int low, int high) 1081 { 1082 struct rockchip_thermal_sensor *sensor = _sensor; 1083 struct rockchip_thermal_data *thermal = sensor->thermal; 1084 const struct rockchip_tsadc_chip *tsadc = thermal->chip; 1085 1086 dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n", 1087 __func__, sensor->id, low, high); 1088 1089 return tsadc->set_alarm_temp(&tsadc->table, 1090 sensor->id, thermal->regs, high); 1091 } 1092 1093 static int rockchip_thermal_get_temp(void *_sensor, int *out_temp) 1094 { 1095 struct rockchip_thermal_sensor *sensor = _sensor; 1096 struct rockchip_thermal_data *thermal = sensor->thermal; 1097 const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip; 1098 int retval; 1099 1100 retval = tsadc->get_temp(&tsadc->table, 1101 sensor->id, thermal->regs, out_temp); 1102 dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n", 1103 sensor->id, *out_temp, retval); 1104 1105 return retval; 1106 } 1107 1108 static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = { 1109 .get_temp = rockchip_thermal_get_temp, 1110 .set_trips = rockchip_thermal_set_trips, 1111 }; 1112 1113 static int rockchip_configure_from_dt(struct device *dev, 1114 struct device_node *np, 1115 struct rockchip_thermal_data *thermal) 1116 { 1117 u32 shut_temp, tshut_mode, tshut_polarity; 1118 1119 if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) { 1120 dev_warn(dev, 1121 "Missing tshut temp property, using default %d\n", 1122 thermal->chip->tshut_temp); 1123 thermal->tshut_temp = thermal->chip->tshut_temp; 1124 } else { 1125 if (shut_temp > INT_MAX) { 1126 dev_err(dev, "Invalid tshut temperature specified: %d\n", 1127 shut_temp); 1128 return -ERANGE; 1129 } 1130 thermal->tshut_temp = shut_temp; 1131 } 1132 1133 if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) { 1134 dev_warn(dev, 1135 "Missing tshut mode property, using default (%s)\n", 1136 thermal->chip->tshut_mode == TSHUT_MODE_GPIO ? 1137 "gpio" : "cru"); 1138 thermal->tshut_mode = thermal->chip->tshut_mode; 1139 } else { 1140 thermal->tshut_mode = tshut_mode; 1141 } 1142 1143 if (thermal->tshut_mode > 1) { 1144 dev_err(dev, "Invalid tshut mode specified: %d\n", 1145 thermal->tshut_mode); 1146 return -EINVAL; 1147 } 1148 1149 if (of_property_read_u32(np, "rockchip,hw-tshut-polarity", 1150 &tshut_polarity)) { 1151 dev_warn(dev, 1152 "Missing tshut-polarity property, using default (%s)\n", 1153 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ? 1154 "low" : "high"); 1155 thermal->tshut_polarity = thermal->chip->tshut_polarity; 1156 } else { 1157 thermal->tshut_polarity = tshut_polarity; 1158 } 1159 1160 if (thermal->tshut_polarity > 1) { 1161 dev_err(dev, "Invalid tshut-polarity specified: %d\n", 1162 thermal->tshut_polarity); 1163 return -EINVAL; 1164 } 1165 1166 /* The tsadc wont to handle the error in here since some SoCs didn't 1167 * need this property. 1168 */ 1169 thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1170 if (IS_ERR(thermal->grf)) 1171 dev_warn(dev, "Missing rockchip,grf property\n"); 1172 1173 return 0; 1174 } 1175 1176 static int 1177 rockchip_thermal_register_sensor(struct platform_device *pdev, 1178 struct rockchip_thermal_data *thermal, 1179 struct rockchip_thermal_sensor *sensor, 1180 int id) 1181 { 1182 const struct rockchip_tsadc_chip *tsadc = thermal->chip; 1183 int error; 1184 1185 tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); 1186 1187 error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, 1188 thermal->tshut_temp); 1189 if (error) 1190 dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n", 1191 __func__, thermal->tshut_temp, error); 1192 1193 sensor->thermal = thermal; 1194 sensor->id = id; 1195 sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id, 1196 sensor, &rockchip_of_thermal_ops); 1197 if (IS_ERR(sensor->tzd)) { 1198 error = PTR_ERR(sensor->tzd); 1199 dev_err(&pdev->dev, "failed to register sensor %d: %d\n", 1200 id, error); 1201 return error; 1202 } 1203 1204 return 0; 1205 } 1206 1207 /** 1208 * Reset TSADC Controller, reset all tsadc registers. 1209 */ 1210 static void rockchip_thermal_reset_controller(struct reset_control *reset) 1211 { 1212 reset_control_assert(reset); 1213 usleep_range(10, 20); 1214 reset_control_deassert(reset); 1215 } 1216 1217 static int rockchip_thermal_probe(struct platform_device *pdev) 1218 { 1219 struct device_node *np = pdev->dev.of_node; 1220 struct rockchip_thermal_data *thermal; 1221 const struct of_device_id *match; 1222 struct resource *res; 1223 int irq; 1224 int i; 1225 int error; 1226 1227 match = of_match_node(of_rockchip_thermal_match, np); 1228 if (!match) 1229 return -ENXIO; 1230 1231 irq = platform_get_irq(pdev, 0); 1232 if (irq < 0) { 1233 dev_err(&pdev->dev, "no irq resource?\n"); 1234 return -EINVAL; 1235 } 1236 1237 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data), 1238 GFP_KERNEL); 1239 if (!thermal) 1240 return -ENOMEM; 1241 1242 thermal->pdev = pdev; 1243 1244 thermal->chip = (const struct rockchip_tsadc_chip *)match->data; 1245 if (!thermal->chip) 1246 return -EINVAL; 1247 1248 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1249 thermal->regs = devm_ioremap_resource(&pdev->dev, res); 1250 if (IS_ERR(thermal->regs)) 1251 return PTR_ERR(thermal->regs); 1252 1253 thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb"); 1254 if (IS_ERR(thermal->reset)) { 1255 error = PTR_ERR(thermal->reset); 1256 dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); 1257 return error; 1258 } 1259 1260 thermal->clk = devm_clk_get(&pdev->dev, "tsadc"); 1261 if (IS_ERR(thermal->clk)) { 1262 error = PTR_ERR(thermal->clk); 1263 dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); 1264 return error; 1265 } 1266 1267 thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); 1268 if (IS_ERR(thermal->pclk)) { 1269 error = PTR_ERR(thermal->pclk); 1270 dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", 1271 error); 1272 return error; 1273 } 1274 1275 error = clk_prepare_enable(thermal->clk); 1276 if (error) { 1277 dev_err(&pdev->dev, "failed to enable converter clock: %d\n", 1278 error); 1279 return error; 1280 } 1281 1282 error = clk_prepare_enable(thermal->pclk); 1283 if (error) { 1284 dev_err(&pdev->dev, "failed to enable pclk: %d\n", error); 1285 goto err_disable_clk; 1286 } 1287 1288 rockchip_thermal_reset_controller(thermal->reset); 1289 1290 error = rockchip_configure_from_dt(&pdev->dev, np, thermal); 1291 if (error) { 1292 dev_err(&pdev->dev, "failed to parse device tree data: %d\n", 1293 error); 1294 goto err_disable_pclk; 1295 } 1296 1297 thermal->chip->initialize(thermal->grf, thermal->regs, 1298 thermal->tshut_polarity); 1299 1300 for (i = 0; i < thermal->chip->chn_num; i++) { 1301 error = rockchip_thermal_register_sensor(pdev, thermal, 1302 &thermal->sensors[i], 1303 thermal->chip->chn_id[i]); 1304 if (error) { 1305 dev_err(&pdev->dev, 1306 "failed to register sensor[%d] : error = %d\n", 1307 i, error); 1308 goto err_disable_pclk; 1309 } 1310 } 1311 1312 error = devm_request_threaded_irq(&pdev->dev, irq, NULL, 1313 &rockchip_thermal_alarm_irq_thread, 1314 IRQF_ONESHOT, 1315 "rockchip_thermal", thermal); 1316 if (error) { 1317 dev_err(&pdev->dev, 1318 "failed to request tsadc irq: %d\n", error); 1319 goto err_disable_pclk; 1320 } 1321 1322 thermal->chip->control(thermal->regs, true); 1323 1324 for (i = 0; i < thermal->chip->chn_num; i++) 1325 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); 1326 1327 platform_set_drvdata(pdev, thermal); 1328 1329 return 0; 1330 1331 err_disable_pclk: 1332 clk_disable_unprepare(thermal->pclk); 1333 err_disable_clk: 1334 clk_disable_unprepare(thermal->clk); 1335 1336 return error; 1337 } 1338 1339 static int rockchip_thermal_remove(struct platform_device *pdev) 1340 { 1341 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); 1342 int i; 1343 1344 for (i = 0; i < thermal->chip->chn_num; i++) { 1345 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i]; 1346 1347 rockchip_thermal_toggle_sensor(sensor, false); 1348 } 1349 1350 thermal->chip->control(thermal->regs, false); 1351 1352 clk_disable_unprepare(thermal->pclk); 1353 clk_disable_unprepare(thermal->clk); 1354 1355 return 0; 1356 } 1357 1358 static int __maybe_unused rockchip_thermal_suspend(struct device *dev) 1359 { 1360 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); 1361 int i; 1362 1363 for (i = 0; i < thermal->chip->chn_num; i++) 1364 rockchip_thermal_toggle_sensor(&thermal->sensors[i], false); 1365 1366 thermal->chip->control(thermal->regs, false); 1367 1368 clk_disable(thermal->pclk); 1369 clk_disable(thermal->clk); 1370 1371 pinctrl_pm_select_sleep_state(dev); 1372 1373 return 0; 1374 } 1375 1376 static int __maybe_unused rockchip_thermal_resume(struct device *dev) 1377 { 1378 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); 1379 int i; 1380 int error; 1381 1382 error = clk_enable(thermal->clk); 1383 if (error) 1384 return error; 1385 1386 error = clk_enable(thermal->pclk); 1387 if (error) { 1388 clk_disable(thermal->clk); 1389 return error; 1390 } 1391 1392 rockchip_thermal_reset_controller(thermal->reset); 1393 1394 thermal->chip->initialize(thermal->grf, thermal->regs, 1395 thermal->tshut_polarity); 1396 1397 for (i = 0; i < thermal->chip->chn_num; i++) { 1398 int id = thermal->sensors[i].id; 1399 1400 thermal->chip->set_tshut_mode(id, thermal->regs, 1401 thermal->tshut_mode); 1402 1403 error = thermal->chip->set_tshut_temp(&thermal->chip->table, 1404 id, thermal->regs, 1405 thermal->tshut_temp); 1406 if (error) 1407 dev_err(dev, "%s: invalid tshut=%d, error=%d\n", 1408 __func__, thermal->tshut_temp, error); 1409 } 1410 1411 thermal->chip->control(thermal->regs, true); 1412 1413 for (i = 0; i < thermal->chip->chn_num; i++) 1414 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); 1415 1416 pinctrl_pm_select_default_state(dev); 1417 1418 return 0; 1419 } 1420 1421 static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops, 1422 rockchip_thermal_suspend, rockchip_thermal_resume); 1423 1424 static struct platform_driver rockchip_thermal_driver = { 1425 .driver = { 1426 .name = "rockchip-thermal", 1427 .pm = &rockchip_thermal_pm_ops, 1428 .of_match_table = of_rockchip_thermal_match, 1429 }, 1430 .probe = rockchip_thermal_probe, 1431 .remove = rockchip_thermal_remove, 1432 }; 1433 1434 module_platform_driver(rockchip_thermal_driver); 1435 1436 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver"); 1437 MODULE_AUTHOR("Rockchip, Inc."); 1438 MODULE_LICENSE("GPL v2"); 1439 MODULE_ALIAS("platform:rockchip-thermal"); 1440