1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd 4 * Caesar Wang <wxt@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/interrupt.h> 10 #include <linux/io.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_address.h> 14 #include <linux/of_irq.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 #include <linux/thermal.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/pinctrl/consumer.h> 21 22 /* 23 * If the temperature over a period of time High, 24 * the resulting TSHUT gave CRU module,let it reset the entire chip, 25 * or via GPIO give PMIC. 26 */ 27 enum tshut_mode { 28 TSHUT_MODE_CRU = 0, 29 TSHUT_MODE_GPIO, 30 }; 31 32 /* 33 * The system Temperature Sensors tshut(tshut) polarity 34 * the bit 8 is tshut polarity. 35 * 0: low active, 1: high active 36 */ 37 enum tshut_polarity { 38 TSHUT_LOW_ACTIVE = 0, 39 TSHUT_HIGH_ACTIVE, 40 }; 41 42 /* 43 * The system has two Temperature Sensors. 44 * sensor0 is for CPU, and sensor1 is for GPU. 45 */ 46 enum sensor_id { 47 SENSOR_CPU = 0, 48 SENSOR_GPU, 49 }; 50 51 /* 52 * The conversion table has the adc value and temperature. 53 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) 54 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) 55 */ 56 enum adc_sort_mode { 57 ADC_DECREMENT = 0, 58 ADC_INCREMENT, 59 }; 60 61 /** 62 * The max sensors is two in rockchip SoCs. 63 * Two sensors: CPU and GPU sensor. 64 */ 65 #define SOC_MAX_SENSORS 2 66 67 /** 68 * struct chip_tsadc_table - hold information about chip-specific differences 69 * @id: conversion table 70 * @length: size of conversion table 71 * @data_mask: mask to apply on data inputs 72 * @mode: sort mode of this adc variant (incrementing or decrementing) 73 */ 74 struct chip_tsadc_table { 75 const struct tsadc_table *id; 76 unsigned int length; 77 u32 data_mask; 78 enum adc_sort_mode mode; 79 }; 80 81 /** 82 * struct rockchip_tsadc_chip - hold the private data of tsadc chip 83 * @chn_id: array of sensor ids of chip corresponding to the channel 84 * @chn_num: the channel number of tsadc chip 85 * @tshut_temp: the hardware-controlled shutdown temperature value 86 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) 87 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) 88 * @initialize: SoC special initialize tsadc controller method 89 * @irq_ack: clear the interrupt 90 * @control: enable/disable method for the tsadc controller 91 * @get_temp: get the temperature 92 * @set_alarm_temp: set the high temperature interrupt 93 * @set_tshut_temp: set the hardware-controlled shutdown temperature 94 * @set_tshut_mode: set the hardware-controlled shutdown mode 95 * @table: the chip-specific conversion table 96 */ 97 struct rockchip_tsadc_chip { 98 /* The sensor id of chip correspond to the ADC channel */ 99 int chn_id[SOC_MAX_SENSORS]; 100 int chn_num; 101 102 /* The hardware-controlled tshut property */ 103 int tshut_temp; 104 enum tshut_mode tshut_mode; 105 enum tshut_polarity tshut_polarity; 106 107 /* Chip-wide methods */ 108 void (*initialize)(struct regmap *grf, 109 void __iomem *reg, enum tshut_polarity p); 110 void (*irq_ack)(void __iomem *reg); 111 void (*control)(void __iomem *reg, bool on); 112 113 /* Per-sensor methods */ 114 int (*get_temp)(const struct chip_tsadc_table *table, 115 int chn, void __iomem *reg, int *temp); 116 int (*set_alarm_temp)(const struct chip_tsadc_table *table, 117 int chn, void __iomem *reg, int temp); 118 int (*set_tshut_temp)(const struct chip_tsadc_table *table, 119 int chn, void __iomem *reg, int temp); 120 void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); 121 122 /* Per-table methods */ 123 struct chip_tsadc_table table; 124 }; 125 126 /** 127 * struct rockchip_thermal_sensor - hold the information of thermal sensor 128 * @thermal: pointer to the platform/configuration data 129 * @tzd: pointer to a thermal zone 130 * @id: identifier of the thermal sensor 131 */ 132 struct rockchip_thermal_sensor { 133 struct rockchip_thermal_data *thermal; 134 struct thermal_zone_device *tzd; 135 int id; 136 }; 137 138 /** 139 * struct rockchip_thermal_data - hold the private data of thermal driver 140 * @chip: pointer to the platform/configuration data 141 * @pdev: platform device of thermal 142 * @reset: the reset controller of tsadc 143 * @sensors: array of thermal sensors 144 * @clk: the controller clock is divided by the exteral 24MHz 145 * @pclk: the advanced peripherals bus clock 146 * @grf: the general register file will be used to do static set by software 147 * @regs: the base address of tsadc controller 148 * @tshut_temp: the hardware-controlled shutdown temperature value 149 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) 150 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) 151 */ 152 struct rockchip_thermal_data { 153 const struct rockchip_tsadc_chip *chip; 154 struct platform_device *pdev; 155 struct reset_control *reset; 156 157 struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS]; 158 159 struct clk *clk; 160 struct clk *pclk; 161 162 struct regmap *grf; 163 void __iomem *regs; 164 165 int tshut_temp; 166 enum tshut_mode tshut_mode; 167 enum tshut_polarity tshut_polarity; 168 }; 169 170 /** 171 * TSADC Sensor Register description: 172 * 173 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it. 174 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399) 175 * 176 */ 177 #define TSADCV2_USER_CON 0x00 178 #define TSADCV2_AUTO_CON 0x04 179 #define TSADCV2_INT_EN 0x08 180 #define TSADCV2_INT_PD 0x0c 181 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) 182 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) 183 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) 184 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 185 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 186 #define TSADCV2_AUTO_PERIOD 0x68 187 #define TSADCV2_AUTO_PERIOD_HT 0x6c 188 189 #define TSADCV2_AUTO_EN BIT(0) 190 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) 191 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) 192 193 #define TSADCV3_AUTO_Q_SEL_EN BIT(1) 194 195 #define TSADCV2_INT_SRC_EN(chn) BIT(chn) 196 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) 197 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) 198 199 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) 200 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) 201 202 #define TSADCV2_DATA_MASK 0xfff 203 #define TSADCV3_DATA_MASK 0x3ff 204 205 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 206 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 207 #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */ 208 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */ 209 #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */ 210 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */ 211 212 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ 213 214 #define GRF_SARADC_TESTBIT 0x0e644 215 #define GRF_TSADC_TESTBIT_L 0x0e648 216 #define GRF_TSADC_TESTBIT_H 0x0e64c 217 218 #define PX30_GRF_SOC_CON2 0x0408 219 220 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) 221 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) 222 #define GRF_TSADC_VCM_EN_L (0x10001 << 7) 223 #define GRF_TSADC_VCM_EN_H (0x10001 << 7) 224 225 #define GRF_CON_TSADC_CH_INV (0x10001 << 1) 226 227 /** 228 * struct tsadc_table - code to temperature conversion table 229 * @code: the value of adc channel 230 * @temp: the temperature 231 * Note: 232 * code to temperature mapping of the temperature sensor is a piece wise linear 233 * curve.Any temperature, code faling between to 2 give temperatures can be 234 * linearly interpolated. 235 * Code to Temperature mapping should be updated based on manufacturer results. 236 */ 237 struct tsadc_table { 238 u32 code; 239 int temp; 240 }; 241 242 static const struct tsadc_table rv1108_table[] = { 243 {0, -40000}, 244 {374, -40000}, 245 {382, -35000}, 246 {389, -30000}, 247 {397, -25000}, 248 {405, -20000}, 249 {413, -15000}, 250 {421, -10000}, 251 {429, -5000}, 252 {436, 0}, 253 {444, 5000}, 254 {452, 10000}, 255 {460, 15000}, 256 {468, 20000}, 257 {476, 25000}, 258 {483, 30000}, 259 {491, 35000}, 260 {499, 40000}, 261 {507, 45000}, 262 {515, 50000}, 263 {523, 55000}, 264 {531, 60000}, 265 {539, 65000}, 266 {547, 70000}, 267 {555, 75000}, 268 {562, 80000}, 269 {570, 85000}, 270 {578, 90000}, 271 {586, 95000}, 272 {594, 100000}, 273 {602, 105000}, 274 {610, 110000}, 275 {618, 115000}, 276 {626, 120000}, 277 {634, 125000}, 278 {TSADCV2_DATA_MASK, 125000}, 279 }; 280 281 static const struct tsadc_table rk3228_code_table[] = { 282 {0, -40000}, 283 {588, -40000}, 284 {593, -35000}, 285 {598, -30000}, 286 {603, -25000}, 287 {608, -20000}, 288 {613, -15000}, 289 {618, -10000}, 290 {623, -5000}, 291 {629, 0}, 292 {634, 5000}, 293 {639, 10000}, 294 {644, 15000}, 295 {649, 20000}, 296 {654, 25000}, 297 {660, 30000}, 298 {665, 35000}, 299 {670, 40000}, 300 {675, 45000}, 301 {681, 50000}, 302 {686, 55000}, 303 {691, 60000}, 304 {696, 65000}, 305 {702, 70000}, 306 {707, 75000}, 307 {712, 80000}, 308 {717, 85000}, 309 {723, 90000}, 310 {728, 95000}, 311 {733, 100000}, 312 {738, 105000}, 313 {744, 110000}, 314 {749, 115000}, 315 {754, 120000}, 316 {760, 125000}, 317 {TSADCV2_DATA_MASK, 125000}, 318 }; 319 320 static const struct tsadc_table rk3288_code_table[] = { 321 {TSADCV2_DATA_MASK, -40000}, 322 {3800, -40000}, 323 {3792, -35000}, 324 {3783, -30000}, 325 {3774, -25000}, 326 {3765, -20000}, 327 {3756, -15000}, 328 {3747, -10000}, 329 {3737, -5000}, 330 {3728, 0}, 331 {3718, 5000}, 332 {3708, 10000}, 333 {3698, 15000}, 334 {3688, 20000}, 335 {3678, 25000}, 336 {3667, 30000}, 337 {3656, 35000}, 338 {3645, 40000}, 339 {3634, 45000}, 340 {3623, 50000}, 341 {3611, 55000}, 342 {3600, 60000}, 343 {3588, 65000}, 344 {3575, 70000}, 345 {3563, 75000}, 346 {3550, 80000}, 347 {3537, 85000}, 348 {3524, 90000}, 349 {3510, 95000}, 350 {3496, 100000}, 351 {3482, 105000}, 352 {3467, 110000}, 353 {3452, 115000}, 354 {3437, 120000}, 355 {3421, 125000}, 356 {0, 125000}, 357 }; 358 359 static const struct tsadc_table rk3328_code_table[] = { 360 {0, -40000}, 361 {296, -40000}, 362 {304, -35000}, 363 {313, -30000}, 364 {331, -20000}, 365 {340, -15000}, 366 {349, -10000}, 367 {359, -5000}, 368 {368, 0}, 369 {378, 5000}, 370 {388, 10000}, 371 {398, 15000}, 372 {408, 20000}, 373 {418, 25000}, 374 {429, 30000}, 375 {440, 35000}, 376 {451, 40000}, 377 {462, 45000}, 378 {473, 50000}, 379 {485, 55000}, 380 {496, 60000}, 381 {508, 65000}, 382 {521, 70000}, 383 {533, 75000}, 384 {546, 80000}, 385 {559, 85000}, 386 {572, 90000}, 387 {586, 95000}, 388 {600, 100000}, 389 {614, 105000}, 390 {629, 110000}, 391 {644, 115000}, 392 {659, 120000}, 393 {675, 125000}, 394 {TSADCV2_DATA_MASK, 125000}, 395 }; 396 397 static const struct tsadc_table rk3368_code_table[] = { 398 {0, -40000}, 399 {106, -40000}, 400 {108, -35000}, 401 {110, -30000}, 402 {112, -25000}, 403 {114, -20000}, 404 {116, -15000}, 405 {118, -10000}, 406 {120, -5000}, 407 {122, 0}, 408 {124, 5000}, 409 {126, 10000}, 410 {128, 15000}, 411 {130, 20000}, 412 {132, 25000}, 413 {134, 30000}, 414 {136, 35000}, 415 {138, 40000}, 416 {140, 45000}, 417 {142, 50000}, 418 {144, 55000}, 419 {146, 60000}, 420 {148, 65000}, 421 {150, 70000}, 422 {152, 75000}, 423 {154, 80000}, 424 {156, 85000}, 425 {158, 90000}, 426 {160, 95000}, 427 {162, 100000}, 428 {163, 105000}, 429 {165, 110000}, 430 {167, 115000}, 431 {169, 120000}, 432 {171, 125000}, 433 {TSADCV3_DATA_MASK, 125000}, 434 }; 435 436 static const struct tsadc_table rk3399_code_table[] = { 437 {0, -40000}, 438 {402, -40000}, 439 {410, -35000}, 440 {419, -30000}, 441 {427, -25000}, 442 {436, -20000}, 443 {444, -15000}, 444 {453, -10000}, 445 {461, -5000}, 446 {470, 0}, 447 {478, 5000}, 448 {487, 10000}, 449 {496, 15000}, 450 {504, 20000}, 451 {513, 25000}, 452 {521, 30000}, 453 {530, 35000}, 454 {538, 40000}, 455 {547, 45000}, 456 {555, 50000}, 457 {564, 55000}, 458 {573, 60000}, 459 {581, 65000}, 460 {590, 70000}, 461 {599, 75000}, 462 {607, 80000}, 463 {616, 85000}, 464 {624, 90000}, 465 {633, 95000}, 466 {642, 100000}, 467 {650, 105000}, 468 {659, 110000}, 469 {668, 115000}, 470 {677, 120000}, 471 {685, 125000}, 472 {TSADCV3_DATA_MASK, 125000}, 473 }; 474 475 static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table, 476 int temp) 477 { 478 int high, low, mid; 479 unsigned long num; 480 unsigned int denom; 481 u32 error = table->data_mask; 482 483 low = 0; 484 high = (table->length - 1) - 1; /* ignore the last check for table */ 485 mid = (high + low) / 2; 486 487 /* Return mask code data when the temp is over table range */ 488 if (temp < table->id[low].temp || temp > table->id[high].temp) 489 goto exit; 490 491 while (low <= high) { 492 if (temp == table->id[mid].temp) 493 return table->id[mid].code; 494 else if (temp < table->id[mid].temp) 495 high = mid - 1; 496 else 497 low = mid + 1; 498 mid = (low + high) / 2; 499 } 500 501 /* 502 * The conversion code granularity provided by the table. Let's 503 * assume that the relationship between temperature and 504 * analog value between 2 table entries is linear and interpolate 505 * to produce less granular result. 506 */ 507 num = abs(table->id[mid + 1].code - table->id[mid].code); 508 num *= temp - table->id[mid].temp; 509 denom = table->id[mid + 1].temp - table->id[mid].temp; 510 511 switch (table->mode) { 512 case ADC_DECREMENT: 513 return table->id[mid].code - (num / denom); 514 case ADC_INCREMENT: 515 return table->id[mid].code + (num / denom); 516 default: 517 pr_err("%s: unknown table mode: %d\n", __func__, table->mode); 518 return error; 519 } 520 521 exit: 522 pr_err("%s: invalid temperature, temp=%d error=%d\n", 523 __func__, temp, error); 524 return error; 525 } 526 527 static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table, 528 u32 code, int *temp) 529 { 530 unsigned int low = 1; 531 unsigned int high = table->length - 1; 532 unsigned int mid = (low + high) / 2; 533 unsigned int num; 534 unsigned long denom; 535 536 WARN_ON(table->length < 2); 537 538 switch (table->mode) { 539 case ADC_DECREMENT: 540 code &= table->data_mask; 541 if (code <= table->id[high].code) 542 return -EAGAIN; /* Incorrect reading */ 543 544 while (low <= high) { 545 if (code >= table->id[mid].code && 546 code < table->id[mid - 1].code) 547 break; 548 else if (code < table->id[mid].code) 549 low = mid + 1; 550 else 551 high = mid - 1; 552 553 mid = (low + high) / 2; 554 } 555 break; 556 case ADC_INCREMENT: 557 code &= table->data_mask; 558 if (code < table->id[low].code) 559 return -EAGAIN; /* Incorrect reading */ 560 561 while (low <= high) { 562 if (code <= table->id[mid].code && 563 code > table->id[mid - 1].code) 564 break; 565 else if (code > table->id[mid].code) 566 low = mid + 1; 567 else 568 high = mid - 1; 569 570 mid = (low + high) / 2; 571 } 572 break; 573 default: 574 pr_err("%s: unknown table mode: %d\n", __func__, table->mode); 575 return -EINVAL; 576 } 577 578 /* 579 * The 5C granularity provided by the table is too much. Let's 580 * assume that the relationship between sensor readings and 581 * temperature between 2 table entries is linear and interpolate 582 * to produce less granular result. 583 */ 584 num = table->id[mid].temp - table->id[mid - 1].temp; 585 num *= abs(table->id[mid - 1].code - code); 586 denom = abs(table->id[mid - 1].code - table->id[mid].code); 587 *temp = table->id[mid - 1].temp + (num / denom); 588 589 return 0; 590 } 591 592 /** 593 * rk_tsadcv2_initialize - initialize TASDC Controller. 594 * @grf: the general register file will be used to do static set by software 595 * @regs: the base address of tsadc controller 596 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) 597 * 598 * (1) Set TSADC_V2_AUTO_PERIOD: 599 * Configure the interleave between every two accessing of 600 * TSADC in normal operation. 601 * 602 * (2) Set TSADCV2_AUTO_PERIOD_HT: 603 * Configure the interleave between every two accessing of 604 * TSADC after the temperature is higher than COM_SHUT or COM_INT. 605 * 606 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: 607 * If the temperature is higher than COMP_INT or COMP_SHUT for 608 * "debounce" times, TSADC controller will generate interrupt or TSHUT. 609 */ 610 static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs, 611 enum tshut_polarity tshut_polarity) 612 { 613 if (tshut_polarity == TSHUT_HIGH_ACTIVE) 614 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 615 regs + TSADCV2_AUTO_CON); 616 else 617 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 618 regs + TSADCV2_AUTO_CON); 619 620 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); 621 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 622 regs + TSADCV2_HIGHT_INT_DEBOUNCE); 623 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, 624 regs + TSADCV2_AUTO_PERIOD_HT); 625 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 626 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 627 } 628 629 /** 630 * rk_tsadcv3_initialize - initialize TASDC Controller. 631 * @grf: the general register file will be used to do static set by software 632 * @regs: the base address of tsadc controller 633 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) 634 * 635 * (1) The tsadc control power sequence. 636 * 637 * (2) Set TSADC_V2_AUTO_PERIOD: 638 * Configure the interleave between every two accessing of 639 * TSADC in normal operation. 640 * 641 * (2) Set TSADCV2_AUTO_PERIOD_HT: 642 * Configure the interleave between every two accessing of 643 * TSADC after the temperature is higher than COM_SHUT or COM_INT. 644 * 645 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: 646 * If the temperature is higher than COMP_INT or COMP_SHUT for 647 * "debounce" times, TSADC controller will generate interrupt or TSHUT. 648 */ 649 static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs, 650 enum tshut_polarity tshut_polarity) 651 { 652 /* The tsadc control power sequence */ 653 if (IS_ERR(grf)) { 654 /* Set interleave value to workround ic time sync issue */ 655 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs + 656 TSADCV2_USER_CON); 657 658 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, 659 regs + TSADCV2_AUTO_PERIOD); 660 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 661 regs + TSADCV2_HIGHT_INT_DEBOUNCE); 662 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, 663 regs + TSADCV2_AUTO_PERIOD_HT); 664 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 665 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 666 667 } else { 668 /* Enable the voltage common mode feature */ 669 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L); 670 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H); 671 672 usleep_range(15, 100); /* The spec note says at least 15 us */ 673 regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON); 674 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON); 675 usleep_range(90, 200); /* The spec note says at least 90 us */ 676 677 writel_relaxed(TSADCV3_AUTO_PERIOD_TIME, 678 regs + TSADCV2_AUTO_PERIOD); 679 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 680 regs + TSADCV2_HIGHT_INT_DEBOUNCE); 681 writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME, 682 regs + TSADCV2_AUTO_PERIOD_HT); 683 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 684 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 685 } 686 687 if (tshut_polarity == TSHUT_HIGH_ACTIVE) 688 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 689 regs + TSADCV2_AUTO_CON); 690 else 691 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 692 regs + TSADCV2_AUTO_CON); 693 } 694 695 static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs, 696 enum tshut_polarity tshut_polarity) 697 { 698 rk_tsadcv2_initialize(grf, regs, tshut_polarity); 699 regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV); 700 } 701 702 static void rk_tsadcv2_irq_ack(void __iomem *regs) 703 { 704 u32 val; 705 706 val = readl_relaxed(regs + TSADCV2_INT_PD); 707 writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); 708 } 709 710 static void rk_tsadcv3_irq_ack(void __iomem *regs) 711 { 712 u32 val; 713 714 val = readl_relaxed(regs + TSADCV2_INT_PD); 715 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); 716 } 717 718 static void rk_tsadcv2_control(void __iomem *regs, bool enable) 719 { 720 u32 val; 721 722 val = readl_relaxed(regs + TSADCV2_AUTO_CON); 723 if (enable) 724 val |= TSADCV2_AUTO_EN; 725 else 726 val &= ~TSADCV2_AUTO_EN; 727 728 writel_relaxed(val, regs + TSADCV2_AUTO_CON); 729 } 730 731 /** 732 * rk_tsadcv3_control - the tsadc controller is enabled or disabled. 733 * @regs: the base address of tsadc controller 734 * @enable: boolean flag to enable the controller 735 * 736 * NOTE: TSADC controller works at auto mode, and some SoCs need set the 737 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output 738 * adc value if setting this bit to enable. 739 */ 740 static void rk_tsadcv3_control(void __iomem *regs, bool enable) 741 { 742 u32 val; 743 744 val = readl_relaxed(regs + TSADCV2_AUTO_CON); 745 if (enable) 746 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; 747 else 748 val &= ~TSADCV2_AUTO_EN; 749 750 writel_relaxed(val, regs + TSADCV2_AUTO_CON); 751 } 752 753 static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table, 754 int chn, void __iomem *regs, int *temp) 755 { 756 u32 val; 757 758 val = readl_relaxed(regs + TSADCV2_DATA(chn)); 759 760 return rk_tsadcv2_code_to_temp(table, val, temp); 761 } 762 763 static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table, 764 int chn, void __iomem *regs, int temp) 765 { 766 u32 alarm_value; 767 u32 int_en, int_clr; 768 769 /* 770 * In some cases, some sensors didn't need the trip points, the 771 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm 772 * in the end, ignore this case and disable the high temperature 773 * interrupt. 774 */ 775 if (temp == INT_MAX) { 776 int_clr = readl_relaxed(regs + TSADCV2_INT_EN); 777 int_clr &= ~TSADCV2_INT_SRC_EN(chn); 778 writel_relaxed(int_clr, regs + TSADCV2_INT_EN); 779 return 0; 780 } 781 782 /* Make sure the value is valid */ 783 alarm_value = rk_tsadcv2_temp_to_code(table, temp); 784 if (alarm_value == table->data_mask) 785 return -ERANGE; 786 787 writel_relaxed(alarm_value & table->data_mask, 788 regs + TSADCV2_COMP_INT(chn)); 789 790 int_en = readl_relaxed(regs + TSADCV2_INT_EN); 791 int_en |= TSADCV2_INT_SRC_EN(chn); 792 writel_relaxed(int_en, regs + TSADCV2_INT_EN); 793 794 return 0; 795 } 796 797 static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table, 798 int chn, void __iomem *regs, int temp) 799 { 800 u32 tshut_value, val; 801 802 /* Make sure the value is valid */ 803 tshut_value = rk_tsadcv2_temp_to_code(table, temp); 804 if (tshut_value == table->data_mask) 805 return -ERANGE; 806 807 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn)); 808 809 /* TSHUT will be valid */ 810 val = readl_relaxed(regs + TSADCV2_AUTO_CON); 811 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON); 812 813 return 0; 814 } 815 816 static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, 817 enum tshut_mode mode) 818 { 819 u32 val; 820 821 val = readl_relaxed(regs + TSADCV2_INT_EN); 822 if (mode == TSHUT_MODE_GPIO) { 823 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); 824 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); 825 } else { 826 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); 827 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); 828 } 829 830 writel_relaxed(val, regs + TSADCV2_INT_EN); 831 } 832 833 static const struct rockchip_tsadc_chip px30_tsadc_data = { 834 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 835 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 836 .chn_num = 2, /* 2 channels for tsadc */ 837 838 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 839 .tshut_temp = 95000, 840 841 .initialize = rk_tsadcv4_initialize, 842 .irq_ack = rk_tsadcv3_irq_ack, 843 .control = rk_tsadcv3_control, 844 .get_temp = rk_tsadcv2_get_temp, 845 .set_alarm_temp = rk_tsadcv2_alarm_temp, 846 .set_tshut_temp = rk_tsadcv2_tshut_temp, 847 .set_tshut_mode = rk_tsadcv2_tshut_mode, 848 849 .table = { 850 .id = rk3328_code_table, 851 .length = ARRAY_SIZE(rk3328_code_table), 852 .data_mask = TSADCV2_DATA_MASK, 853 .mode = ADC_INCREMENT, 854 }, 855 }; 856 857 static const struct rockchip_tsadc_chip rv1108_tsadc_data = { 858 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 859 .chn_num = 1, /* one channel for tsadc */ 860 861 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 862 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 863 .tshut_temp = 95000, 864 865 .initialize = rk_tsadcv2_initialize, 866 .irq_ack = rk_tsadcv3_irq_ack, 867 .control = rk_tsadcv3_control, 868 .get_temp = rk_tsadcv2_get_temp, 869 .set_alarm_temp = rk_tsadcv2_alarm_temp, 870 .set_tshut_temp = rk_tsadcv2_tshut_temp, 871 .set_tshut_mode = rk_tsadcv2_tshut_mode, 872 873 .table = { 874 .id = rv1108_table, 875 .length = ARRAY_SIZE(rv1108_table), 876 .data_mask = TSADCV2_DATA_MASK, 877 .mode = ADC_INCREMENT, 878 }, 879 }; 880 881 static const struct rockchip_tsadc_chip rk3228_tsadc_data = { 882 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 883 .chn_num = 1, /* one channel for tsadc */ 884 885 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 886 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 887 .tshut_temp = 95000, 888 889 .initialize = rk_tsadcv2_initialize, 890 .irq_ack = rk_tsadcv3_irq_ack, 891 .control = rk_tsadcv3_control, 892 .get_temp = rk_tsadcv2_get_temp, 893 .set_alarm_temp = rk_tsadcv2_alarm_temp, 894 .set_tshut_temp = rk_tsadcv2_tshut_temp, 895 .set_tshut_mode = rk_tsadcv2_tshut_mode, 896 897 .table = { 898 .id = rk3228_code_table, 899 .length = ARRAY_SIZE(rk3228_code_table), 900 .data_mask = TSADCV3_DATA_MASK, 901 .mode = ADC_INCREMENT, 902 }, 903 }; 904 905 static const struct rockchip_tsadc_chip rk3288_tsadc_data = { 906 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ 907 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ 908 .chn_num = 2, /* two channels for tsadc */ 909 910 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 911 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 912 .tshut_temp = 95000, 913 914 .initialize = rk_tsadcv2_initialize, 915 .irq_ack = rk_tsadcv2_irq_ack, 916 .control = rk_tsadcv2_control, 917 .get_temp = rk_tsadcv2_get_temp, 918 .set_alarm_temp = rk_tsadcv2_alarm_temp, 919 .set_tshut_temp = rk_tsadcv2_tshut_temp, 920 .set_tshut_mode = rk_tsadcv2_tshut_mode, 921 922 .table = { 923 .id = rk3288_code_table, 924 .length = ARRAY_SIZE(rk3288_code_table), 925 .data_mask = TSADCV2_DATA_MASK, 926 .mode = ADC_DECREMENT, 927 }, 928 }; 929 930 static const struct rockchip_tsadc_chip rk3328_tsadc_data = { 931 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 932 .chn_num = 1, /* one channels for tsadc */ 933 934 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 935 .tshut_temp = 95000, 936 937 .initialize = rk_tsadcv2_initialize, 938 .irq_ack = rk_tsadcv3_irq_ack, 939 .control = rk_tsadcv3_control, 940 .get_temp = rk_tsadcv2_get_temp, 941 .set_alarm_temp = rk_tsadcv2_alarm_temp, 942 .set_tshut_temp = rk_tsadcv2_tshut_temp, 943 .set_tshut_mode = rk_tsadcv2_tshut_mode, 944 945 .table = { 946 .id = rk3328_code_table, 947 .length = ARRAY_SIZE(rk3328_code_table), 948 .data_mask = TSADCV2_DATA_MASK, 949 .mode = ADC_INCREMENT, 950 }, 951 }; 952 953 static const struct rockchip_tsadc_chip rk3366_tsadc_data = { 954 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 955 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 956 .chn_num = 2, /* two channels for tsadc */ 957 958 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 959 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 960 .tshut_temp = 95000, 961 962 .initialize = rk_tsadcv3_initialize, 963 .irq_ack = rk_tsadcv3_irq_ack, 964 .control = rk_tsadcv3_control, 965 .get_temp = rk_tsadcv2_get_temp, 966 .set_alarm_temp = rk_tsadcv2_alarm_temp, 967 .set_tshut_temp = rk_tsadcv2_tshut_temp, 968 .set_tshut_mode = rk_tsadcv2_tshut_mode, 969 970 .table = { 971 .id = rk3228_code_table, 972 .length = ARRAY_SIZE(rk3228_code_table), 973 .data_mask = TSADCV3_DATA_MASK, 974 .mode = ADC_INCREMENT, 975 }, 976 }; 977 978 static const struct rockchip_tsadc_chip rk3368_tsadc_data = { 979 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 980 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 981 .chn_num = 2, /* two channels for tsadc */ 982 983 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 984 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 985 .tshut_temp = 95000, 986 987 .initialize = rk_tsadcv2_initialize, 988 .irq_ack = rk_tsadcv2_irq_ack, 989 .control = rk_tsadcv2_control, 990 .get_temp = rk_tsadcv2_get_temp, 991 .set_alarm_temp = rk_tsadcv2_alarm_temp, 992 .set_tshut_temp = rk_tsadcv2_tshut_temp, 993 .set_tshut_mode = rk_tsadcv2_tshut_mode, 994 995 .table = { 996 .id = rk3368_code_table, 997 .length = ARRAY_SIZE(rk3368_code_table), 998 .data_mask = TSADCV3_DATA_MASK, 999 .mode = ADC_INCREMENT, 1000 }, 1001 }; 1002 1003 static const struct rockchip_tsadc_chip rk3399_tsadc_data = { 1004 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1005 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1006 .chn_num = 2, /* two channels for tsadc */ 1007 1008 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1009 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1010 .tshut_temp = 95000, 1011 1012 .initialize = rk_tsadcv3_initialize, 1013 .irq_ack = rk_tsadcv3_irq_ack, 1014 .control = rk_tsadcv3_control, 1015 .get_temp = rk_tsadcv2_get_temp, 1016 .set_alarm_temp = rk_tsadcv2_alarm_temp, 1017 .set_tshut_temp = rk_tsadcv2_tshut_temp, 1018 .set_tshut_mode = rk_tsadcv2_tshut_mode, 1019 1020 .table = { 1021 .id = rk3399_code_table, 1022 .length = ARRAY_SIZE(rk3399_code_table), 1023 .data_mask = TSADCV3_DATA_MASK, 1024 .mode = ADC_INCREMENT, 1025 }, 1026 }; 1027 1028 static const struct of_device_id of_rockchip_thermal_match[] = { 1029 { .compatible = "rockchip,px30-tsadc", 1030 .data = (void *)&px30_tsadc_data, 1031 }, 1032 { 1033 .compatible = "rockchip,rv1108-tsadc", 1034 .data = (void *)&rv1108_tsadc_data, 1035 }, 1036 { 1037 .compatible = "rockchip,rk3228-tsadc", 1038 .data = (void *)&rk3228_tsadc_data, 1039 }, 1040 { 1041 .compatible = "rockchip,rk3288-tsadc", 1042 .data = (void *)&rk3288_tsadc_data, 1043 }, 1044 { 1045 .compatible = "rockchip,rk3328-tsadc", 1046 .data = (void *)&rk3328_tsadc_data, 1047 }, 1048 { 1049 .compatible = "rockchip,rk3366-tsadc", 1050 .data = (void *)&rk3366_tsadc_data, 1051 }, 1052 { 1053 .compatible = "rockchip,rk3368-tsadc", 1054 .data = (void *)&rk3368_tsadc_data, 1055 }, 1056 { 1057 .compatible = "rockchip,rk3399-tsadc", 1058 .data = (void *)&rk3399_tsadc_data, 1059 }, 1060 { /* end */ }, 1061 }; 1062 MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match); 1063 1064 static void 1065 rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on) 1066 { 1067 struct thermal_zone_device *tzd = sensor->tzd; 1068 1069 tzd->ops->set_mode(tzd, 1070 on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED); 1071 } 1072 1073 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev) 1074 { 1075 struct rockchip_thermal_data *thermal = dev; 1076 int i; 1077 1078 dev_dbg(&thermal->pdev->dev, "thermal alarm\n"); 1079 1080 thermal->chip->irq_ack(thermal->regs); 1081 1082 for (i = 0; i < thermal->chip->chn_num; i++) 1083 thermal_zone_device_update(thermal->sensors[i].tzd, 1084 THERMAL_EVENT_UNSPECIFIED); 1085 1086 return IRQ_HANDLED; 1087 } 1088 1089 static int rockchip_thermal_set_trips(void *_sensor, int low, int high) 1090 { 1091 struct rockchip_thermal_sensor *sensor = _sensor; 1092 struct rockchip_thermal_data *thermal = sensor->thermal; 1093 const struct rockchip_tsadc_chip *tsadc = thermal->chip; 1094 1095 dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n", 1096 __func__, sensor->id, low, high); 1097 1098 return tsadc->set_alarm_temp(&tsadc->table, 1099 sensor->id, thermal->regs, high); 1100 } 1101 1102 static int rockchip_thermal_get_temp(void *_sensor, int *out_temp) 1103 { 1104 struct rockchip_thermal_sensor *sensor = _sensor; 1105 struct rockchip_thermal_data *thermal = sensor->thermal; 1106 const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip; 1107 int retval; 1108 1109 retval = tsadc->get_temp(&tsadc->table, 1110 sensor->id, thermal->regs, out_temp); 1111 dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n", 1112 sensor->id, *out_temp, retval); 1113 1114 return retval; 1115 } 1116 1117 static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = { 1118 .get_temp = rockchip_thermal_get_temp, 1119 .set_trips = rockchip_thermal_set_trips, 1120 }; 1121 1122 static int rockchip_configure_from_dt(struct device *dev, 1123 struct device_node *np, 1124 struct rockchip_thermal_data *thermal) 1125 { 1126 u32 shut_temp, tshut_mode, tshut_polarity; 1127 1128 if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) { 1129 dev_warn(dev, 1130 "Missing tshut temp property, using default %d\n", 1131 thermal->chip->tshut_temp); 1132 thermal->tshut_temp = thermal->chip->tshut_temp; 1133 } else { 1134 if (shut_temp > INT_MAX) { 1135 dev_err(dev, "Invalid tshut temperature specified: %d\n", 1136 shut_temp); 1137 return -ERANGE; 1138 } 1139 thermal->tshut_temp = shut_temp; 1140 } 1141 1142 if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) { 1143 dev_warn(dev, 1144 "Missing tshut mode property, using default (%s)\n", 1145 thermal->chip->tshut_mode == TSHUT_MODE_GPIO ? 1146 "gpio" : "cru"); 1147 thermal->tshut_mode = thermal->chip->tshut_mode; 1148 } else { 1149 thermal->tshut_mode = tshut_mode; 1150 } 1151 1152 if (thermal->tshut_mode > 1) { 1153 dev_err(dev, "Invalid tshut mode specified: %d\n", 1154 thermal->tshut_mode); 1155 return -EINVAL; 1156 } 1157 1158 if (of_property_read_u32(np, "rockchip,hw-tshut-polarity", 1159 &tshut_polarity)) { 1160 dev_warn(dev, 1161 "Missing tshut-polarity property, using default (%s)\n", 1162 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ? 1163 "low" : "high"); 1164 thermal->tshut_polarity = thermal->chip->tshut_polarity; 1165 } else { 1166 thermal->tshut_polarity = tshut_polarity; 1167 } 1168 1169 if (thermal->tshut_polarity > 1) { 1170 dev_err(dev, "Invalid tshut-polarity specified: %d\n", 1171 thermal->tshut_polarity); 1172 return -EINVAL; 1173 } 1174 1175 /* The tsadc wont to handle the error in here since some SoCs didn't 1176 * need this property. 1177 */ 1178 thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1179 if (IS_ERR(thermal->grf)) 1180 dev_warn(dev, "Missing rockchip,grf property\n"); 1181 1182 return 0; 1183 } 1184 1185 static int 1186 rockchip_thermal_register_sensor(struct platform_device *pdev, 1187 struct rockchip_thermal_data *thermal, 1188 struct rockchip_thermal_sensor *sensor, 1189 int id) 1190 { 1191 const struct rockchip_tsadc_chip *tsadc = thermal->chip; 1192 int error; 1193 1194 tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); 1195 1196 error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, 1197 thermal->tshut_temp); 1198 if (error) 1199 dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n", 1200 __func__, thermal->tshut_temp, error); 1201 1202 sensor->thermal = thermal; 1203 sensor->id = id; 1204 sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id, 1205 sensor, &rockchip_of_thermal_ops); 1206 if (IS_ERR(sensor->tzd)) { 1207 error = PTR_ERR(sensor->tzd); 1208 dev_err(&pdev->dev, "failed to register sensor %d: %d\n", 1209 id, error); 1210 return error; 1211 } 1212 1213 return 0; 1214 } 1215 1216 /** 1217 * Reset TSADC Controller, reset all tsadc registers. 1218 * @reset: the reset controller of tsadc 1219 */ 1220 static void rockchip_thermal_reset_controller(struct reset_control *reset) 1221 { 1222 reset_control_assert(reset); 1223 usleep_range(10, 20); 1224 reset_control_deassert(reset); 1225 } 1226 1227 static int rockchip_thermal_probe(struct platform_device *pdev) 1228 { 1229 struct device_node *np = pdev->dev.of_node; 1230 struct rockchip_thermal_data *thermal; 1231 const struct of_device_id *match; 1232 struct resource *res; 1233 int irq; 1234 int i; 1235 int error; 1236 1237 match = of_match_node(of_rockchip_thermal_match, np); 1238 if (!match) 1239 return -ENXIO; 1240 1241 irq = platform_get_irq(pdev, 0); 1242 if (irq < 0) { 1243 dev_err(&pdev->dev, "no irq resource?\n"); 1244 return -EINVAL; 1245 } 1246 1247 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data), 1248 GFP_KERNEL); 1249 if (!thermal) 1250 return -ENOMEM; 1251 1252 thermal->pdev = pdev; 1253 1254 thermal->chip = (const struct rockchip_tsadc_chip *)match->data; 1255 if (!thermal->chip) 1256 return -EINVAL; 1257 1258 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1259 thermal->regs = devm_ioremap_resource(&pdev->dev, res); 1260 if (IS_ERR(thermal->regs)) 1261 return PTR_ERR(thermal->regs); 1262 1263 thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb"); 1264 if (IS_ERR(thermal->reset)) { 1265 error = PTR_ERR(thermal->reset); 1266 dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); 1267 return error; 1268 } 1269 1270 thermal->clk = devm_clk_get(&pdev->dev, "tsadc"); 1271 if (IS_ERR(thermal->clk)) { 1272 error = PTR_ERR(thermal->clk); 1273 dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); 1274 return error; 1275 } 1276 1277 thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); 1278 if (IS_ERR(thermal->pclk)) { 1279 error = PTR_ERR(thermal->pclk); 1280 dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", 1281 error); 1282 return error; 1283 } 1284 1285 error = clk_prepare_enable(thermal->clk); 1286 if (error) { 1287 dev_err(&pdev->dev, "failed to enable converter clock: %d\n", 1288 error); 1289 return error; 1290 } 1291 1292 error = clk_prepare_enable(thermal->pclk); 1293 if (error) { 1294 dev_err(&pdev->dev, "failed to enable pclk: %d\n", error); 1295 goto err_disable_clk; 1296 } 1297 1298 rockchip_thermal_reset_controller(thermal->reset); 1299 1300 error = rockchip_configure_from_dt(&pdev->dev, np, thermal); 1301 if (error) { 1302 dev_err(&pdev->dev, "failed to parse device tree data: %d\n", 1303 error); 1304 goto err_disable_pclk; 1305 } 1306 1307 thermal->chip->initialize(thermal->grf, thermal->regs, 1308 thermal->tshut_polarity); 1309 1310 for (i = 0; i < thermal->chip->chn_num; i++) { 1311 error = rockchip_thermal_register_sensor(pdev, thermal, 1312 &thermal->sensors[i], 1313 thermal->chip->chn_id[i]); 1314 if (error) { 1315 dev_err(&pdev->dev, 1316 "failed to register sensor[%d] : error = %d\n", 1317 i, error); 1318 goto err_disable_pclk; 1319 } 1320 } 1321 1322 error = devm_request_threaded_irq(&pdev->dev, irq, NULL, 1323 &rockchip_thermal_alarm_irq_thread, 1324 IRQF_ONESHOT, 1325 "rockchip_thermal", thermal); 1326 if (error) { 1327 dev_err(&pdev->dev, 1328 "failed to request tsadc irq: %d\n", error); 1329 goto err_disable_pclk; 1330 } 1331 1332 thermal->chip->control(thermal->regs, true); 1333 1334 for (i = 0; i < thermal->chip->chn_num; i++) 1335 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); 1336 1337 platform_set_drvdata(pdev, thermal); 1338 1339 return 0; 1340 1341 err_disable_pclk: 1342 clk_disable_unprepare(thermal->pclk); 1343 err_disable_clk: 1344 clk_disable_unprepare(thermal->clk); 1345 1346 return error; 1347 } 1348 1349 static int rockchip_thermal_remove(struct platform_device *pdev) 1350 { 1351 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); 1352 int i; 1353 1354 for (i = 0; i < thermal->chip->chn_num; i++) { 1355 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i]; 1356 1357 rockchip_thermal_toggle_sensor(sensor, false); 1358 } 1359 1360 thermal->chip->control(thermal->regs, false); 1361 1362 clk_disable_unprepare(thermal->pclk); 1363 clk_disable_unprepare(thermal->clk); 1364 1365 return 0; 1366 } 1367 1368 static int __maybe_unused rockchip_thermal_suspend(struct device *dev) 1369 { 1370 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); 1371 int i; 1372 1373 for (i = 0; i < thermal->chip->chn_num; i++) 1374 rockchip_thermal_toggle_sensor(&thermal->sensors[i], false); 1375 1376 thermal->chip->control(thermal->regs, false); 1377 1378 clk_disable(thermal->pclk); 1379 clk_disable(thermal->clk); 1380 1381 pinctrl_pm_select_sleep_state(dev); 1382 1383 return 0; 1384 } 1385 1386 static int __maybe_unused rockchip_thermal_resume(struct device *dev) 1387 { 1388 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); 1389 int i; 1390 int error; 1391 1392 error = clk_enable(thermal->clk); 1393 if (error) 1394 return error; 1395 1396 error = clk_enable(thermal->pclk); 1397 if (error) { 1398 clk_disable(thermal->clk); 1399 return error; 1400 } 1401 1402 rockchip_thermal_reset_controller(thermal->reset); 1403 1404 thermal->chip->initialize(thermal->grf, thermal->regs, 1405 thermal->tshut_polarity); 1406 1407 for (i = 0; i < thermal->chip->chn_num; i++) { 1408 int id = thermal->sensors[i].id; 1409 1410 thermal->chip->set_tshut_mode(id, thermal->regs, 1411 thermal->tshut_mode); 1412 1413 error = thermal->chip->set_tshut_temp(&thermal->chip->table, 1414 id, thermal->regs, 1415 thermal->tshut_temp); 1416 if (error) 1417 dev_err(dev, "%s: invalid tshut=%d, error=%d\n", 1418 __func__, thermal->tshut_temp, error); 1419 } 1420 1421 thermal->chip->control(thermal->regs, true); 1422 1423 for (i = 0; i < thermal->chip->chn_num; i++) 1424 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); 1425 1426 pinctrl_pm_select_default_state(dev); 1427 1428 return 0; 1429 } 1430 1431 static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops, 1432 rockchip_thermal_suspend, rockchip_thermal_resume); 1433 1434 static struct platform_driver rockchip_thermal_driver = { 1435 .driver = { 1436 .name = "rockchip-thermal", 1437 .pm = &rockchip_thermal_pm_ops, 1438 .of_match_table = of_rockchip_thermal_match, 1439 }, 1440 .probe = rockchip_thermal_probe, 1441 .remove = rockchip_thermal_remove, 1442 }; 1443 1444 module_platform_driver(rockchip_thermal_driver); 1445 1446 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver"); 1447 MODULE_AUTHOR("Rockchip, Inc."); 1448 MODULE_LICENSE("GPL v2"); 1449 MODULE_ALIAS("platform:rockchip-thermal"); 1450