1 /* 2 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd 3 * Caesar Wang <wxt@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 */ 14 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/of.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/platform_device.h> 24 #include <linux/regmap.h> 25 #include <linux/reset.h> 26 #include <linux/thermal.h> 27 #include <linux/mfd/syscon.h> 28 #include <linux/pinctrl/consumer.h> 29 30 /** 31 * If the temperature over a period of time High, 32 * the resulting TSHUT gave CRU module,let it reset the entire chip, 33 * or via GPIO give PMIC. 34 */ 35 enum tshut_mode { 36 TSHUT_MODE_CRU = 0, 37 TSHUT_MODE_GPIO, 38 }; 39 40 /** 41 * The system Temperature Sensors tshut(tshut) polarity 42 * the bit 8 is tshut polarity. 43 * 0: low active, 1: high active 44 */ 45 enum tshut_polarity { 46 TSHUT_LOW_ACTIVE = 0, 47 TSHUT_HIGH_ACTIVE, 48 }; 49 50 /** 51 * The system has two Temperature Sensors. 52 * sensor0 is for CPU, and sensor1 is for GPU. 53 */ 54 enum sensor_id { 55 SENSOR_CPU = 0, 56 SENSOR_GPU, 57 }; 58 59 /** 60 * The conversion table has the adc value and temperature. 61 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) 62 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) 63 */ 64 enum adc_sort_mode { 65 ADC_DECREMENT = 0, 66 ADC_INCREMENT, 67 }; 68 69 /** 70 * The max sensors is two in rockchip SoCs. 71 * Two sensors: CPU and GPU sensor. 72 */ 73 #define SOC_MAX_SENSORS 2 74 75 /** 76 * struct chip_tsadc_table - hold information about chip-specific differences 77 * @id: conversion table 78 * @length: size of conversion table 79 * @data_mask: mask to apply on data inputs 80 * @mode: sort mode of this adc variant (incrementing or decrementing) 81 */ 82 struct chip_tsadc_table { 83 const struct tsadc_table *id; 84 unsigned int length; 85 u32 data_mask; 86 enum adc_sort_mode mode; 87 }; 88 89 /** 90 * struct rockchip_tsadc_chip - hold the private data of tsadc chip 91 * @chn_id[SOC_MAX_SENSORS]: the sensor id of chip correspond to the channel 92 * @chn_num: the channel number of tsadc chip 93 * @tshut_temp: the hardware-controlled shutdown temperature value 94 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) 95 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) 96 * @initialize: SoC special initialize tsadc controller method 97 * @irq_ack: clear the interrupt 98 * @get_temp: get the temperature 99 * @set_alarm_temp: set the high temperature interrupt 100 * @set_tshut_temp: set the hardware-controlled shutdown temperature 101 * @set_tshut_mode: set the hardware-controlled shutdown mode 102 * @table: the chip-specific conversion table 103 */ 104 struct rockchip_tsadc_chip { 105 /* The sensor id of chip correspond to the ADC channel */ 106 int chn_id[SOC_MAX_SENSORS]; 107 int chn_num; 108 109 /* The hardware-controlled tshut property */ 110 int tshut_temp; 111 enum tshut_mode tshut_mode; 112 enum tshut_polarity tshut_polarity; 113 114 /* Chip-wide methods */ 115 void (*initialize)(struct regmap *grf, 116 void __iomem *reg, enum tshut_polarity p); 117 void (*irq_ack)(void __iomem *reg); 118 void (*control)(void __iomem *reg, bool on); 119 120 /* Per-sensor methods */ 121 int (*get_temp)(const struct chip_tsadc_table *table, 122 int chn, void __iomem *reg, int *temp); 123 int (*set_alarm_temp)(const struct chip_tsadc_table *table, 124 int chn, void __iomem *reg, int temp); 125 int (*set_tshut_temp)(const struct chip_tsadc_table *table, 126 int chn, void __iomem *reg, int temp); 127 void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); 128 129 /* Per-table methods */ 130 struct chip_tsadc_table table; 131 }; 132 133 /** 134 * struct rockchip_thermal_sensor - hold the information of thermal sensor 135 * @thermal: pointer to the platform/configuration data 136 * @tzd: pointer to a thermal zone 137 * @id: identifier of the thermal sensor 138 */ 139 struct rockchip_thermal_sensor { 140 struct rockchip_thermal_data *thermal; 141 struct thermal_zone_device *tzd; 142 int id; 143 }; 144 145 /** 146 * struct rockchip_thermal_data - hold the private data of thermal driver 147 * @chip: pointer to the platform/configuration data 148 * @pdev: platform device of thermal 149 * @reset: the reset controller of tsadc 150 * @sensors[SOC_MAX_SENSORS]: the thermal sensor 151 * @clk: the controller clock is divided by the exteral 24MHz 152 * @pclk: the advanced peripherals bus clock 153 * @grf: the general register file will be used to do static set by software 154 * @regs: the base address of tsadc controller 155 * @tshut_temp: the hardware-controlled shutdown temperature value 156 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) 157 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) 158 */ 159 struct rockchip_thermal_data { 160 const struct rockchip_tsadc_chip *chip; 161 struct platform_device *pdev; 162 struct reset_control *reset; 163 164 struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS]; 165 166 struct clk *clk; 167 struct clk *pclk; 168 169 struct regmap *grf; 170 void __iomem *regs; 171 172 int tshut_temp; 173 enum tshut_mode tshut_mode; 174 enum tshut_polarity tshut_polarity; 175 }; 176 177 /** 178 * TSADC Sensor Register description: 179 * 180 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it. 181 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399) 182 * 183 */ 184 #define TSADCV2_USER_CON 0x00 185 #define TSADCV2_AUTO_CON 0x04 186 #define TSADCV2_INT_EN 0x08 187 #define TSADCV2_INT_PD 0x0c 188 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) 189 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) 190 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) 191 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 192 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 193 #define TSADCV2_AUTO_PERIOD 0x68 194 #define TSADCV2_AUTO_PERIOD_HT 0x6c 195 196 #define TSADCV2_AUTO_EN BIT(0) 197 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) 198 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) 199 200 #define TSADCV3_AUTO_Q_SEL_EN BIT(1) 201 202 #define TSADCV2_INT_SRC_EN(chn) BIT(chn) 203 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) 204 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) 205 206 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) 207 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) 208 209 #define TSADCV2_DATA_MASK 0xfff 210 #define TSADCV3_DATA_MASK 0x3ff 211 212 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 213 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 214 #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */ 215 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */ 216 #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */ 217 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */ 218 219 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ 220 221 #define GRF_SARADC_TESTBIT 0x0e644 222 #define GRF_TSADC_TESTBIT_L 0x0e648 223 #define GRF_TSADC_TESTBIT_H 0x0e64c 224 225 #define PX30_GRF_SOC_CON2 0x0408 226 227 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) 228 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) 229 #define GRF_TSADC_VCM_EN_L (0x10001 << 7) 230 #define GRF_TSADC_VCM_EN_H (0x10001 << 7) 231 232 #define GRF_CON_TSADC_CH_INV (0x10001 << 1) 233 234 /** 235 * struct tsadc_table - code to temperature conversion table 236 * @code: the value of adc channel 237 * @temp: the temperature 238 * Note: 239 * code to temperature mapping of the temperature sensor is a piece wise linear 240 * curve.Any temperature, code faling between to 2 give temperatures can be 241 * linearly interpolated. 242 * Code to Temperature mapping should be updated based on manufacturer results. 243 */ 244 struct tsadc_table { 245 u32 code; 246 int temp; 247 }; 248 249 static const struct tsadc_table rv1108_table[] = { 250 {0, -40000}, 251 {374, -40000}, 252 {382, -35000}, 253 {389, -30000}, 254 {397, -25000}, 255 {405, -20000}, 256 {413, -15000}, 257 {421, -10000}, 258 {429, -5000}, 259 {436, 0}, 260 {444, 5000}, 261 {452, 10000}, 262 {460, 15000}, 263 {468, 20000}, 264 {476, 25000}, 265 {483, 30000}, 266 {491, 35000}, 267 {499, 40000}, 268 {507, 45000}, 269 {515, 50000}, 270 {523, 55000}, 271 {531, 60000}, 272 {539, 65000}, 273 {547, 70000}, 274 {555, 75000}, 275 {562, 80000}, 276 {570, 85000}, 277 {578, 90000}, 278 {586, 95000}, 279 {594, 100000}, 280 {602, 105000}, 281 {610, 110000}, 282 {618, 115000}, 283 {626, 120000}, 284 {634, 125000}, 285 {TSADCV2_DATA_MASK, 125000}, 286 }; 287 288 static const struct tsadc_table rk3228_code_table[] = { 289 {0, -40000}, 290 {588, -40000}, 291 {593, -35000}, 292 {598, -30000}, 293 {603, -25000}, 294 {608, -20000}, 295 {613, -15000}, 296 {618, -10000}, 297 {623, -5000}, 298 {629, 0}, 299 {634, 5000}, 300 {639, 10000}, 301 {644, 15000}, 302 {649, 20000}, 303 {654, 25000}, 304 {660, 30000}, 305 {665, 35000}, 306 {670, 40000}, 307 {675, 45000}, 308 {681, 50000}, 309 {686, 55000}, 310 {691, 60000}, 311 {696, 65000}, 312 {702, 70000}, 313 {707, 75000}, 314 {712, 80000}, 315 {717, 85000}, 316 {723, 90000}, 317 {728, 95000}, 318 {733, 100000}, 319 {738, 105000}, 320 {744, 110000}, 321 {749, 115000}, 322 {754, 120000}, 323 {760, 125000}, 324 {TSADCV2_DATA_MASK, 125000}, 325 }; 326 327 static const struct tsadc_table rk3288_code_table[] = { 328 {TSADCV2_DATA_MASK, -40000}, 329 {3800, -40000}, 330 {3792, -35000}, 331 {3783, -30000}, 332 {3774, -25000}, 333 {3765, -20000}, 334 {3756, -15000}, 335 {3747, -10000}, 336 {3737, -5000}, 337 {3728, 0}, 338 {3718, 5000}, 339 {3708, 10000}, 340 {3698, 15000}, 341 {3688, 20000}, 342 {3678, 25000}, 343 {3667, 30000}, 344 {3656, 35000}, 345 {3645, 40000}, 346 {3634, 45000}, 347 {3623, 50000}, 348 {3611, 55000}, 349 {3600, 60000}, 350 {3588, 65000}, 351 {3575, 70000}, 352 {3563, 75000}, 353 {3550, 80000}, 354 {3537, 85000}, 355 {3524, 90000}, 356 {3510, 95000}, 357 {3496, 100000}, 358 {3482, 105000}, 359 {3467, 110000}, 360 {3452, 115000}, 361 {3437, 120000}, 362 {3421, 125000}, 363 {0, 125000}, 364 }; 365 366 static const struct tsadc_table rk3328_code_table[] = { 367 {0, -40000}, 368 {296, -40000}, 369 {304, -35000}, 370 {313, -30000}, 371 {331, -20000}, 372 {340, -15000}, 373 {349, -10000}, 374 {359, -5000}, 375 {368, 0}, 376 {378, 5000}, 377 {388, 10000}, 378 {398, 15000}, 379 {408, 20000}, 380 {418, 25000}, 381 {429, 30000}, 382 {440, 35000}, 383 {451, 40000}, 384 {462, 45000}, 385 {473, 50000}, 386 {485, 55000}, 387 {496, 60000}, 388 {508, 65000}, 389 {521, 70000}, 390 {533, 75000}, 391 {546, 80000}, 392 {559, 85000}, 393 {572, 90000}, 394 {586, 95000}, 395 {600, 100000}, 396 {614, 105000}, 397 {629, 110000}, 398 {644, 115000}, 399 {659, 120000}, 400 {675, 125000}, 401 {TSADCV2_DATA_MASK, 125000}, 402 }; 403 404 static const struct tsadc_table rk3368_code_table[] = { 405 {0, -40000}, 406 {106, -40000}, 407 {108, -35000}, 408 {110, -30000}, 409 {112, -25000}, 410 {114, -20000}, 411 {116, -15000}, 412 {118, -10000}, 413 {120, -5000}, 414 {122, 0}, 415 {124, 5000}, 416 {126, 10000}, 417 {128, 15000}, 418 {130, 20000}, 419 {132, 25000}, 420 {134, 30000}, 421 {136, 35000}, 422 {138, 40000}, 423 {140, 45000}, 424 {142, 50000}, 425 {144, 55000}, 426 {146, 60000}, 427 {148, 65000}, 428 {150, 70000}, 429 {152, 75000}, 430 {154, 80000}, 431 {156, 85000}, 432 {158, 90000}, 433 {160, 95000}, 434 {162, 100000}, 435 {163, 105000}, 436 {165, 110000}, 437 {167, 115000}, 438 {169, 120000}, 439 {171, 125000}, 440 {TSADCV3_DATA_MASK, 125000}, 441 }; 442 443 static const struct tsadc_table rk3399_code_table[] = { 444 {0, -40000}, 445 {402, -40000}, 446 {410, -35000}, 447 {419, -30000}, 448 {427, -25000}, 449 {436, -20000}, 450 {444, -15000}, 451 {453, -10000}, 452 {461, -5000}, 453 {470, 0}, 454 {478, 5000}, 455 {487, 10000}, 456 {496, 15000}, 457 {504, 20000}, 458 {513, 25000}, 459 {521, 30000}, 460 {530, 35000}, 461 {538, 40000}, 462 {547, 45000}, 463 {555, 50000}, 464 {564, 55000}, 465 {573, 60000}, 466 {581, 65000}, 467 {590, 70000}, 468 {599, 75000}, 469 {607, 80000}, 470 {616, 85000}, 471 {624, 90000}, 472 {633, 95000}, 473 {642, 100000}, 474 {650, 105000}, 475 {659, 110000}, 476 {668, 115000}, 477 {677, 120000}, 478 {685, 125000}, 479 {TSADCV3_DATA_MASK, 125000}, 480 }; 481 482 static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table, 483 int temp) 484 { 485 int high, low, mid; 486 unsigned long num; 487 unsigned int denom; 488 u32 error = table->data_mask; 489 490 low = 0; 491 high = (table->length - 1) - 1; /* ignore the last check for table */ 492 mid = (high + low) / 2; 493 494 /* Return mask code data when the temp is over table range */ 495 if (temp < table->id[low].temp || temp > table->id[high].temp) 496 goto exit; 497 498 while (low <= high) { 499 if (temp == table->id[mid].temp) 500 return table->id[mid].code; 501 else if (temp < table->id[mid].temp) 502 high = mid - 1; 503 else 504 low = mid + 1; 505 mid = (low + high) / 2; 506 } 507 508 /* 509 * The conversion code granularity provided by the table. Let's 510 * assume that the relationship between temperature and 511 * analog value between 2 table entries is linear and interpolate 512 * to produce less granular result. 513 */ 514 num = abs(table->id[mid + 1].code - table->id[mid].code); 515 num *= temp - table->id[mid].temp; 516 denom = table->id[mid + 1].temp - table->id[mid].temp; 517 518 switch (table->mode) { 519 case ADC_DECREMENT: 520 return table->id[mid].code - (num / denom); 521 case ADC_INCREMENT: 522 return table->id[mid].code + (num / denom); 523 default: 524 pr_err("%s: unknown table mode: %d\n", __func__, table->mode); 525 return error; 526 } 527 528 exit: 529 pr_err("%s: invalid temperature, temp=%d error=%d\n", 530 __func__, temp, error); 531 return error; 532 } 533 534 static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table, 535 u32 code, int *temp) 536 { 537 unsigned int low = 1; 538 unsigned int high = table->length - 1; 539 unsigned int mid = (low + high) / 2; 540 unsigned int num; 541 unsigned long denom; 542 543 WARN_ON(table->length < 2); 544 545 switch (table->mode) { 546 case ADC_DECREMENT: 547 code &= table->data_mask; 548 if (code <= table->id[high].code) 549 return -EAGAIN; /* Incorrect reading */ 550 551 while (low <= high) { 552 if (code >= table->id[mid].code && 553 code < table->id[mid - 1].code) 554 break; 555 else if (code < table->id[mid].code) 556 low = mid + 1; 557 else 558 high = mid - 1; 559 560 mid = (low + high) / 2; 561 } 562 break; 563 case ADC_INCREMENT: 564 code &= table->data_mask; 565 if (code < table->id[low].code) 566 return -EAGAIN; /* Incorrect reading */ 567 568 while (low <= high) { 569 if (code <= table->id[mid].code && 570 code > table->id[mid - 1].code) 571 break; 572 else if (code > table->id[mid].code) 573 low = mid + 1; 574 else 575 high = mid - 1; 576 577 mid = (low + high) / 2; 578 } 579 break; 580 default: 581 pr_err("%s: unknown table mode: %d\n", __func__, table->mode); 582 return -EINVAL; 583 } 584 585 /* 586 * The 5C granularity provided by the table is too much. Let's 587 * assume that the relationship between sensor readings and 588 * temperature between 2 table entries is linear and interpolate 589 * to produce less granular result. 590 */ 591 num = table->id[mid].temp - table->id[mid - 1].temp; 592 num *= abs(table->id[mid - 1].code - code); 593 denom = abs(table->id[mid - 1].code - table->id[mid].code); 594 *temp = table->id[mid - 1].temp + (num / denom); 595 596 return 0; 597 } 598 599 /** 600 * rk_tsadcv2_initialize - initialize TASDC Controller. 601 * 602 * (1) Set TSADC_V2_AUTO_PERIOD: 603 * Configure the interleave between every two accessing of 604 * TSADC in normal operation. 605 * 606 * (2) Set TSADCV2_AUTO_PERIOD_HT: 607 * Configure the interleave between every two accessing of 608 * TSADC after the temperature is higher than COM_SHUT or COM_INT. 609 * 610 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: 611 * If the temperature is higher than COMP_INT or COMP_SHUT for 612 * "debounce" times, TSADC controller will generate interrupt or TSHUT. 613 */ 614 static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs, 615 enum tshut_polarity tshut_polarity) 616 { 617 if (tshut_polarity == TSHUT_HIGH_ACTIVE) 618 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 619 regs + TSADCV2_AUTO_CON); 620 else 621 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 622 regs + TSADCV2_AUTO_CON); 623 624 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); 625 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 626 regs + TSADCV2_HIGHT_INT_DEBOUNCE); 627 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, 628 regs + TSADCV2_AUTO_PERIOD_HT); 629 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 630 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 631 } 632 633 /** 634 * rk_tsadcv3_initialize - initialize TASDC Controller. 635 * 636 * (1) The tsadc control power sequence. 637 * 638 * (2) Set TSADC_V2_AUTO_PERIOD: 639 * Configure the interleave between every two accessing of 640 * TSADC in normal operation. 641 * 642 * (2) Set TSADCV2_AUTO_PERIOD_HT: 643 * Configure the interleave between every two accessing of 644 * TSADC after the temperature is higher than COM_SHUT or COM_INT. 645 * 646 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: 647 * If the temperature is higher than COMP_INT or COMP_SHUT for 648 * "debounce" times, TSADC controller will generate interrupt or TSHUT. 649 */ 650 static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs, 651 enum tshut_polarity tshut_polarity) 652 { 653 /* The tsadc control power sequence */ 654 if (IS_ERR(grf)) { 655 /* Set interleave value to workround ic time sync issue */ 656 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs + 657 TSADCV2_USER_CON); 658 659 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, 660 regs + TSADCV2_AUTO_PERIOD); 661 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 662 regs + TSADCV2_HIGHT_INT_DEBOUNCE); 663 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, 664 regs + TSADCV2_AUTO_PERIOD_HT); 665 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 666 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 667 668 } else { 669 /* Enable the voltage common mode feature */ 670 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L); 671 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H); 672 673 usleep_range(15, 100); /* The spec note says at least 15 us */ 674 regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON); 675 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON); 676 usleep_range(90, 200); /* The spec note says at least 90 us */ 677 678 writel_relaxed(TSADCV3_AUTO_PERIOD_TIME, 679 regs + TSADCV2_AUTO_PERIOD); 680 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 681 regs + TSADCV2_HIGHT_INT_DEBOUNCE); 682 writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME, 683 regs + TSADCV2_AUTO_PERIOD_HT); 684 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 685 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 686 } 687 688 if (tshut_polarity == TSHUT_HIGH_ACTIVE) 689 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 690 regs + TSADCV2_AUTO_CON); 691 else 692 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 693 regs + TSADCV2_AUTO_CON); 694 } 695 696 static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs, 697 enum tshut_polarity tshut_polarity) 698 { 699 rk_tsadcv2_initialize(grf, regs, tshut_polarity); 700 regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV); 701 } 702 703 static void rk_tsadcv2_irq_ack(void __iomem *regs) 704 { 705 u32 val; 706 707 val = readl_relaxed(regs + TSADCV2_INT_PD); 708 writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); 709 } 710 711 static void rk_tsadcv3_irq_ack(void __iomem *regs) 712 { 713 u32 val; 714 715 val = readl_relaxed(regs + TSADCV2_INT_PD); 716 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); 717 } 718 719 static void rk_tsadcv2_control(void __iomem *regs, bool enable) 720 { 721 u32 val; 722 723 val = readl_relaxed(regs + TSADCV2_AUTO_CON); 724 if (enable) 725 val |= TSADCV2_AUTO_EN; 726 else 727 val &= ~TSADCV2_AUTO_EN; 728 729 writel_relaxed(val, regs + TSADCV2_AUTO_CON); 730 } 731 732 /** 733 * rk_tsadcv3_control - the tsadc controller is enabled or disabled. 734 * 735 * NOTE: TSADC controller works at auto mode, and some SoCs need set the 736 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output 737 * adc value if setting this bit to enable. 738 */ 739 static void rk_tsadcv3_control(void __iomem *regs, bool enable) 740 { 741 u32 val; 742 743 val = readl_relaxed(regs + TSADCV2_AUTO_CON); 744 if (enable) 745 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; 746 else 747 val &= ~TSADCV2_AUTO_EN; 748 749 writel_relaxed(val, regs + TSADCV2_AUTO_CON); 750 } 751 752 static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table, 753 int chn, void __iomem *regs, int *temp) 754 { 755 u32 val; 756 757 val = readl_relaxed(regs + TSADCV2_DATA(chn)); 758 759 return rk_tsadcv2_code_to_temp(table, val, temp); 760 } 761 762 static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table, 763 int chn, void __iomem *regs, int temp) 764 { 765 u32 alarm_value; 766 u32 int_en, int_clr; 767 768 /* 769 * In some cases, some sensors didn't need the trip points, the 770 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm 771 * in the end, ignore this case and disable the high temperature 772 * interrupt. 773 */ 774 if (temp == INT_MAX) { 775 int_clr = readl_relaxed(regs + TSADCV2_INT_EN); 776 int_clr &= ~TSADCV2_INT_SRC_EN(chn); 777 writel_relaxed(int_clr, regs + TSADCV2_INT_EN); 778 return 0; 779 } 780 781 /* Make sure the value is valid */ 782 alarm_value = rk_tsadcv2_temp_to_code(table, temp); 783 if (alarm_value == table->data_mask) 784 return -ERANGE; 785 786 writel_relaxed(alarm_value & table->data_mask, 787 regs + TSADCV2_COMP_INT(chn)); 788 789 int_en = readl_relaxed(regs + TSADCV2_INT_EN); 790 int_en |= TSADCV2_INT_SRC_EN(chn); 791 writel_relaxed(int_en, regs + TSADCV2_INT_EN); 792 793 return 0; 794 } 795 796 static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table, 797 int chn, void __iomem *regs, int temp) 798 { 799 u32 tshut_value, val; 800 801 /* Make sure the value is valid */ 802 tshut_value = rk_tsadcv2_temp_to_code(table, temp); 803 if (tshut_value == table->data_mask) 804 return -ERANGE; 805 806 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn)); 807 808 /* TSHUT will be valid */ 809 val = readl_relaxed(regs + TSADCV2_AUTO_CON); 810 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON); 811 812 return 0; 813 } 814 815 static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, 816 enum tshut_mode mode) 817 { 818 u32 val; 819 820 val = readl_relaxed(regs + TSADCV2_INT_EN); 821 if (mode == TSHUT_MODE_GPIO) { 822 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); 823 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); 824 } else { 825 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); 826 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); 827 } 828 829 writel_relaxed(val, regs + TSADCV2_INT_EN); 830 } 831 832 static const struct rockchip_tsadc_chip px30_tsadc_data = { 833 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 834 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 835 .chn_num = 2, /* 2 channels for tsadc */ 836 837 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 838 .tshut_temp = 95000, 839 840 .initialize = rk_tsadcv4_initialize, 841 .irq_ack = rk_tsadcv3_irq_ack, 842 .control = rk_tsadcv3_control, 843 .get_temp = rk_tsadcv2_get_temp, 844 .set_alarm_temp = rk_tsadcv2_alarm_temp, 845 .set_tshut_temp = rk_tsadcv2_tshut_temp, 846 .set_tshut_mode = rk_tsadcv2_tshut_mode, 847 848 .table = { 849 .id = rk3328_code_table, 850 .length = ARRAY_SIZE(rk3328_code_table), 851 .data_mask = TSADCV2_DATA_MASK, 852 .mode = ADC_INCREMENT, 853 }, 854 }; 855 856 static const struct rockchip_tsadc_chip rv1108_tsadc_data = { 857 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 858 .chn_num = 1, /* one channel for tsadc */ 859 860 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 861 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 862 .tshut_temp = 95000, 863 864 .initialize = rk_tsadcv2_initialize, 865 .irq_ack = rk_tsadcv3_irq_ack, 866 .control = rk_tsadcv3_control, 867 .get_temp = rk_tsadcv2_get_temp, 868 .set_alarm_temp = rk_tsadcv2_alarm_temp, 869 .set_tshut_temp = rk_tsadcv2_tshut_temp, 870 .set_tshut_mode = rk_tsadcv2_tshut_mode, 871 872 .table = { 873 .id = rv1108_table, 874 .length = ARRAY_SIZE(rv1108_table), 875 .data_mask = TSADCV2_DATA_MASK, 876 .mode = ADC_INCREMENT, 877 }, 878 }; 879 880 static const struct rockchip_tsadc_chip rk3228_tsadc_data = { 881 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 882 .chn_num = 1, /* one channel for tsadc */ 883 884 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 885 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 886 .tshut_temp = 95000, 887 888 .initialize = rk_tsadcv2_initialize, 889 .irq_ack = rk_tsadcv3_irq_ack, 890 .control = rk_tsadcv3_control, 891 .get_temp = rk_tsadcv2_get_temp, 892 .set_alarm_temp = rk_tsadcv2_alarm_temp, 893 .set_tshut_temp = rk_tsadcv2_tshut_temp, 894 .set_tshut_mode = rk_tsadcv2_tshut_mode, 895 896 .table = { 897 .id = rk3228_code_table, 898 .length = ARRAY_SIZE(rk3228_code_table), 899 .data_mask = TSADCV3_DATA_MASK, 900 .mode = ADC_INCREMENT, 901 }, 902 }; 903 904 static const struct rockchip_tsadc_chip rk3288_tsadc_data = { 905 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ 906 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ 907 .chn_num = 2, /* two channels for tsadc */ 908 909 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 910 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 911 .tshut_temp = 95000, 912 913 .initialize = rk_tsadcv2_initialize, 914 .irq_ack = rk_tsadcv2_irq_ack, 915 .control = rk_tsadcv2_control, 916 .get_temp = rk_tsadcv2_get_temp, 917 .set_alarm_temp = rk_tsadcv2_alarm_temp, 918 .set_tshut_temp = rk_tsadcv2_tshut_temp, 919 .set_tshut_mode = rk_tsadcv2_tshut_mode, 920 921 .table = { 922 .id = rk3288_code_table, 923 .length = ARRAY_SIZE(rk3288_code_table), 924 .data_mask = TSADCV2_DATA_MASK, 925 .mode = ADC_DECREMENT, 926 }, 927 }; 928 929 static const struct rockchip_tsadc_chip rk3328_tsadc_data = { 930 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 931 .chn_num = 1, /* one channels for tsadc */ 932 933 .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */ 934 .tshut_temp = 95000, 935 936 .initialize = rk_tsadcv2_initialize, 937 .irq_ack = rk_tsadcv3_irq_ack, 938 .control = rk_tsadcv3_control, 939 .get_temp = rk_tsadcv2_get_temp, 940 .set_alarm_temp = rk_tsadcv2_alarm_temp, 941 .set_tshut_temp = rk_tsadcv2_tshut_temp, 942 .set_tshut_mode = rk_tsadcv2_tshut_mode, 943 944 .table = { 945 .id = rk3328_code_table, 946 .length = ARRAY_SIZE(rk3328_code_table), 947 .data_mask = TSADCV2_DATA_MASK, 948 .mode = ADC_INCREMENT, 949 }, 950 }; 951 952 static const struct rockchip_tsadc_chip rk3366_tsadc_data = { 953 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 954 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 955 .chn_num = 2, /* two channels for tsadc */ 956 957 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 958 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 959 .tshut_temp = 95000, 960 961 .initialize = rk_tsadcv3_initialize, 962 .irq_ack = rk_tsadcv3_irq_ack, 963 .control = rk_tsadcv3_control, 964 .get_temp = rk_tsadcv2_get_temp, 965 .set_alarm_temp = rk_tsadcv2_alarm_temp, 966 .set_tshut_temp = rk_tsadcv2_tshut_temp, 967 .set_tshut_mode = rk_tsadcv2_tshut_mode, 968 969 .table = { 970 .id = rk3228_code_table, 971 .length = ARRAY_SIZE(rk3228_code_table), 972 .data_mask = TSADCV3_DATA_MASK, 973 .mode = ADC_INCREMENT, 974 }, 975 }; 976 977 static const struct rockchip_tsadc_chip rk3368_tsadc_data = { 978 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 979 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 980 .chn_num = 2, /* two channels for tsadc */ 981 982 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 983 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 984 .tshut_temp = 95000, 985 986 .initialize = rk_tsadcv2_initialize, 987 .irq_ack = rk_tsadcv2_irq_ack, 988 .control = rk_tsadcv2_control, 989 .get_temp = rk_tsadcv2_get_temp, 990 .set_alarm_temp = rk_tsadcv2_alarm_temp, 991 .set_tshut_temp = rk_tsadcv2_tshut_temp, 992 .set_tshut_mode = rk_tsadcv2_tshut_mode, 993 994 .table = { 995 .id = rk3368_code_table, 996 .length = ARRAY_SIZE(rk3368_code_table), 997 .data_mask = TSADCV3_DATA_MASK, 998 .mode = ADC_INCREMENT, 999 }, 1000 }; 1001 1002 static const struct rockchip_tsadc_chip rk3399_tsadc_data = { 1003 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 1004 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 1005 .chn_num = 2, /* two channels for tsadc */ 1006 1007 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 1008 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 1009 .tshut_temp = 95000, 1010 1011 .initialize = rk_tsadcv3_initialize, 1012 .irq_ack = rk_tsadcv3_irq_ack, 1013 .control = rk_tsadcv3_control, 1014 .get_temp = rk_tsadcv2_get_temp, 1015 .set_alarm_temp = rk_tsadcv2_alarm_temp, 1016 .set_tshut_temp = rk_tsadcv2_tshut_temp, 1017 .set_tshut_mode = rk_tsadcv2_tshut_mode, 1018 1019 .table = { 1020 .id = rk3399_code_table, 1021 .length = ARRAY_SIZE(rk3399_code_table), 1022 .data_mask = TSADCV3_DATA_MASK, 1023 .mode = ADC_INCREMENT, 1024 }, 1025 }; 1026 1027 static const struct of_device_id of_rockchip_thermal_match[] = { 1028 { .compatible = "rockchip,px30-tsadc", 1029 .data = (void *)&px30_tsadc_data, 1030 }, 1031 { 1032 .compatible = "rockchip,rv1108-tsadc", 1033 .data = (void *)&rv1108_tsadc_data, 1034 }, 1035 { 1036 .compatible = "rockchip,rk3228-tsadc", 1037 .data = (void *)&rk3228_tsadc_data, 1038 }, 1039 { 1040 .compatible = "rockchip,rk3288-tsadc", 1041 .data = (void *)&rk3288_tsadc_data, 1042 }, 1043 { 1044 .compatible = "rockchip,rk3328-tsadc", 1045 .data = (void *)&rk3328_tsadc_data, 1046 }, 1047 { 1048 .compatible = "rockchip,rk3366-tsadc", 1049 .data = (void *)&rk3366_tsadc_data, 1050 }, 1051 { 1052 .compatible = "rockchip,rk3368-tsadc", 1053 .data = (void *)&rk3368_tsadc_data, 1054 }, 1055 { 1056 .compatible = "rockchip,rk3399-tsadc", 1057 .data = (void *)&rk3399_tsadc_data, 1058 }, 1059 { /* end */ }, 1060 }; 1061 MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match); 1062 1063 static void 1064 rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on) 1065 { 1066 struct thermal_zone_device *tzd = sensor->tzd; 1067 1068 tzd->ops->set_mode(tzd, 1069 on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED); 1070 } 1071 1072 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev) 1073 { 1074 struct rockchip_thermal_data *thermal = dev; 1075 int i; 1076 1077 dev_dbg(&thermal->pdev->dev, "thermal alarm\n"); 1078 1079 thermal->chip->irq_ack(thermal->regs); 1080 1081 for (i = 0; i < thermal->chip->chn_num; i++) 1082 thermal_zone_device_update(thermal->sensors[i].tzd, 1083 THERMAL_EVENT_UNSPECIFIED); 1084 1085 return IRQ_HANDLED; 1086 } 1087 1088 static int rockchip_thermal_set_trips(void *_sensor, int low, int high) 1089 { 1090 struct rockchip_thermal_sensor *sensor = _sensor; 1091 struct rockchip_thermal_data *thermal = sensor->thermal; 1092 const struct rockchip_tsadc_chip *tsadc = thermal->chip; 1093 1094 dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n", 1095 __func__, sensor->id, low, high); 1096 1097 return tsadc->set_alarm_temp(&tsadc->table, 1098 sensor->id, thermal->regs, high); 1099 } 1100 1101 static int rockchip_thermal_get_temp(void *_sensor, int *out_temp) 1102 { 1103 struct rockchip_thermal_sensor *sensor = _sensor; 1104 struct rockchip_thermal_data *thermal = sensor->thermal; 1105 const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip; 1106 int retval; 1107 1108 retval = tsadc->get_temp(&tsadc->table, 1109 sensor->id, thermal->regs, out_temp); 1110 dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n", 1111 sensor->id, *out_temp, retval); 1112 1113 return retval; 1114 } 1115 1116 static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = { 1117 .get_temp = rockchip_thermal_get_temp, 1118 .set_trips = rockchip_thermal_set_trips, 1119 }; 1120 1121 static int rockchip_configure_from_dt(struct device *dev, 1122 struct device_node *np, 1123 struct rockchip_thermal_data *thermal) 1124 { 1125 u32 shut_temp, tshut_mode, tshut_polarity; 1126 1127 if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) { 1128 dev_warn(dev, 1129 "Missing tshut temp property, using default %d\n", 1130 thermal->chip->tshut_temp); 1131 thermal->tshut_temp = thermal->chip->tshut_temp; 1132 } else { 1133 if (shut_temp > INT_MAX) { 1134 dev_err(dev, "Invalid tshut temperature specified: %d\n", 1135 shut_temp); 1136 return -ERANGE; 1137 } 1138 thermal->tshut_temp = shut_temp; 1139 } 1140 1141 if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) { 1142 dev_warn(dev, 1143 "Missing tshut mode property, using default (%s)\n", 1144 thermal->chip->tshut_mode == TSHUT_MODE_GPIO ? 1145 "gpio" : "cru"); 1146 thermal->tshut_mode = thermal->chip->tshut_mode; 1147 } else { 1148 thermal->tshut_mode = tshut_mode; 1149 } 1150 1151 if (thermal->tshut_mode > 1) { 1152 dev_err(dev, "Invalid tshut mode specified: %d\n", 1153 thermal->tshut_mode); 1154 return -EINVAL; 1155 } 1156 1157 if (of_property_read_u32(np, "rockchip,hw-tshut-polarity", 1158 &tshut_polarity)) { 1159 dev_warn(dev, 1160 "Missing tshut-polarity property, using default (%s)\n", 1161 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ? 1162 "low" : "high"); 1163 thermal->tshut_polarity = thermal->chip->tshut_polarity; 1164 } else { 1165 thermal->tshut_polarity = tshut_polarity; 1166 } 1167 1168 if (thermal->tshut_polarity > 1) { 1169 dev_err(dev, "Invalid tshut-polarity specified: %d\n", 1170 thermal->tshut_polarity); 1171 return -EINVAL; 1172 } 1173 1174 /* The tsadc wont to handle the error in here since some SoCs didn't 1175 * need this property. 1176 */ 1177 thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 1178 if (IS_ERR(thermal->grf)) 1179 dev_warn(dev, "Missing rockchip,grf property\n"); 1180 1181 return 0; 1182 } 1183 1184 static int 1185 rockchip_thermal_register_sensor(struct platform_device *pdev, 1186 struct rockchip_thermal_data *thermal, 1187 struct rockchip_thermal_sensor *sensor, 1188 int id) 1189 { 1190 const struct rockchip_tsadc_chip *tsadc = thermal->chip; 1191 int error; 1192 1193 tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); 1194 1195 error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs, 1196 thermal->tshut_temp); 1197 if (error) 1198 dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n", 1199 __func__, thermal->tshut_temp, error); 1200 1201 sensor->thermal = thermal; 1202 sensor->id = id; 1203 sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id, 1204 sensor, &rockchip_of_thermal_ops); 1205 if (IS_ERR(sensor->tzd)) { 1206 error = PTR_ERR(sensor->tzd); 1207 dev_err(&pdev->dev, "failed to register sensor %d: %d\n", 1208 id, error); 1209 return error; 1210 } 1211 1212 return 0; 1213 } 1214 1215 /** 1216 * Reset TSADC Controller, reset all tsadc registers. 1217 */ 1218 static void rockchip_thermal_reset_controller(struct reset_control *reset) 1219 { 1220 reset_control_assert(reset); 1221 usleep_range(10, 20); 1222 reset_control_deassert(reset); 1223 } 1224 1225 static int rockchip_thermal_probe(struct platform_device *pdev) 1226 { 1227 struct device_node *np = pdev->dev.of_node; 1228 struct rockchip_thermal_data *thermal; 1229 const struct of_device_id *match; 1230 struct resource *res; 1231 int irq; 1232 int i; 1233 int error; 1234 1235 match = of_match_node(of_rockchip_thermal_match, np); 1236 if (!match) 1237 return -ENXIO; 1238 1239 irq = platform_get_irq(pdev, 0); 1240 if (irq < 0) { 1241 dev_err(&pdev->dev, "no irq resource?\n"); 1242 return -EINVAL; 1243 } 1244 1245 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data), 1246 GFP_KERNEL); 1247 if (!thermal) 1248 return -ENOMEM; 1249 1250 thermal->pdev = pdev; 1251 1252 thermal->chip = (const struct rockchip_tsadc_chip *)match->data; 1253 if (!thermal->chip) 1254 return -EINVAL; 1255 1256 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1257 thermal->regs = devm_ioremap_resource(&pdev->dev, res); 1258 if (IS_ERR(thermal->regs)) 1259 return PTR_ERR(thermal->regs); 1260 1261 thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb"); 1262 if (IS_ERR(thermal->reset)) { 1263 error = PTR_ERR(thermal->reset); 1264 dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); 1265 return error; 1266 } 1267 1268 thermal->clk = devm_clk_get(&pdev->dev, "tsadc"); 1269 if (IS_ERR(thermal->clk)) { 1270 error = PTR_ERR(thermal->clk); 1271 dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); 1272 return error; 1273 } 1274 1275 thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); 1276 if (IS_ERR(thermal->pclk)) { 1277 error = PTR_ERR(thermal->pclk); 1278 dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", 1279 error); 1280 return error; 1281 } 1282 1283 error = clk_prepare_enable(thermal->clk); 1284 if (error) { 1285 dev_err(&pdev->dev, "failed to enable converter clock: %d\n", 1286 error); 1287 return error; 1288 } 1289 1290 error = clk_prepare_enable(thermal->pclk); 1291 if (error) { 1292 dev_err(&pdev->dev, "failed to enable pclk: %d\n", error); 1293 goto err_disable_clk; 1294 } 1295 1296 rockchip_thermal_reset_controller(thermal->reset); 1297 1298 error = rockchip_configure_from_dt(&pdev->dev, np, thermal); 1299 if (error) { 1300 dev_err(&pdev->dev, "failed to parse device tree data: %d\n", 1301 error); 1302 goto err_disable_pclk; 1303 } 1304 1305 thermal->chip->initialize(thermal->grf, thermal->regs, 1306 thermal->tshut_polarity); 1307 1308 for (i = 0; i < thermal->chip->chn_num; i++) { 1309 error = rockchip_thermal_register_sensor(pdev, thermal, 1310 &thermal->sensors[i], 1311 thermal->chip->chn_id[i]); 1312 if (error) { 1313 dev_err(&pdev->dev, 1314 "failed to register sensor[%d] : error = %d\n", 1315 i, error); 1316 goto err_disable_pclk; 1317 } 1318 } 1319 1320 error = devm_request_threaded_irq(&pdev->dev, irq, NULL, 1321 &rockchip_thermal_alarm_irq_thread, 1322 IRQF_ONESHOT, 1323 "rockchip_thermal", thermal); 1324 if (error) { 1325 dev_err(&pdev->dev, 1326 "failed to request tsadc irq: %d\n", error); 1327 goto err_disable_pclk; 1328 } 1329 1330 thermal->chip->control(thermal->regs, true); 1331 1332 for (i = 0; i < thermal->chip->chn_num; i++) 1333 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); 1334 1335 platform_set_drvdata(pdev, thermal); 1336 1337 return 0; 1338 1339 err_disable_pclk: 1340 clk_disable_unprepare(thermal->pclk); 1341 err_disable_clk: 1342 clk_disable_unprepare(thermal->clk); 1343 1344 return error; 1345 } 1346 1347 static int rockchip_thermal_remove(struct platform_device *pdev) 1348 { 1349 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); 1350 int i; 1351 1352 for (i = 0; i < thermal->chip->chn_num; i++) { 1353 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i]; 1354 1355 rockchip_thermal_toggle_sensor(sensor, false); 1356 } 1357 1358 thermal->chip->control(thermal->regs, false); 1359 1360 clk_disable_unprepare(thermal->pclk); 1361 clk_disable_unprepare(thermal->clk); 1362 1363 return 0; 1364 } 1365 1366 static int __maybe_unused rockchip_thermal_suspend(struct device *dev) 1367 { 1368 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); 1369 int i; 1370 1371 for (i = 0; i < thermal->chip->chn_num; i++) 1372 rockchip_thermal_toggle_sensor(&thermal->sensors[i], false); 1373 1374 thermal->chip->control(thermal->regs, false); 1375 1376 clk_disable(thermal->pclk); 1377 clk_disable(thermal->clk); 1378 1379 pinctrl_pm_select_sleep_state(dev); 1380 1381 return 0; 1382 } 1383 1384 static int __maybe_unused rockchip_thermal_resume(struct device *dev) 1385 { 1386 struct rockchip_thermal_data *thermal = dev_get_drvdata(dev); 1387 int i; 1388 int error; 1389 1390 error = clk_enable(thermal->clk); 1391 if (error) 1392 return error; 1393 1394 error = clk_enable(thermal->pclk); 1395 if (error) { 1396 clk_disable(thermal->clk); 1397 return error; 1398 } 1399 1400 rockchip_thermal_reset_controller(thermal->reset); 1401 1402 thermal->chip->initialize(thermal->grf, thermal->regs, 1403 thermal->tshut_polarity); 1404 1405 for (i = 0; i < thermal->chip->chn_num; i++) { 1406 int id = thermal->sensors[i].id; 1407 1408 thermal->chip->set_tshut_mode(id, thermal->regs, 1409 thermal->tshut_mode); 1410 1411 error = thermal->chip->set_tshut_temp(&thermal->chip->table, 1412 id, thermal->regs, 1413 thermal->tshut_temp); 1414 if (error) 1415 dev_err(dev, "%s: invalid tshut=%d, error=%d\n", 1416 __func__, thermal->tshut_temp, error); 1417 } 1418 1419 thermal->chip->control(thermal->regs, true); 1420 1421 for (i = 0; i < thermal->chip->chn_num; i++) 1422 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); 1423 1424 pinctrl_pm_select_default_state(dev); 1425 1426 return 0; 1427 } 1428 1429 static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops, 1430 rockchip_thermal_suspend, rockchip_thermal_resume); 1431 1432 static struct platform_driver rockchip_thermal_driver = { 1433 .driver = { 1434 .name = "rockchip-thermal", 1435 .pm = &rockchip_thermal_pm_ops, 1436 .of_match_table = of_rockchip_thermal_match, 1437 }, 1438 .probe = rockchip_thermal_probe, 1439 .remove = rockchip_thermal_remove, 1440 }; 1441 1442 module_platform_driver(rockchip_thermal_driver); 1443 1444 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver"); 1445 MODULE_AUTHOR("Rockchip, Inc."); 1446 MODULE_LICENSE("GPL v2"); 1447 MODULE_ALIAS("platform:rockchip-thermal"); 1448