1 /*
2  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
3  *
4  * Copyright (c) 2015, Fuzhou Rockchip Electronics Co., Ltd
5  * Caesar Wang <wxt@rock-chips.com>
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  */
16 
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/interrupt.h>
20 #include <linux/io.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/platform_device.h>
26 #include <linux/reset.h>
27 #include <linux/thermal.h>
28 #include <linux/pinctrl/consumer.h>
29 
30 /**
31  * If the temperature over a period of time High,
32  * the resulting TSHUT gave CRU module,let it reset the entire chip,
33  * or via GPIO give PMIC.
34  */
35 enum tshut_mode {
36 	TSHUT_MODE_CRU = 0,
37 	TSHUT_MODE_GPIO,
38 };
39 
40 /**
41  * the system Temperature Sensors tshut(tshut) polarity
42  * the bit 8 is tshut polarity.
43  * 0: low active, 1: high active
44  */
45 enum tshut_polarity {
46 	TSHUT_LOW_ACTIVE = 0,
47 	TSHUT_HIGH_ACTIVE,
48 };
49 
50 /**
51  * The system has two Temperature Sensors.
52  * sensor0 is for CPU, and sensor1 is for GPU.
53  */
54 enum sensor_id {
55 	SENSOR_CPU = 0,
56 	SENSOR_GPU,
57 };
58 
59 /**
60 * The conversion table has the adc value and temperature.
61 * ADC_DECREMENT is the adc value decremnet.(e.g. v2_code_table)
62 * ADC_INCREMNET is the adc value incremnet.(e.g. v3_code_table)
63 */
64 enum adc_sort_mode {
65 	ADC_DECREMENT = 0,
66 	ADC_INCREMENT,
67 };
68 
69 /**
70  * The max sensors is two in rockchip SoCs.
71  * Two sensors: CPU and GPU sensor.
72  */
73 #define SOC_MAX_SENSORS	2
74 
75 struct chip_tsadc_table {
76 	const struct tsadc_table *id;
77 
78 	/* the array table size*/
79 	unsigned int length;
80 
81 	/* that analogic mask data */
82 	u32 data_mask;
83 
84 	/* the sort mode is adc value that increment or decrement in table */
85 	enum adc_sort_mode mode;
86 };
87 
88 struct rockchip_tsadc_chip {
89 	/* The sensor id of chip correspond to the ADC channel */
90 	int chn_id[SOC_MAX_SENSORS];
91 	int chn_num;
92 
93 	/* The hardware-controlled tshut property */
94 	int tshut_temp;
95 	enum tshut_mode tshut_mode;
96 	enum tshut_polarity tshut_polarity;
97 
98 	/* Chip-wide methods */
99 	void (*initialize)(void __iomem *reg, enum tshut_polarity p);
100 	void (*irq_ack)(void __iomem *reg);
101 	void (*control)(void __iomem *reg, bool on);
102 
103 	/* Per-sensor methods */
104 	int (*get_temp)(struct chip_tsadc_table table,
105 			int chn, void __iomem *reg, int *temp);
106 	void (*set_tshut_temp)(struct chip_tsadc_table table,
107 			       int chn, void __iomem *reg, int temp);
108 	void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
109 
110 	/* Per-table methods */
111 	struct chip_tsadc_table table;
112 };
113 
114 struct rockchip_thermal_sensor {
115 	struct rockchip_thermal_data *thermal;
116 	struct thermal_zone_device *tzd;
117 	int id;
118 };
119 
120 struct rockchip_thermal_data {
121 	const struct rockchip_tsadc_chip *chip;
122 	struct platform_device *pdev;
123 	struct reset_control *reset;
124 
125 	struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
126 
127 	struct clk *clk;
128 	struct clk *pclk;
129 
130 	void __iomem *regs;
131 
132 	int tshut_temp;
133 	enum tshut_mode tshut_mode;
134 	enum tshut_polarity tshut_polarity;
135 };
136 
137 /* TSADC Sensor info define: */
138 #define TSADCV2_AUTO_CON			0x04
139 #define TSADCV2_INT_EN				0x08
140 #define TSADCV2_INT_PD				0x0c
141 #define TSADCV2_DATA(chn)			(0x20 + (chn) * 0x04)
142 #define TSADCV2_COMP_SHUT(chn)		        (0x40 + (chn) * 0x04)
143 #define TSADCV2_HIGHT_INT_DEBOUNCE		0x60
144 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE		0x64
145 #define TSADCV2_AUTO_PERIOD			0x68
146 #define TSADCV2_AUTO_PERIOD_HT			0x6c
147 
148 #define TSADCV2_AUTO_EN				BIT(0)
149 #define TSADCV2_AUTO_SRC_EN(chn)		BIT(4 + (chn))
150 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH	BIT(8)
151 
152 #define TSADCV2_INT_SRC_EN(chn)			BIT(chn)
153 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn)		BIT(4 + (chn))
154 #define TSADCV2_SHUT_2CRU_SRC_EN(chn)		BIT(8 + (chn))
155 
156 #define TSADCV2_INT_PD_CLEAR_MASK		~BIT(8)
157 
158 #define TSADCV2_DATA_MASK			0xfff
159 #define TSADCV3_DATA_MASK			0x3ff
160 
161 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT	4
162 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT	4
163 #define TSADCV2_AUTO_PERIOD_TIME		250 /* msec */
164 #define TSADCV2_AUTO_PERIOD_HT_TIME		50  /* msec */
165 
166 struct tsadc_table {
167 	u32 code;
168 	int temp;
169 };
170 
171 static const struct tsadc_table v2_code_table[] = {
172 	{TSADCV2_DATA_MASK, -40000},
173 	{3800, -40000},
174 	{3792, -35000},
175 	{3783, -30000},
176 	{3774, -25000},
177 	{3765, -20000},
178 	{3756, -15000},
179 	{3747, -10000},
180 	{3737, -5000},
181 	{3728, 0},
182 	{3718, 5000},
183 	{3708, 10000},
184 	{3698, 15000},
185 	{3688, 20000},
186 	{3678, 25000},
187 	{3667, 30000},
188 	{3656, 35000},
189 	{3645, 40000},
190 	{3634, 45000},
191 	{3623, 50000},
192 	{3611, 55000},
193 	{3600, 60000},
194 	{3588, 65000},
195 	{3575, 70000},
196 	{3563, 75000},
197 	{3550, 80000},
198 	{3537, 85000},
199 	{3524, 90000},
200 	{3510, 95000},
201 	{3496, 100000},
202 	{3482, 105000},
203 	{3467, 110000},
204 	{3452, 115000},
205 	{3437, 120000},
206 	{3421, 125000},
207 };
208 
209 static const struct tsadc_table v3_code_table[] = {
210 	{0, -40000},
211 	{106, -40000},
212 	{108, -35000},
213 	{110, -30000},
214 	{112, -25000},
215 	{114, -20000},
216 	{116, -15000},
217 	{118, -10000},
218 	{120, -5000},
219 	{122, 0},
220 	{124, 5000},
221 	{126, 10000},
222 	{128, 15000},
223 	{130, 20000},
224 	{132, 25000},
225 	{134, 30000},
226 	{136, 35000},
227 	{138, 40000},
228 	{140, 45000},
229 	{142, 50000},
230 	{144, 55000},
231 	{146, 60000},
232 	{148, 65000},
233 	{150, 70000},
234 	{152, 75000},
235 	{154, 80000},
236 	{156, 85000},
237 	{158, 90000},
238 	{160, 95000},
239 	{162, 100000},
240 	{163, 105000},
241 	{165, 110000},
242 	{167, 115000},
243 	{169, 120000},
244 	{171, 125000},
245 	{TSADCV3_DATA_MASK, 125000},
246 };
247 
248 static u32 rk_tsadcv2_temp_to_code(struct chip_tsadc_table table,
249 				   int temp)
250 {
251 	int high, low, mid;
252 
253 	low = 0;
254 	high = table.length - 1;
255 	mid = (high + low) / 2;
256 
257 	if (temp < table.id[low].temp || temp > table.id[high].temp)
258 		return 0;
259 
260 	while (low <= high) {
261 		if (temp == table.id[mid].temp)
262 			return table.id[mid].code;
263 		else if (temp < table.id[mid].temp)
264 			high = mid - 1;
265 		else
266 			low = mid + 1;
267 		mid = (low + high) / 2;
268 	}
269 
270 	return 0;
271 }
272 
273 static int rk_tsadcv2_code_to_temp(struct chip_tsadc_table table, u32 code,
274 				   int *temp)
275 {
276 	unsigned int low = 1;
277 	unsigned int high = table.length - 1;
278 	unsigned int mid = (low + high) / 2;
279 	unsigned int num;
280 	unsigned long denom;
281 
282 	WARN_ON(table.length < 2);
283 
284 	switch (table.mode) {
285 	case ADC_DECREMENT:
286 		code &= table.data_mask;
287 		if (code < table.id[high].code)
288 			return -EAGAIN;		/* Incorrect reading */
289 
290 		while (low <= high) {
291 			if (code >= table.id[mid].code &&
292 			    code < table.id[mid - 1].code)
293 				break;
294 			else if (code < table.id[mid].code)
295 				low = mid + 1;
296 			else
297 				high = mid - 1;
298 
299 			mid = (low + high) / 2;
300 		}
301 		break;
302 	case ADC_INCREMENT:
303 		code &= table.data_mask;
304 		if (code < table.id[low].code)
305 			return -EAGAIN;		/* Incorrect reading */
306 
307 		while (low <= high) {
308 			if (code >= table.id[mid - 1].code &&
309 			    code < table.id[mid].code)
310 				break;
311 			else if (code > table.id[mid].code)
312 				low = mid + 1;
313 			else
314 				high = mid - 1;
315 
316 			mid = (low + high) / 2;
317 		}
318 		break;
319 	default:
320 		pr_err("Invalid the conversion table\n");
321 	}
322 
323 	/*
324 	 * The 5C granularity provided by the table is too much. Let's
325 	 * assume that the relationship between sensor readings and
326 	 * temperature between 2 table entries is linear and interpolate
327 	 * to produce less granular result.
328 	 */
329 	num = table.id[mid].temp - v2_code_table[mid - 1].temp;
330 	num *= abs(table.id[mid - 1].code - code);
331 	denom = abs(table.id[mid - 1].code - table.id[mid].code);
332 	*temp = table.id[mid - 1].temp + (num / denom);
333 
334 	return 0;
335 }
336 
337 /**
338  * rk_tsadcv2_initialize - initialize TASDC Controller.
339  *
340  * (1) Set TSADC_V2_AUTO_PERIOD:
341  *     Configure the interleave between every two accessing of
342  *     TSADC in normal operation.
343  *
344  * (2) Set TSADCV2_AUTO_PERIOD_HT:
345  *     Configure the interleave between every two accessing of
346  *     TSADC after the temperature is higher than COM_SHUT or COM_INT.
347  *
348  * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
349  *     If the temperature is higher than COMP_INT or COMP_SHUT for
350  *     "debounce" times, TSADC controller will generate interrupt or TSHUT.
351  */
352 static void rk_tsadcv2_initialize(void __iomem *regs,
353 				  enum tshut_polarity tshut_polarity)
354 {
355 	if (tshut_polarity == TSHUT_HIGH_ACTIVE)
356 		writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
357 			       regs + TSADCV2_AUTO_CON);
358 	else
359 		writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
360 			       regs + TSADCV2_AUTO_CON);
361 
362 	writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
363 	writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
364 		       regs + TSADCV2_HIGHT_INT_DEBOUNCE);
365 	writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
366 		       regs + TSADCV2_AUTO_PERIOD_HT);
367 	writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
368 		       regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
369 }
370 
371 static void rk_tsadcv2_irq_ack(void __iomem *regs)
372 {
373 	u32 val;
374 
375 	val = readl_relaxed(regs + TSADCV2_INT_PD);
376 	writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
377 }
378 
379 static void rk_tsadcv2_control(void __iomem *regs, bool enable)
380 {
381 	u32 val;
382 
383 	val = readl_relaxed(regs + TSADCV2_AUTO_CON);
384 	if (enable)
385 		val |= TSADCV2_AUTO_EN;
386 	else
387 		val &= ~TSADCV2_AUTO_EN;
388 
389 	writel_relaxed(val, regs + TSADCV2_AUTO_CON);
390 }
391 
392 static int rk_tsadcv2_get_temp(struct chip_tsadc_table table,
393 			       int chn, void __iomem *regs, int *temp)
394 {
395 	u32 val;
396 
397 	val = readl_relaxed(regs + TSADCV2_DATA(chn));
398 
399 	return rk_tsadcv2_code_to_temp(table, val, temp);
400 }
401 
402 static void rk_tsadcv2_tshut_temp(struct chip_tsadc_table table,
403 				  int chn, void __iomem *regs, int temp)
404 {
405 	u32 tshut_value, val;
406 
407 	tshut_value = rk_tsadcv2_temp_to_code(table, temp);
408 	writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
409 
410 	/* TSHUT will be valid */
411 	val = readl_relaxed(regs + TSADCV2_AUTO_CON);
412 	writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
413 }
414 
415 static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
416 				  enum tshut_mode mode)
417 {
418 	u32 val;
419 
420 	val = readl_relaxed(regs + TSADCV2_INT_EN);
421 	if (mode == TSHUT_MODE_GPIO) {
422 		val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
423 		val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
424 	} else {
425 		val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
426 		val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
427 	}
428 
429 	writel_relaxed(val, regs + TSADCV2_INT_EN);
430 }
431 
432 static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
433 	.chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
434 	.chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
435 	.chn_num = 2, /* two channels for tsadc */
436 
437 	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
438 	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
439 	.tshut_temp = 95000,
440 
441 	.initialize = rk_tsadcv2_initialize,
442 	.irq_ack = rk_tsadcv2_irq_ack,
443 	.control = rk_tsadcv2_control,
444 	.get_temp = rk_tsadcv2_get_temp,
445 	.set_tshut_temp = rk_tsadcv2_tshut_temp,
446 	.set_tshut_mode = rk_tsadcv2_tshut_mode,
447 
448 	.table = {
449 		.id = v2_code_table,
450 		.length = ARRAY_SIZE(v2_code_table),
451 		.data_mask = TSADCV2_DATA_MASK,
452 		.mode = ADC_DECREMENT,
453 	},
454 };
455 
456 static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
457 	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
458 	.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
459 	.chn_num = 2, /* two channels for tsadc */
460 
461 	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
462 	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
463 	.tshut_temp = 95000,
464 
465 	.initialize = rk_tsadcv2_initialize,
466 	.irq_ack = rk_tsadcv2_irq_ack,
467 	.control = rk_tsadcv2_control,
468 	.get_temp = rk_tsadcv2_get_temp,
469 	.set_tshut_temp = rk_tsadcv2_tshut_temp,
470 	.set_tshut_mode = rk_tsadcv2_tshut_mode,
471 
472 	.table = {
473 		.id = v3_code_table,
474 		.length = ARRAY_SIZE(v3_code_table),
475 		.data_mask = TSADCV3_DATA_MASK,
476 		.mode = ADC_INCREMENT,
477 	},
478 };
479 
480 static const struct of_device_id of_rockchip_thermal_match[] = {
481 	{
482 		.compatible = "rockchip,rk3288-tsadc",
483 		.data = (void *)&rk3288_tsadc_data,
484 	},
485 	{
486 		.compatible = "rockchip,rk3368-tsadc",
487 		.data = (void *)&rk3368_tsadc_data,
488 	},
489 	{ /* end */ },
490 };
491 MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
492 
493 static void
494 rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
495 {
496 	struct thermal_zone_device *tzd = sensor->tzd;
497 
498 	tzd->ops->set_mode(tzd,
499 		on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED);
500 }
501 
502 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
503 {
504 	struct rockchip_thermal_data *thermal = dev;
505 	int i;
506 
507 	dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
508 
509 	thermal->chip->irq_ack(thermal->regs);
510 
511 	for (i = 0; i < thermal->chip->chn_num; i++)
512 		thermal_zone_device_update(thermal->sensors[i].tzd);
513 
514 	return IRQ_HANDLED;
515 }
516 
517 static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
518 {
519 	struct rockchip_thermal_sensor *sensor = _sensor;
520 	struct rockchip_thermal_data *thermal = sensor->thermal;
521 	const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
522 	int retval;
523 
524 	retval = tsadc->get_temp(tsadc->table,
525 				 sensor->id, thermal->regs, out_temp);
526 	dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
527 		sensor->id, *out_temp, retval);
528 
529 	return retval;
530 }
531 
532 static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
533 	.get_temp = rockchip_thermal_get_temp,
534 };
535 
536 static int rockchip_configure_from_dt(struct device *dev,
537 				      struct device_node *np,
538 				      struct rockchip_thermal_data *thermal)
539 {
540 	u32 shut_temp, tshut_mode, tshut_polarity;
541 
542 	if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
543 		dev_warn(dev,
544 			 "Missing tshut temp property, using default %d\n",
545 			 thermal->chip->tshut_temp);
546 		thermal->tshut_temp = thermal->chip->tshut_temp;
547 	} else {
548 		thermal->tshut_temp = shut_temp;
549 	}
550 
551 	if (thermal->tshut_temp > INT_MAX) {
552 		dev_err(dev, "Invalid tshut temperature specified: %d\n",
553 			thermal->tshut_temp);
554 		return -ERANGE;
555 	}
556 
557 	if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
558 		dev_warn(dev,
559 			 "Missing tshut mode property, using default (%s)\n",
560 			 thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
561 				"gpio" : "cru");
562 		thermal->tshut_mode = thermal->chip->tshut_mode;
563 	} else {
564 		thermal->tshut_mode = tshut_mode;
565 	}
566 
567 	if (thermal->tshut_mode > 1) {
568 		dev_err(dev, "Invalid tshut mode specified: %d\n",
569 			thermal->tshut_mode);
570 		return -EINVAL;
571 	}
572 
573 	if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
574 				 &tshut_polarity)) {
575 		dev_warn(dev,
576 			 "Missing tshut-polarity property, using default (%s)\n",
577 			 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
578 				"low" : "high");
579 		thermal->tshut_polarity = thermal->chip->tshut_polarity;
580 	} else {
581 		thermal->tshut_polarity = tshut_polarity;
582 	}
583 
584 	if (thermal->tshut_polarity > 1) {
585 		dev_err(dev, "Invalid tshut-polarity specified: %d\n",
586 			thermal->tshut_polarity);
587 		return -EINVAL;
588 	}
589 
590 	return 0;
591 }
592 
593 static int
594 rockchip_thermal_register_sensor(struct platform_device *pdev,
595 				 struct rockchip_thermal_data *thermal,
596 				 struct rockchip_thermal_sensor *sensor,
597 				 int id)
598 {
599 	const struct rockchip_tsadc_chip *tsadc = thermal->chip;
600 	int error;
601 
602 	tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
603 	tsadc->set_tshut_temp(tsadc->table, id, thermal->regs,
604 			      thermal->tshut_temp);
605 
606 	sensor->thermal = thermal;
607 	sensor->id = id;
608 	sensor->tzd = thermal_zone_of_sensor_register(&pdev->dev, id, sensor,
609 						      &rockchip_of_thermal_ops);
610 	if (IS_ERR(sensor->tzd)) {
611 		error = PTR_ERR(sensor->tzd);
612 		dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
613 			id, error);
614 		return error;
615 	}
616 
617 	return 0;
618 }
619 
620 /*
621  * Reset TSADC Controller, reset all tsadc registers.
622  */
623 static void rockchip_thermal_reset_controller(struct reset_control *reset)
624 {
625 	reset_control_assert(reset);
626 	usleep_range(10, 20);
627 	reset_control_deassert(reset);
628 }
629 
630 static int rockchip_thermal_probe(struct platform_device *pdev)
631 {
632 	struct device_node *np = pdev->dev.of_node;
633 	struct rockchip_thermal_data *thermal;
634 	const struct of_device_id *match;
635 	struct resource *res;
636 	int irq;
637 	int i, j;
638 	int error;
639 
640 	match = of_match_node(of_rockchip_thermal_match, np);
641 	if (!match)
642 		return -ENXIO;
643 
644 	irq = platform_get_irq(pdev, 0);
645 	if (irq < 0) {
646 		dev_err(&pdev->dev, "no irq resource?\n");
647 		return -EINVAL;
648 	}
649 
650 	thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
651 			       GFP_KERNEL);
652 	if (!thermal)
653 		return -ENOMEM;
654 
655 	thermal->pdev = pdev;
656 
657 	thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
658 	if (!thermal->chip)
659 		return -EINVAL;
660 
661 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
662 	thermal->regs = devm_ioremap_resource(&pdev->dev, res);
663 	if (IS_ERR(thermal->regs))
664 		return PTR_ERR(thermal->regs);
665 
666 	thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
667 	if (IS_ERR(thermal->reset)) {
668 		error = PTR_ERR(thermal->reset);
669 		dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
670 		return error;
671 	}
672 
673 	thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
674 	if (IS_ERR(thermal->clk)) {
675 		error = PTR_ERR(thermal->clk);
676 		dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
677 		return error;
678 	}
679 
680 	thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
681 	if (IS_ERR(thermal->pclk)) {
682 		error = PTR_ERR(thermal->pclk);
683 		dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
684 			error);
685 		return error;
686 	}
687 
688 	error = clk_prepare_enable(thermal->clk);
689 	if (error) {
690 		dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
691 			error);
692 		return error;
693 	}
694 
695 	error = clk_prepare_enable(thermal->pclk);
696 	if (error) {
697 		dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
698 		goto err_disable_clk;
699 	}
700 
701 	rockchip_thermal_reset_controller(thermal->reset);
702 
703 	error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
704 	if (error) {
705 		dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
706 			error);
707 		goto err_disable_pclk;
708 	}
709 
710 	thermal->chip->initialize(thermal->regs, thermal->tshut_polarity);
711 
712 	for (i = 0; i < thermal->chip->chn_num; i++) {
713 		error = rockchip_thermal_register_sensor(pdev, thermal,
714 						&thermal->sensors[i],
715 						thermal->chip->chn_id[i]);
716 		if (error) {
717 			dev_err(&pdev->dev,
718 				"failed to register sensor[%d] : error = %d\n",
719 				i, error);
720 			for (j = 0; j < i; j++)
721 				thermal_zone_of_sensor_unregister(&pdev->dev,
722 						thermal->sensors[j].tzd);
723 			goto err_disable_pclk;
724 		}
725 	}
726 
727 	error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
728 					  &rockchip_thermal_alarm_irq_thread,
729 					  IRQF_ONESHOT,
730 					  "rockchip_thermal", thermal);
731 	if (error) {
732 		dev_err(&pdev->dev,
733 			"failed to request tsadc irq: %d\n", error);
734 		goto err_unregister_sensor;
735 	}
736 
737 	thermal->chip->control(thermal->regs, true);
738 
739 	for (i = 0; i < thermal->chip->chn_num; i++)
740 		rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
741 
742 	platform_set_drvdata(pdev, thermal);
743 
744 	return 0;
745 
746 err_unregister_sensor:
747 	while (i--)
748 		thermal_zone_of_sensor_unregister(&pdev->dev,
749 						  thermal->sensors[i].tzd);
750 
751 err_disable_pclk:
752 	clk_disable_unprepare(thermal->pclk);
753 err_disable_clk:
754 	clk_disable_unprepare(thermal->clk);
755 
756 	return error;
757 }
758 
759 static int rockchip_thermal_remove(struct platform_device *pdev)
760 {
761 	struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
762 	int i;
763 
764 	for (i = 0; i < thermal->chip->chn_num; i++) {
765 		struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
766 
767 		rockchip_thermal_toggle_sensor(sensor, false);
768 		thermal_zone_of_sensor_unregister(&pdev->dev, sensor->tzd);
769 	}
770 
771 	thermal->chip->control(thermal->regs, false);
772 
773 	clk_disable_unprepare(thermal->pclk);
774 	clk_disable_unprepare(thermal->clk);
775 
776 	return 0;
777 }
778 
779 static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
780 {
781 	struct platform_device *pdev = to_platform_device(dev);
782 	struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
783 	int i;
784 
785 	for (i = 0; i < thermal->chip->chn_num; i++)
786 		rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
787 
788 	thermal->chip->control(thermal->regs, false);
789 
790 	clk_disable(thermal->pclk);
791 	clk_disable(thermal->clk);
792 
793 	pinctrl_pm_select_sleep_state(dev);
794 
795 	return 0;
796 }
797 
798 static int __maybe_unused rockchip_thermal_resume(struct device *dev)
799 {
800 	struct platform_device *pdev = to_platform_device(dev);
801 	struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
802 	int i;
803 	int error;
804 
805 	error = clk_enable(thermal->clk);
806 	if (error)
807 		return error;
808 
809 	error = clk_enable(thermal->pclk);
810 	if (error)
811 		return error;
812 
813 	rockchip_thermal_reset_controller(thermal->reset);
814 
815 	thermal->chip->initialize(thermal->regs, thermal->tshut_polarity);
816 
817 	for (i = 0; i < thermal->chip->chn_num; i++) {
818 		int id = thermal->sensors[i].id;
819 
820 		thermal->chip->set_tshut_mode(id, thermal->regs,
821 					      thermal->tshut_mode);
822 		thermal->chip->set_tshut_temp(thermal->chip->table,
823 					      id, thermal->regs,
824 					      thermal->tshut_temp);
825 	}
826 
827 	thermal->chip->control(thermal->regs, true);
828 
829 	for (i = 0; i < thermal->chip->chn_num; i++)
830 		rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
831 
832 	pinctrl_pm_select_default_state(dev);
833 
834 	return 0;
835 }
836 
837 static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
838 			 rockchip_thermal_suspend, rockchip_thermal_resume);
839 
840 static struct platform_driver rockchip_thermal_driver = {
841 	.driver = {
842 		.name = "rockchip-thermal",
843 		.pm = &rockchip_thermal_pm_ops,
844 		.of_match_table = of_rockchip_thermal_match,
845 	},
846 	.probe = rockchip_thermal_probe,
847 	.remove = rockchip_thermal_remove,
848 };
849 
850 module_platform_driver(rockchip_thermal_driver);
851 
852 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
853 MODULE_AUTHOR("Rockchip, Inc.");
854 MODULE_LICENSE("GPL v2");
855 MODULE_ALIAS("platform:rockchip-thermal");
856