1cbac8f63SCaesar Wang /* 2678065d5SCaesar Wang * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd 320f0af75SCaesar Wang * Caesar Wang <wxt@rock-chips.com> 420f0af75SCaesar Wang * 5cbac8f63SCaesar Wang * This program is free software; you can redistribute it and/or modify it 6cbac8f63SCaesar Wang * under the terms and conditions of the GNU General Public License, 7cbac8f63SCaesar Wang * version 2, as published by the Free Software Foundation. 8cbac8f63SCaesar Wang * 9cbac8f63SCaesar Wang * This program is distributed in the hope it will be useful, but WITHOUT 10cbac8f63SCaesar Wang * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11cbac8f63SCaesar Wang * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12cbac8f63SCaesar Wang * more details. 13cbac8f63SCaesar Wang */ 14cbac8f63SCaesar Wang 15cbac8f63SCaesar Wang #include <linux/clk.h> 16cbac8f63SCaesar Wang #include <linux/delay.h> 17cbac8f63SCaesar Wang #include <linux/interrupt.h> 18cbac8f63SCaesar Wang #include <linux/io.h> 19cbac8f63SCaesar Wang #include <linux/module.h> 20cbac8f63SCaesar Wang #include <linux/of.h> 21cbac8f63SCaesar Wang #include <linux/of_address.h> 22cbac8f63SCaesar Wang #include <linux/of_irq.h> 23cbac8f63SCaesar Wang #include <linux/platform_device.h> 24b9484763SCaesar Wang #include <linux/regmap.h> 25cbac8f63SCaesar Wang #include <linux/reset.h> 26cbac8f63SCaesar Wang #include <linux/thermal.h> 27b9484763SCaesar Wang #include <linux/mfd/syscon.h> 28c970872eSCaesar Wang #include <linux/pinctrl/consumer.h> 29cbac8f63SCaesar Wang 30cbac8f63SCaesar Wang /** 31cbac8f63SCaesar Wang * If the temperature over a period of time High, 32cbac8f63SCaesar Wang * the resulting TSHUT gave CRU module,let it reset the entire chip, 33cbac8f63SCaesar Wang * or via GPIO give PMIC. 34cbac8f63SCaesar Wang */ 35cbac8f63SCaesar Wang enum tshut_mode { 36cbac8f63SCaesar Wang TSHUT_MODE_CRU = 0, 37cbac8f63SCaesar Wang TSHUT_MODE_GPIO, 38cbac8f63SCaesar Wang }; 39cbac8f63SCaesar Wang 40cbac8f63SCaesar Wang /** 4113c1cfdaSCaesar Wang * The system Temperature Sensors tshut(tshut) polarity 42cbac8f63SCaesar Wang * the bit 8 is tshut polarity. 43cbac8f63SCaesar Wang * 0: low active, 1: high active 44cbac8f63SCaesar Wang */ 45cbac8f63SCaesar Wang enum tshut_polarity { 46cbac8f63SCaesar Wang TSHUT_LOW_ACTIVE = 0, 47cbac8f63SCaesar Wang TSHUT_HIGH_ACTIVE, 48cbac8f63SCaesar Wang }; 49cbac8f63SCaesar Wang 50cbac8f63SCaesar Wang /** 511d98b618SCaesar Wang * The system has two Temperature Sensors. 521d98b618SCaesar Wang * sensor0 is for CPU, and sensor1 is for GPU. 53cbac8f63SCaesar Wang */ 54cbac8f63SCaesar Wang enum sensor_id { 551d98b618SCaesar Wang SENSOR_CPU = 0, 56cbac8f63SCaesar Wang SENSOR_GPU, 57cbac8f63SCaesar Wang }; 58cbac8f63SCaesar Wang 591d98b618SCaesar Wang /** 60020ba95dSCaesar Wang * The conversion table has the adc value and temperature. 61952418a3SCaesar Wang * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table) 62952418a3SCaesar Wang * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table) 63020ba95dSCaesar Wang */ 64020ba95dSCaesar Wang enum adc_sort_mode { 65020ba95dSCaesar Wang ADC_DECREMENT = 0, 66020ba95dSCaesar Wang ADC_INCREMENT, 67020ba95dSCaesar Wang }; 68020ba95dSCaesar Wang 69020ba95dSCaesar Wang /** 701d98b618SCaesar Wang * The max sensors is two in rockchip SoCs. 711d98b618SCaesar Wang * Two sensors: CPU and GPU sensor. 721d98b618SCaesar Wang */ 731d98b618SCaesar Wang #define SOC_MAX_SENSORS 2 741d98b618SCaesar Wang 7513c1cfdaSCaesar Wang /** 76678065d5SCaesar Wang * struct chip_tsadc_table - hold information about chip-specific differences 7713c1cfdaSCaesar Wang * @id: conversion table 7813c1cfdaSCaesar Wang * @length: size of conversion table 7913c1cfdaSCaesar Wang * @data_mask: mask to apply on data inputs 8013c1cfdaSCaesar Wang * @mode: sort mode of this adc variant (incrementing or decrementing) 8113c1cfdaSCaesar Wang */ 82ce74110dSCaesar Wang struct chip_tsadc_table { 83ce74110dSCaesar Wang const struct tsadc_table *id; 84ce74110dSCaesar Wang unsigned int length; 85ce74110dSCaesar Wang u32 data_mask; 86020ba95dSCaesar Wang enum adc_sort_mode mode; 87ce74110dSCaesar Wang }; 88ce74110dSCaesar Wang 89678065d5SCaesar Wang /** 90678065d5SCaesar Wang * struct rockchip_tsadc_chip - hold the private data of tsadc chip 91678065d5SCaesar Wang * @chn_id[SOC_MAX_SENSORS]: the sensor id of chip correspond to the channel 92678065d5SCaesar Wang * @chn_num: the channel number of tsadc chip 93678065d5SCaesar Wang * @tshut_temp: the hardware-controlled shutdown temperature value 94678065d5SCaesar Wang * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) 95678065d5SCaesar Wang * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) 96678065d5SCaesar Wang * @initialize: SoC special initialize tsadc controller method 97678065d5SCaesar Wang * @irq_ack: clear the interrupt 98678065d5SCaesar Wang * @get_temp: get the temperature 9914848502SCaesar Wang * @set_alarm_temp: set the high temperature interrupt 100678065d5SCaesar Wang * @set_tshut_temp: set the hardware-controlled shutdown temperature 101678065d5SCaesar Wang * @set_tshut_mode: set the hardware-controlled shutdown mode 102678065d5SCaesar Wang * @table: the chip-specific conversion table 103678065d5SCaesar Wang */ 104cbac8f63SCaesar Wang struct rockchip_tsadc_chip { 1051d98b618SCaesar Wang /* The sensor id of chip correspond to the ADC channel */ 1061d98b618SCaesar Wang int chn_id[SOC_MAX_SENSORS]; 1071d98b618SCaesar Wang int chn_num; 1081d98b618SCaesar Wang 109cbac8f63SCaesar Wang /* The hardware-controlled tshut property */ 110437df217SCaesar Wang int tshut_temp; 111cbac8f63SCaesar Wang enum tshut_mode tshut_mode; 112cbac8f63SCaesar Wang enum tshut_polarity tshut_polarity; 113cbac8f63SCaesar Wang 114cbac8f63SCaesar Wang /* Chip-wide methods */ 115b9484763SCaesar Wang void (*initialize)(struct regmap *grf, 116b9484763SCaesar Wang void __iomem *reg, enum tshut_polarity p); 117cbac8f63SCaesar Wang void (*irq_ack)(void __iomem *reg); 118cbac8f63SCaesar Wang void (*control)(void __iomem *reg, bool on); 119cbac8f63SCaesar Wang 120cbac8f63SCaesar Wang /* Per-sensor methods */ 121ce74110dSCaesar Wang int (*get_temp)(struct chip_tsadc_table table, 122ce74110dSCaesar Wang int chn, void __iomem *reg, int *temp); 12314848502SCaesar Wang void (*set_alarm_temp)(struct chip_tsadc_table table, 12414848502SCaesar Wang int chn, void __iomem *reg, int temp); 125ce74110dSCaesar Wang void (*set_tshut_temp)(struct chip_tsadc_table table, 126437df217SCaesar Wang int chn, void __iomem *reg, int temp); 127cbac8f63SCaesar Wang void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m); 128ce74110dSCaesar Wang 129ce74110dSCaesar Wang /* Per-table methods */ 130ce74110dSCaesar Wang struct chip_tsadc_table table; 131cbac8f63SCaesar Wang }; 132cbac8f63SCaesar Wang 133678065d5SCaesar Wang /** 134678065d5SCaesar Wang * struct rockchip_thermal_sensor - hold the information of thermal sensor 135678065d5SCaesar Wang * @thermal: pointer to the platform/configuration data 136678065d5SCaesar Wang * @tzd: pointer to a thermal zone 137678065d5SCaesar Wang * @id: identifier of the thermal sensor 138678065d5SCaesar Wang */ 139cbac8f63SCaesar Wang struct rockchip_thermal_sensor { 140cbac8f63SCaesar Wang struct rockchip_thermal_data *thermal; 141cbac8f63SCaesar Wang struct thermal_zone_device *tzd; 1421d98b618SCaesar Wang int id; 143cbac8f63SCaesar Wang }; 144cbac8f63SCaesar Wang 145678065d5SCaesar Wang /** 146678065d5SCaesar Wang * struct rockchip_thermal_data - hold the private data of thermal driver 147678065d5SCaesar Wang * @chip: pointer to the platform/configuration data 148678065d5SCaesar Wang * @pdev: platform device of thermal 149678065d5SCaesar Wang * @reset: the reset controller of tsadc 150678065d5SCaesar Wang * @sensors[SOC_MAX_SENSORS]: the thermal sensor 151678065d5SCaesar Wang * @clk: the controller clock is divided by the exteral 24MHz 152678065d5SCaesar Wang * @pclk: the advanced peripherals bus clock 153678065d5SCaesar Wang * @grf: the general register file will be used to do static set by software 154678065d5SCaesar Wang * @regs: the base address of tsadc controller 155678065d5SCaesar Wang * @tshut_temp: the hardware-controlled shutdown temperature value 156678065d5SCaesar Wang * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) 157678065d5SCaesar Wang * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) 158678065d5SCaesar Wang */ 159cbac8f63SCaesar Wang struct rockchip_thermal_data { 160cbac8f63SCaesar Wang const struct rockchip_tsadc_chip *chip; 161cbac8f63SCaesar Wang struct platform_device *pdev; 162cbac8f63SCaesar Wang struct reset_control *reset; 163cbac8f63SCaesar Wang 1641d98b618SCaesar Wang struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS]; 165cbac8f63SCaesar Wang 166cbac8f63SCaesar Wang struct clk *clk; 167cbac8f63SCaesar Wang struct clk *pclk; 168cbac8f63SCaesar Wang 169b9484763SCaesar Wang struct regmap *grf; 170cbac8f63SCaesar Wang void __iomem *regs; 171cbac8f63SCaesar Wang 172437df217SCaesar Wang int tshut_temp; 173cbac8f63SCaesar Wang enum tshut_mode tshut_mode; 174cbac8f63SCaesar Wang enum tshut_polarity tshut_polarity; 175cbac8f63SCaesar Wang }; 176cbac8f63SCaesar Wang 177952418a3SCaesar Wang /** 178952418a3SCaesar Wang * TSADC Sensor Register description: 179952418a3SCaesar Wang * 180952418a3SCaesar Wang * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it. 181952418a3SCaesar Wang * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399) 182952418a3SCaesar Wang * 183952418a3SCaesar Wang */ 184b9484763SCaesar Wang #define TSADCV2_USER_CON 0x00 185cbac8f63SCaesar Wang #define TSADCV2_AUTO_CON 0x04 186cbac8f63SCaesar Wang #define TSADCV2_INT_EN 0x08 187cbac8f63SCaesar Wang #define TSADCV2_INT_PD 0x0c 188cbac8f63SCaesar Wang #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04) 18914848502SCaesar Wang #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04) 190cbac8f63SCaesar Wang #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04) 191cbac8f63SCaesar Wang #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60 192cbac8f63SCaesar Wang #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64 193cbac8f63SCaesar Wang #define TSADCV2_AUTO_PERIOD 0x68 194cbac8f63SCaesar Wang #define TSADCV2_AUTO_PERIOD_HT 0x6c 195cbac8f63SCaesar Wang 196cbac8f63SCaesar Wang #define TSADCV2_AUTO_EN BIT(0) 197cbac8f63SCaesar Wang #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn)) 198cbac8f63SCaesar Wang #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8) 199678065d5SCaesar Wang 2007ea38c6cSCaesar Wang #define TSADCV3_AUTO_Q_SEL_EN BIT(1) 201cbac8f63SCaesar Wang 202cbac8f63SCaesar Wang #define TSADCV2_INT_SRC_EN(chn) BIT(chn) 203cbac8f63SCaesar Wang #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn)) 204cbac8f63SCaesar Wang #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn)) 205cbac8f63SCaesar Wang 206452e01b3SDmitry Torokhov #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8) 207952418a3SCaesar Wang #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16) 208cbac8f63SCaesar Wang 209cbac8f63SCaesar Wang #define TSADCV2_DATA_MASK 0xfff 21020f0af75SCaesar Wang #define TSADCV3_DATA_MASK 0x3ff 21120f0af75SCaesar Wang 212cbac8f63SCaesar Wang #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4 213cbac8f63SCaesar Wang #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4 21446667879SCaesar Wang #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */ 21546667879SCaesar Wang #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */ 2165ef62de7SRocky Hao #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */ 2175ef62de7SRocky Hao #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */ 21846667879SCaesar Wang 219b9484763SCaesar Wang #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */ 220b9484763SCaesar Wang 221b9484763SCaesar Wang #define GRF_SARADC_TESTBIT 0x0e644 222b9484763SCaesar Wang #define GRF_TSADC_TESTBIT_L 0x0e648 223b9484763SCaesar Wang #define GRF_TSADC_TESTBIT_H 0x0e64c 224b9484763SCaesar Wang 225b9484763SCaesar Wang #define GRF_SARADC_TESTBIT_ON (0x10001 << 2) 226b9484763SCaesar Wang #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2) 22723f75e48SRocky Hao #define GRF_TSADC_VCM_EN_L (0x10001 << 7) 22823f75e48SRocky Hao #define GRF_TSADC_VCM_EN_H (0x10001 << 7) 229cbac8f63SCaesar Wang 230678065d5SCaesar Wang /** 231678065d5SCaesar Wang * struct tsadc_table - code to temperature conversion table 232678065d5SCaesar Wang * @code: the value of adc channel 233678065d5SCaesar Wang * @temp: the temperature 234678065d5SCaesar Wang * Note: 235678065d5SCaesar Wang * code to temperature mapping of the temperature sensor is a piece wise linear 236678065d5SCaesar Wang * curve.Any temperature, code faling between to 2 give temperatures can be 237678065d5SCaesar Wang * linearly interpolated. 238678065d5SCaesar Wang * Code to Temperature mapping should be updated based on manufacturer results. 239678065d5SCaesar Wang */ 240cbac8f63SCaesar Wang struct tsadc_table { 241d9a241cbSDmitry Torokhov u32 code; 242437df217SCaesar Wang int temp; 243cbac8f63SCaesar Wang }; 244cbac8f63SCaesar Wang 245952418a3SCaesar Wang static const struct tsadc_table rk3228_code_table[] = { 2467ea38c6cSCaesar Wang {0, -40000}, 2477ea38c6cSCaesar Wang {588, -40000}, 2487ea38c6cSCaesar Wang {593, -35000}, 2497ea38c6cSCaesar Wang {598, -30000}, 2507ea38c6cSCaesar Wang {603, -25000}, 2517ea38c6cSCaesar Wang {608, -20000}, 2527ea38c6cSCaesar Wang {613, -15000}, 2537ea38c6cSCaesar Wang {618, -10000}, 2547ea38c6cSCaesar Wang {623, -5000}, 2557ea38c6cSCaesar Wang {629, 0}, 2567ea38c6cSCaesar Wang {634, 5000}, 2577ea38c6cSCaesar Wang {639, 10000}, 2587ea38c6cSCaesar Wang {644, 15000}, 2597ea38c6cSCaesar Wang {649, 20000}, 2607ea38c6cSCaesar Wang {654, 25000}, 2617ea38c6cSCaesar Wang {660, 30000}, 2627ea38c6cSCaesar Wang {665, 35000}, 2637ea38c6cSCaesar Wang {670, 40000}, 2647ea38c6cSCaesar Wang {675, 45000}, 2657ea38c6cSCaesar Wang {681, 50000}, 2667ea38c6cSCaesar Wang {686, 55000}, 2677ea38c6cSCaesar Wang {691, 60000}, 2687ea38c6cSCaesar Wang {696, 65000}, 2697ea38c6cSCaesar Wang {702, 70000}, 2707ea38c6cSCaesar Wang {707, 75000}, 2717ea38c6cSCaesar Wang {712, 80000}, 2727ea38c6cSCaesar Wang {717, 85000}, 2737ea38c6cSCaesar Wang {723, 90000}, 2747ea38c6cSCaesar Wang {728, 95000}, 2757ea38c6cSCaesar Wang {733, 100000}, 2767ea38c6cSCaesar Wang {738, 105000}, 2777ea38c6cSCaesar Wang {744, 110000}, 2787ea38c6cSCaesar Wang {749, 115000}, 2797ea38c6cSCaesar Wang {754, 120000}, 2807ea38c6cSCaesar Wang {760, 125000}, 2817ea38c6cSCaesar Wang {TSADCV2_DATA_MASK, 125000}, 2827b02a5e7SCaesar Wang }; 2837b02a5e7SCaesar Wang 284952418a3SCaesar Wang static const struct tsadc_table rk3288_code_table[] = { 285cbac8f63SCaesar Wang {TSADCV2_DATA_MASK, -40000}, 286cbac8f63SCaesar Wang {3800, -40000}, 287cbac8f63SCaesar Wang {3792, -35000}, 288cbac8f63SCaesar Wang {3783, -30000}, 289cbac8f63SCaesar Wang {3774, -25000}, 290cbac8f63SCaesar Wang {3765, -20000}, 291cbac8f63SCaesar Wang {3756, -15000}, 292cbac8f63SCaesar Wang {3747, -10000}, 293cbac8f63SCaesar Wang {3737, -5000}, 294cbac8f63SCaesar Wang {3728, 0}, 295cbac8f63SCaesar Wang {3718, 5000}, 296cbac8f63SCaesar Wang {3708, 10000}, 297cbac8f63SCaesar Wang {3698, 15000}, 298cbac8f63SCaesar Wang {3688, 20000}, 299cbac8f63SCaesar Wang {3678, 25000}, 300cbac8f63SCaesar Wang {3667, 30000}, 301cbac8f63SCaesar Wang {3656, 35000}, 302cbac8f63SCaesar Wang {3645, 40000}, 303cbac8f63SCaesar Wang {3634, 45000}, 304cbac8f63SCaesar Wang {3623, 50000}, 305cbac8f63SCaesar Wang {3611, 55000}, 306cbac8f63SCaesar Wang {3600, 60000}, 307cbac8f63SCaesar Wang {3588, 65000}, 308cbac8f63SCaesar Wang {3575, 70000}, 309cbac8f63SCaesar Wang {3563, 75000}, 310cbac8f63SCaesar Wang {3550, 80000}, 311cbac8f63SCaesar Wang {3537, 85000}, 312cbac8f63SCaesar Wang {3524, 90000}, 313cbac8f63SCaesar Wang {3510, 95000}, 314cbac8f63SCaesar Wang {3496, 100000}, 315cbac8f63SCaesar Wang {3482, 105000}, 316cbac8f63SCaesar Wang {3467, 110000}, 317cbac8f63SCaesar Wang {3452, 115000}, 318cbac8f63SCaesar Wang {3437, 120000}, 319cbac8f63SCaesar Wang {3421, 125000}, 320cbac8f63SCaesar Wang }; 321cbac8f63SCaesar Wang 322952418a3SCaesar Wang static const struct tsadc_table rk3368_code_table[] = { 32320f0af75SCaesar Wang {0, -40000}, 32420f0af75SCaesar Wang {106, -40000}, 32520f0af75SCaesar Wang {108, -35000}, 32620f0af75SCaesar Wang {110, -30000}, 32720f0af75SCaesar Wang {112, -25000}, 32820f0af75SCaesar Wang {114, -20000}, 32920f0af75SCaesar Wang {116, -15000}, 33020f0af75SCaesar Wang {118, -10000}, 33120f0af75SCaesar Wang {120, -5000}, 33220f0af75SCaesar Wang {122, 0}, 33320f0af75SCaesar Wang {124, 5000}, 33420f0af75SCaesar Wang {126, 10000}, 33520f0af75SCaesar Wang {128, 15000}, 33620f0af75SCaesar Wang {130, 20000}, 33720f0af75SCaesar Wang {132, 25000}, 33820f0af75SCaesar Wang {134, 30000}, 33920f0af75SCaesar Wang {136, 35000}, 34020f0af75SCaesar Wang {138, 40000}, 34120f0af75SCaesar Wang {140, 45000}, 34220f0af75SCaesar Wang {142, 50000}, 34320f0af75SCaesar Wang {144, 55000}, 34420f0af75SCaesar Wang {146, 60000}, 34520f0af75SCaesar Wang {148, 65000}, 34620f0af75SCaesar Wang {150, 70000}, 34720f0af75SCaesar Wang {152, 75000}, 34820f0af75SCaesar Wang {154, 80000}, 34920f0af75SCaesar Wang {156, 85000}, 35020f0af75SCaesar Wang {158, 90000}, 35120f0af75SCaesar Wang {160, 95000}, 35220f0af75SCaesar Wang {162, 100000}, 35320f0af75SCaesar Wang {163, 105000}, 35420f0af75SCaesar Wang {165, 110000}, 35520f0af75SCaesar Wang {167, 115000}, 35620f0af75SCaesar Wang {169, 120000}, 35720f0af75SCaesar Wang {171, 125000}, 35820f0af75SCaesar Wang {TSADCV3_DATA_MASK, 125000}, 35920f0af75SCaesar Wang }; 36020f0af75SCaesar Wang 361952418a3SCaesar Wang static const struct tsadc_table rk3399_code_table[] = { 3627ea38c6cSCaesar Wang {0, -40000}, 363f762a35dSCaesar Wang {402, -40000}, 364f762a35dSCaesar Wang {410, -35000}, 365f762a35dSCaesar Wang {419, -30000}, 366f762a35dSCaesar Wang {427, -25000}, 367f762a35dSCaesar Wang {436, -20000}, 368f762a35dSCaesar Wang {444, -15000}, 369f762a35dSCaesar Wang {453, -10000}, 370f762a35dSCaesar Wang {461, -5000}, 371f762a35dSCaesar Wang {470, 0}, 372f762a35dSCaesar Wang {478, 5000}, 373f762a35dSCaesar Wang {487, 10000}, 374f762a35dSCaesar Wang {496, 15000}, 375f762a35dSCaesar Wang {504, 20000}, 376f762a35dSCaesar Wang {513, 25000}, 377f762a35dSCaesar Wang {521, 30000}, 378f762a35dSCaesar Wang {530, 35000}, 379f762a35dSCaesar Wang {538, 40000}, 380f762a35dSCaesar Wang {547, 45000}, 381f762a35dSCaesar Wang {555, 50000}, 382f762a35dSCaesar Wang {564, 55000}, 383f762a35dSCaesar Wang {573, 60000}, 384f762a35dSCaesar Wang {581, 65000}, 385f762a35dSCaesar Wang {590, 70000}, 386f762a35dSCaesar Wang {599, 75000}, 387f762a35dSCaesar Wang {607, 80000}, 388f762a35dSCaesar Wang {616, 85000}, 389f762a35dSCaesar Wang {624, 90000}, 390f762a35dSCaesar Wang {633, 95000}, 391f762a35dSCaesar Wang {642, 100000}, 392f762a35dSCaesar Wang {650, 105000}, 393f762a35dSCaesar Wang {659, 110000}, 394f762a35dSCaesar Wang {668, 115000}, 395f762a35dSCaesar Wang {677, 120000}, 396f762a35dSCaesar Wang {685, 125000}, 3977ea38c6cSCaesar Wang {TSADCV3_DATA_MASK, 125000}, 398b0d70338SCaesar Wang }; 399b0d70338SCaesar Wang 400ce74110dSCaesar Wang static u32 rk_tsadcv2_temp_to_code(struct chip_tsadc_table table, 401437df217SCaesar Wang int temp) 402cbac8f63SCaesar Wang { 403cbac8f63SCaesar Wang int high, low, mid; 4041f09ba82SCaesar Wang u32 error = 0; 405cbac8f63SCaesar Wang 406cbac8f63SCaesar Wang low = 0; 407ce74110dSCaesar Wang high = table.length - 1; 408cbac8f63SCaesar Wang mid = (high + low) / 2; 409cbac8f63SCaesar Wang 4101f09ba82SCaesar Wang /* Return mask code data when the temp is over table range */ 4111f09ba82SCaesar Wang if (temp < table.id[low].temp || temp > table.id[high].temp) { 4121f09ba82SCaesar Wang error = table.data_mask; 4131f09ba82SCaesar Wang goto exit; 4141f09ba82SCaesar Wang } 415cbac8f63SCaesar Wang 416cbac8f63SCaesar Wang while (low <= high) { 417ce74110dSCaesar Wang if (temp == table.id[mid].temp) 418ce74110dSCaesar Wang return table.id[mid].code; 419ce74110dSCaesar Wang else if (temp < table.id[mid].temp) 420cbac8f63SCaesar Wang high = mid - 1; 421cbac8f63SCaesar Wang else 422cbac8f63SCaesar Wang low = mid + 1; 423cbac8f63SCaesar Wang mid = (low + high) / 2; 424cbac8f63SCaesar Wang } 425cbac8f63SCaesar Wang 4261f09ba82SCaesar Wang exit: 427e6ed1b4aSBrian Norris pr_err("%s: invalid temperature, temp=%d error=%d\n", 428e6ed1b4aSBrian Norris __func__, temp, error); 4291f09ba82SCaesar Wang return error; 430cbac8f63SCaesar Wang } 431cbac8f63SCaesar Wang 432ce74110dSCaesar Wang static int rk_tsadcv2_code_to_temp(struct chip_tsadc_table table, u32 code, 433ce74110dSCaesar Wang int *temp) 434cbac8f63SCaesar Wang { 435d9a241cbSDmitry Torokhov unsigned int low = 1; 436ce74110dSCaesar Wang unsigned int high = table.length - 1; 4371e9a1aeaSCaesar Wang unsigned int mid = (low + high) / 2; 4381e9a1aeaSCaesar Wang unsigned int num; 4391e9a1aeaSCaesar Wang unsigned long denom; 440cbac8f63SCaesar Wang 441ce74110dSCaesar Wang WARN_ON(table.length < 2); 442cbac8f63SCaesar Wang 443020ba95dSCaesar Wang switch (table.mode) { 444020ba95dSCaesar Wang case ADC_DECREMENT: 445ce74110dSCaesar Wang code &= table.data_mask; 446ce74110dSCaesar Wang if (code < table.id[high].code) 447d9a241cbSDmitry Torokhov return -EAGAIN; /* Incorrect reading */ 448d9a241cbSDmitry Torokhov 449d9a241cbSDmitry Torokhov while (low <= high) { 450ce74110dSCaesar Wang if (code >= table.id[mid].code && 451ce74110dSCaesar Wang code < table.id[mid - 1].code) 4521e9a1aeaSCaesar Wang break; 453ce74110dSCaesar Wang else if (code < table.id[mid].code) 454cbac8f63SCaesar Wang low = mid + 1; 455cbac8f63SCaesar Wang else 456cbac8f63SCaesar Wang high = mid - 1; 457020ba95dSCaesar Wang 458cbac8f63SCaesar Wang mid = (low + high) / 2; 459cbac8f63SCaesar Wang } 460020ba95dSCaesar Wang break; 461020ba95dSCaesar Wang case ADC_INCREMENT: 462020ba95dSCaesar Wang code &= table.data_mask; 463020ba95dSCaesar Wang if (code < table.id[low].code) 464020ba95dSCaesar Wang return -EAGAIN; /* Incorrect reading */ 465020ba95dSCaesar Wang 466020ba95dSCaesar Wang while (low <= high) { 467a87dd797SCaesar Wang if (code <= table.id[mid].code && 468a87dd797SCaesar Wang code > table.id[mid - 1].code) 469020ba95dSCaesar Wang break; 470020ba95dSCaesar Wang else if (code > table.id[mid].code) 471020ba95dSCaesar Wang low = mid + 1; 472020ba95dSCaesar Wang else 473020ba95dSCaesar Wang high = mid - 1; 474020ba95dSCaesar Wang 475020ba95dSCaesar Wang mid = (low + high) / 2; 476020ba95dSCaesar Wang } 477020ba95dSCaesar Wang break; 478020ba95dSCaesar Wang default: 479e6ed1b4aSBrian Norris pr_err("%s: unknown table mode: %d\n", __func__, table.mode); 480e6ed1b4aSBrian Norris return -EINVAL; 481020ba95dSCaesar Wang } 482cbac8f63SCaesar Wang 4831e9a1aeaSCaesar Wang /* 4841e9a1aeaSCaesar Wang * The 5C granularity provided by the table is too much. Let's 4851e9a1aeaSCaesar Wang * assume that the relationship between sensor readings and 4861e9a1aeaSCaesar Wang * temperature between 2 table entries is linear and interpolate 4871e9a1aeaSCaesar Wang * to produce less granular result. 4881e9a1aeaSCaesar Wang */ 4891d37a037SElaine Zhang num = table.id[mid].temp - table.id[mid - 1].temp; 490020ba95dSCaesar Wang num *= abs(table.id[mid - 1].code - code); 491020ba95dSCaesar Wang denom = abs(table.id[mid - 1].code - table.id[mid].code); 492ce74110dSCaesar Wang *temp = table.id[mid - 1].temp + (num / denom); 493d9a241cbSDmitry Torokhov 494d9a241cbSDmitry Torokhov return 0; 495cbac8f63SCaesar Wang } 496cbac8f63SCaesar Wang 497cbac8f63SCaesar Wang /** 498144c5565SCaesar Wang * rk_tsadcv2_initialize - initialize TASDC Controller. 499144c5565SCaesar Wang * 500144c5565SCaesar Wang * (1) Set TSADC_V2_AUTO_PERIOD: 501144c5565SCaesar Wang * Configure the interleave between every two accessing of 502144c5565SCaesar Wang * TSADC in normal operation. 503144c5565SCaesar Wang * 504144c5565SCaesar Wang * (2) Set TSADCV2_AUTO_PERIOD_HT: 505144c5565SCaesar Wang * Configure the interleave between every two accessing of 506144c5565SCaesar Wang * TSADC after the temperature is higher than COM_SHUT or COM_INT. 507144c5565SCaesar Wang * 508144c5565SCaesar Wang * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: 509144c5565SCaesar Wang * If the temperature is higher than COMP_INT or COMP_SHUT for 510cbac8f63SCaesar Wang * "debounce" times, TSADC controller will generate interrupt or TSHUT. 511cbac8f63SCaesar Wang */ 512b9484763SCaesar Wang static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs, 513cbac8f63SCaesar Wang enum tshut_polarity tshut_polarity) 514cbac8f63SCaesar Wang { 515cbac8f63SCaesar Wang if (tshut_polarity == TSHUT_HIGH_ACTIVE) 516452e01b3SDmitry Torokhov writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 517cbac8f63SCaesar Wang regs + TSADCV2_AUTO_CON); 518cbac8f63SCaesar Wang else 519452e01b3SDmitry Torokhov writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 520cbac8f63SCaesar Wang regs + TSADCV2_AUTO_CON); 521cbac8f63SCaesar Wang 522cbac8f63SCaesar Wang writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD); 523cbac8f63SCaesar Wang writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 524cbac8f63SCaesar Wang regs + TSADCV2_HIGHT_INT_DEBOUNCE); 525cbac8f63SCaesar Wang writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, 526cbac8f63SCaesar Wang regs + TSADCV2_AUTO_PERIOD_HT); 527cbac8f63SCaesar Wang writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 528cbac8f63SCaesar Wang regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 529b9484763SCaesar Wang } 530b9484763SCaesar Wang 531b9484763SCaesar Wang /** 532b9484763SCaesar Wang * rk_tsadcv3_initialize - initialize TASDC Controller. 533678065d5SCaesar Wang * 534b9484763SCaesar Wang * (1) The tsadc control power sequence. 535b9484763SCaesar Wang * 536b9484763SCaesar Wang * (2) Set TSADC_V2_AUTO_PERIOD: 537b9484763SCaesar Wang * Configure the interleave between every two accessing of 538b9484763SCaesar Wang * TSADC in normal operation. 539b9484763SCaesar Wang * 540b9484763SCaesar Wang * (2) Set TSADCV2_AUTO_PERIOD_HT: 541b9484763SCaesar Wang * Configure the interleave between every two accessing of 542b9484763SCaesar Wang * TSADC after the temperature is higher than COM_SHUT or COM_INT. 543b9484763SCaesar Wang * 544b9484763SCaesar Wang * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE: 545b9484763SCaesar Wang * If the temperature is higher than COMP_INT or COMP_SHUT for 546b9484763SCaesar Wang * "debounce" times, TSADC controller will generate interrupt or TSHUT. 547b9484763SCaesar Wang */ 548b9484763SCaesar Wang static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs, 549b9484763SCaesar Wang enum tshut_polarity tshut_polarity) 550b9484763SCaesar Wang { 551b9484763SCaesar Wang /* The tsadc control power sequence */ 552b9484763SCaesar Wang if (IS_ERR(grf)) { 553b9484763SCaesar Wang /* Set interleave value to workround ic time sync issue */ 554b9484763SCaesar Wang writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs + 555b9484763SCaesar Wang TSADCV2_USER_CON); 55646667879SCaesar Wang 55746667879SCaesar Wang writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, 55846667879SCaesar Wang regs + TSADCV2_AUTO_PERIOD); 55946667879SCaesar Wang writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 56046667879SCaesar Wang regs + TSADCV2_HIGHT_INT_DEBOUNCE); 56146667879SCaesar Wang writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME, 56246667879SCaesar Wang regs + TSADCV2_AUTO_PERIOD_HT); 56346667879SCaesar Wang writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 56446667879SCaesar Wang regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 56546667879SCaesar Wang 566b9484763SCaesar Wang } else { 56723f75e48SRocky Hao /* Enable the voltage common mode feature */ 56823f75e48SRocky Hao regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L); 56923f75e48SRocky Hao regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H); 57023f75e48SRocky Hao 5712fe5c1b0SCaesar Wang usleep_range(15, 100); /* The spec note says at least 15 us */ 572b9484763SCaesar Wang regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON); 573b9484763SCaesar Wang regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON); 5742fe5c1b0SCaesar Wang usleep_range(90, 200); /* The spec note says at least 90 us */ 57546667879SCaesar Wang 57646667879SCaesar Wang writel_relaxed(TSADCV3_AUTO_PERIOD_TIME, 57746667879SCaesar Wang regs + TSADCV2_AUTO_PERIOD); 57846667879SCaesar Wang writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT, 57946667879SCaesar Wang regs + TSADCV2_HIGHT_INT_DEBOUNCE); 58046667879SCaesar Wang writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME, 58146667879SCaesar Wang regs + TSADCV2_AUTO_PERIOD_HT); 58246667879SCaesar Wang writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT, 58346667879SCaesar Wang regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE); 584b9484763SCaesar Wang } 585b9484763SCaesar Wang 586b9484763SCaesar Wang if (tshut_polarity == TSHUT_HIGH_ACTIVE) 587b9484763SCaesar Wang writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 588b9484763SCaesar Wang regs + TSADCV2_AUTO_CON); 589b9484763SCaesar Wang else 590b9484763SCaesar Wang writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH, 591b9484763SCaesar Wang regs + TSADCV2_AUTO_CON); 592cbac8f63SCaesar Wang } 593cbac8f63SCaesar Wang 594cbac8f63SCaesar Wang static void rk_tsadcv2_irq_ack(void __iomem *regs) 595cbac8f63SCaesar Wang { 596cbac8f63SCaesar Wang u32 val; 597cbac8f63SCaesar Wang 598cbac8f63SCaesar Wang val = readl_relaxed(regs + TSADCV2_INT_PD); 599452e01b3SDmitry Torokhov writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); 600cbac8f63SCaesar Wang } 601cbac8f63SCaesar Wang 602952418a3SCaesar Wang static void rk_tsadcv3_irq_ack(void __iomem *regs) 603952418a3SCaesar Wang { 604952418a3SCaesar Wang u32 val; 605952418a3SCaesar Wang 606952418a3SCaesar Wang val = readl_relaxed(regs + TSADCV2_INT_PD); 607952418a3SCaesar Wang writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD); 608952418a3SCaesar Wang } 609952418a3SCaesar Wang 610cbac8f63SCaesar Wang static void rk_tsadcv2_control(void __iomem *regs, bool enable) 611cbac8f63SCaesar Wang { 612cbac8f63SCaesar Wang u32 val; 613cbac8f63SCaesar Wang 614cbac8f63SCaesar Wang val = readl_relaxed(regs + TSADCV2_AUTO_CON); 615cbac8f63SCaesar Wang if (enable) 616cbac8f63SCaesar Wang val |= TSADCV2_AUTO_EN; 617cbac8f63SCaesar Wang else 618cbac8f63SCaesar Wang val &= ~TSADCV2_AUTO_EN; 619cbac8f63SCaesar Wang 620cbac8f63SCaesar Wang writel_relaxed(val, regs + TSADCV2_AUTO_CON); 621cbac8f63SCaesar Wang } 622cbac8f63SCaesar Wang 6237ea38c6cSCaesar Wang /** 624678065d5SCaesar Wang * rk_tsadcv3_control - the tsadc controller is enabled or disabled. 625678065d5SCaesar Wang * 626678065d5SCaesar Wang * NOTE: TSADC controller works at auto mode, and some SoCs need set the 627678065d5SCaesar Wang * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output 628678065d5SCaesar Wang * adc value if setting this bit to enable. 6297ea38c6cSCaesar Wang */ 6307ea38c6cSCaesar Wang static void rk_tsadcv3_control(void __iomem *regs, bool enable) 6317ea38c6cSCaesar Wang { 6327ea38c6cSCaesar Wang u32 val; 6337ea38c6cSCaesar Wang 6347ea38c6cSCaesar Wang val = readl_relaxed(regs + TSADCV2_AUTO_CON); 6357ea38c6cSCaesar Wang if (enable) 6367ea38c6cSCaesar Wang val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN; 6377ea38c6cSCaesar Wang else 6387ea38c6cSCaesar Wang val &= ~TSADCV2_AUTO_EN; 6397ea38c6cSCaesar Wang 6407ea38c6cSCaesar Wang writel_relaxed(val, regs + TSADCV2_AUTO_CON); 6417ea38c6cSCaesar Wang } 6427ea38c6cSCaesar Wang 643ce74110dSCaesar Wang static int rk_tsadcv2_get_temp(struct chip_tsadc_table table, 644ce74110dSCaesar Wang int chn, void __iomem *regs, int *temp) 645cbac8f63SCaesar Wang { 646cbac8f63SCaesar Wang u32 val; 647cbac8f63SCaesar Wang 648cbac8f63SCaesar Wang val = readl_relaxed(regs + TSADCV2_DATA(chn)); 649cbac8f63SCaesar Wang 650ce74110dSCaesar Wang return rk_tsadcv2_code_to_temp(table, val, temp); 651cbac8f63SCaesar Wang } 652cbac8f63SCaesar Wang 65314848502SCaesar Wang static void rk_tsadcv2_alarm_temp(struct chip_tsadc_table table, 65414848502SCaesar Wang int chn, void __iomem *regs, int temp) 65514848502SCaesar Wang { 65614848502SCaesar Wang u32 alarm_value, int_en; 65714848502SCaesar Wang 6581f09ba82SCaesar Wang /* Make sure the value is valid */ 65914848502SCaesar Wang alarm_value = rk_tsadcv2_temp_to_code(table, temp); 6601f09ba82SCaesar Wang if (alarm_value == table.data_mask) 6611f09ba82SCaesar Wang return; 6621f09ba82SCaesar Wang 66314848502SCaesar Wang writel_relaxed(alarm_value & table.data_mask, 66414848502SCaesar Wang regs + TSADCV2_COMP_INT(chn)); 66514848502SCaesar Wang 66614848502SCaesar Wang int_en = readl_relaxed(regs + TSADCV2_INT_EN); 66714848502SCaesar Wang int_en |= TSADCV2_INT_SRC_EN(chn); 66814848502SCaesar Wang writel_relaxed(int_en, regs + TSADCV2_INT_EN); 66914848502SCaesar Wang } 67014848502SCaesar Wang 671ce74110dSCaesar Wang static void rk_tsadcv2_tshut_temp(struct chip_tsadc_table table, 672437df217SCaesar Wang int chn, void __iomem *regs, int temp) 673cbac8f63SCaesar Wang { 674cbac8f63SCaesar Wang u32 tshut_value, val; 675cbac8f63SCaesar Wang 6761f09ba82SCaesar Wang /* Make sure the value is valid */ 677ce74110dSCaesar Wang tshut_value = rk_tsadcv2_temp_to_code(table, temp); 6781f09ba82SCaesar Wang if (tshut_value == table.data_mask) 6791f09ba82SCaesar Wang return; 6801f09ba82SCaesar Wang 681cbac8f63SCaesar Wang writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn)); 682cbac8f63SCaesar Wang 683cbac8f63SCaesar Wang /* TSHUT will be valid */ 684cbac8f63SCaesar Wang val = readl_relaxed(regs + TSADCV2_AUTO_CON); 685cbac8f63SCaesar Wang writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON); 686cbac8f63SCaesar Wang } 687cbac8f63SCaesar Wang 688cbac8f63SCaesar Wang static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs, 689cbac8f63SCaesar Wang enum tshut_mode mode) 690cbac8f63SCaesar Wang { 691cbac8f63SCaesar Wang u32 val; 692cbac8f63SCaesar Wang 693cbac8f63SCaesar Wang val = readl_relaxed(regs + TSADCV2_INT_EN); 694cbac8f63SCaesar Wang if (mode == TSHUT_MODE_GPIO) { 695cbac8f63SCaesar Wang val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn); 696cbac8f63SCaesar Wang val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn); 697cbac8f63SCaesar Wang } else { 698cbac8f63SCaesar Wang val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn); 699cbac8f63SCaesar Wang val |= TSADCV2_SHUT_2CRU_SRC_EN(chn); 700cbac8f63SCaesar Wang } 701cbac8f63SCaesar Wang 702cbac8f63SCaesar Wang writel_relaxed(val, regs + TSADCV2_INT_EN); 703cbac8f63SCaesar Wang } 704cbac8f63SCaesar Wang 7057b02a5e7SCaesar Wang static const struct rockchip_tsadc_chip rk3228_tsadc_data = { 7067b02a5e7SCaesar Wang .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 7077b02a5e7SCaesar Wang .chn_num = 1, /* one channel for tsadc */ 7087b02a5e7SCaesar Wang 7097b02a5e7SCaesar Wang .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 7107b02a5e7SCaesar Wang .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 7117b02a5e7SCaesar Wang .tshut_temp = 95000, 7127b02a5e7SCaesar Wang 7137b02a5e7SCaesar Wang .initialize = rk_tsadcv2_initialize, 714952418a3SCaesar Wang .irq_ack = rk_tsadcv3_irq_ack, 7157ea38c6cSCaesar Wang .control = rk_tsadcv3_control, 7167b02a5e7SCaesar Wang .get_temp = rk_tsadcv2_get_temp, 71714848502SCaesar Wang .set_alarm_temp = rk_tsadcv2_alarm_temp, 7187b02a5e7SCaesar Wang .set_tshut_temp = rk_tsadcv2_tshut_temp, 7197b02a5e7SCaesar Wang .set_tshut_mode = rk_tsadcv2_tshut_mode, 7207b02a5e7SCaesar Wang 7217b02a5e7SCaesar Wang .table = { 722952418a3SCaesar Wang .id = rk3228_code_table, 723952418a3SCaesar Wang .length = ARRAY_SIZE(rk3228_code_table), 7247b02a5e7SCaesar Wang .data_mask = TSADCV3_DATA_MASK, 7257ea38c6cSCaesar Wang .mode = ADC_INCREMENT, 7267b02a5e7SCaesar Wang }, 7277b02a5e7SCaesar Wang }; 7287b02a5e7SCaesar Wang 729cbac8f63SCaesar Wang static const struct rockchip_tsadc_chip rk3288_tsadc_data = { 7301d98b618SCaesar Wang .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */ 7311d98b618SCaesar Wang .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */ 7321d98b618SCaesar Wang .chn_num = 2, /* two channels for tsadc */ 7331d98b618SCaesar Wang 734cbac8f63SCaesar Wang .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 735cbac8f63SCaesar Wang .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 736cbac8f63SCaesar Wang .tshut_temp = 95000, 737cbac8f63SCaesar Wang 738cbac8f63SCaesar Wang .initialize = rk_tsadcv2_initialize, 739cbac8f63SCaesar Wang .irq_ack = rk_tsadcv2_irq_ack, 740cbac8f63SCaesar Wang .control = rk_tsadcv2_control, 741cbac8f63SCaesar Wang .get_temp = rk_tsadcv2_get_temp, 74214848502SCaesar Wang .set_alarm_temp = rk_tsadcv2_alarm_temp, 743cbac8f63SCaesar Wang .set_tshut_temp = rk_tsadcv2_tshut_temp, 744cbac8f63SCaesar Wang .set_tshut_mode = rk_tsadcv2_tshut_mode, 745ce74110dSCaesar Wang 746ce74110dSCaesar Wang .table = { 747952418a3SCaesar Wang .id = rk3288_code_table, 748952418a3SCaesar Wang .length = ARRAY_SIZE(rk3288_code_table), 749ce74110dSCaesar Wang .data_mask = TSADCV2_DATA_MASK, 750020ba95dSCaesar Wang .mode = ADC_DECREMENT, 751ce74110dSCaesar Wang }, 752cbac8f63SCaesar Wang }; 753cbac8f63SCaesar Wang 7541cd60269SElaine Zhang static const struct rockchip_tsadc_chip rk3366_tsadc_data = { 7551cd60269SElaine Zhang .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 7561cd60269SElaine Zhang .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 7571cd60269SElaine Zhang .chn_num = 2, /* two channels for tsadc */ 7581cd60269SElaine Zhang 7591cd60269SElaine Zhang .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 7601cd60269SElaine Zhang .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 7611cd60269SElaine Zhang .tshut_temp = 95000, 7621cd60269SElaine Zhang 7631cd60269SElaine Zhang .initialize = rk_tsadcv3_initialize, 7641cd60269SElaine Zhang .irq_ack = rk_tsadcv3_irq_ack, 7651cd60269SElaine Zhang .control = rk_tsadcv3_control, 7661cd60269SElaine Zhang .get_temp = rk_tsadcv2_get_temp, 76714848502SCaesar Wang .set_alarm_temp = rk_tsadcv2_alarm_temp, 7681cd60269SElaine Zhang .set_tshut_temp = rk_tsadcv2_tshut_temp, 7691cd60269SElaine Zhang .set_tshut_mode = rk_tsadcv2_tshut_mode, 7701cd60269SElaine Zhang 7711cd60269SElaine Zhang .table = { 7721cd60269SElaine Zhang .id = rk3228_code_table, 7731cd60269SElaine Zhang .length = ARRAY_SIZE(rk3228_code_table), 7741cd60269SElaine Zhang .data_mask = TSADCV3_DATA_MASK, 7751cd60269SElaine Zhang .mode = ADC_INCREMENT, 7761cd60269SElaine Zhang }, 7771cd60269SElaine Zhang }; 7781cd60269SElaine Zhang 77920f0af75SCaesar Wang static const struct rockchip_tsadc_chip rk3368_tsadc_data = { 78020f0af75SCaesar Wang .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 78120f0af75SCaesar Wang .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 78220f0af75SCaesar Wang .chn_num = 2, /* two channels for tsadc */ 78320f0af75SCaesar Wang 78420f0af75SCaesar Wang .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 78520f0af75SCaesar Wang .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 78620f0af75SCaesar Wang .tshut_temp = 95000, 78720f0af75SCaesar Wang 78820f0af75SCaesar Wang .initialize = rk_tsadcv2_initialize, 78920f0af75SCaesar Wang .irq_ack = rk_tsadcv2_irq_ack, 79020f0af75SCaesar Wang .control = rk_tsadcv2_control, 79120f0af75SCaesar Wang .get_temp = rk_tsadcv2_get_temp, 79214848502SCaesar Wang .set_alarm_temp = rk_tsadcv2_alarm_temp, 79320f0af75SCaesar Wang .set_tshut_temp = rk_tsadcv2_tshut_temp, 79420f0af75SCaesar Wang .set_tshut_mode = rk_tsadcv2_tshut_mode, 79520f0af75SCaesar Wang 79620f0af75SCaesar Wang .table = { 797952418a3SCaesar Wang .id = rk3368_code_table, 798952418a3SCaesar Wang .length = ARRAY_SIZE(rk3368_code_table), 79920f0af75SCaesar Wang .data_mask = TSADCV3_DATA_MASK, 80020f0af75SCaesar Wang .mode = ADC_INCREMENT, 80120f0af75SCaesar Wang }, 80220f0af75SCaesar Wang }; 80320f0af75SCaesar Wang 804b0d70338SCaesar Wang static const struct rockchip_tsadc_chip rk3399_tsadc_data = { 805b0d70338SCaesar Wang .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */ 806b0d70338SCaesar Wang .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */ 807b0d70338SCaesar Wang .chn_num = 2, /* two channels for tsadc */ 808b0d70338SCaesar Wang 809b0d70338SCaesar Wang .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ 810b0d70338SCaesar Wang .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ 811b0d70338SCaesar Wang .tshut_temp = 95000, 812b0d70338SCaesar Wang 813b9484763SCaesar Wang .initialize = rk_tsadcv3_initialize, 814952418a3SCaesar Wang .irq_ack = rk_tsadcv3_irq_ack, 8157ea38c6cSCaesar Wang .control = rk_tsadcv3_control, 816b0d70338SCaesar Wang .get_temp = rk_tsadcv2_get_temp, 81714848502SCaesar Wang .set_alarm_temp = rk_tsadcv2_alarm_temp, 818b0d70338SCaesar Wang .set_tshut_temp = rk_tsadcv2_tshut_temp, 819b0d70338SCaesar Wang .set_tshut_mode = rk_tsadcv2_tshut_mode, 820b0d70338SCaesar Wang 821b0d70338SCaesar Wang .table = { 822952418a3SCaesar Wang .id = rk3399_code_table, 823952418a3SCaesar Wang .length = ARRAY_SIZE(rk3399_code_table), 824b0d70338SCaesar Wang .data_mask = TSADCV3_DATA_MASK, 8257ea38c6cSCaesar Wang .mode = ADC_INCREMENT, 826b0d70338SCaesar Wang }, 827b0d70338SCaesar Wang }; 828b0d70338SCaesar Wang 829cbac8f63SCaesar Wang static const struct of_device_id of_rockchip_thermal_match[] = { 830cbac8f63SCaesar Wang { 8317b02a5e7SCaesar Wang .compatible = "rockchip,rk3228-tsadc", 8327b02a5e7SCaesar Wang .data = (void *)&rk3228_tsadc_data, 8337b02a5e7SCaesar Wang }, 8347b02a5e7SCaesar Wang { 835cbac8f63SCaesar Wang .compatible = "rockchip,rk3288-tsadc", 836cbac8f63SCaesar Wang .data = (void *)&rk3288_tsadc_data, 837cbac8f63SCaesar Wang }, 83820f0af75SCaesar Wang { 8391cd60269SElaine Zhang .compatible = "rockchip,rk3366-tsadc", 8401cd60269SElaine Zhang .data = (void *)&rk3366_tsadc_data, 8411cd60269SElaine Zhang }, 8421cd60269SElaine Zhang { 84320f0af75SCaesar Wang .compatible = "rockchip,rk3368-tsadc", 84420f0af75SCaesar Wang .data = (void *)&rk3368_tsadc_data, 84520f0af75SCaesar Wang }, 846b0d70338SCaesar Wang { 847b0d70338SCaesar Wang .compatible = "rockchip,rk3399-tsadc", 848b0d70338SCaesar Wang .data = (void *)&rk3399_tsadc_data, 849b0d70338SCaesar Wang }, 850cbac8f63SCaesar Wang { /* end */ }, 851cbac8f63SCaesar Wang }; 852cbac8f63SCaesar Wang MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match); 853cbac8f63SCaesar Wang 854cbac8f63SCaesar Wang static void 855cbac8f63SCaesar Wang rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on) 856cbac8f63SCaesar Wang { 857cbac8f63SCaesar Wang struct thermal_zone_device *tzd = sensor->tzd; 858cbac8f63SCaesar Wang 859cbac8f63SCaesar Wang tzd->ops->set_mode(tzd, 860cbac8f63SCaesar Wang on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED); 861cbac8f63SCaesar Wang } 862cbac8f63SCaesar Wang 863cbac8f63SCaesar Wang static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev) 864cbac8f63SCaesar Wang { 865cbac8f63SCaesar Wang struct rockchip_thermal_data *thermal = dev; 866cbac8f63SCaesar Wang int i; 867cbac8f63SCaesar Wang 868cbac8f63SCaesar Wang dev_dbg(&thermal->pdev->dev, "thermal alarm\n"); 869cbac8f63SCaesar Wang 870cbac8f63SCaesar Wang thermal->chip->irq_ack(thermal->regs); 871cbac8f63SCaesar Wang 8721d98b618SCaesar Wang for (i = 0; i < thermal->chip->chn_num; i++) 8730e70f466SSrinivas Pandruvada thermal_zone_device_update(thermal->sensors[i].tzd, 8740e70f466SSrinivas Pandruvada THERMAL_EVENT_UNSPECIFIED); 875cbac8f63SCaesar Wang 876cbac8f63SCaesar Wang return IRQ_HANDLED; 877cbac8f63SCaesar Wang } 878cbac8f63SCaesar Wang 87914848502SCaesar Wang static int rockchip_thermal_set_trips(void *_sensor, int low, int high) 88014848502SCaesar Wang { 88114848502SCaesar Wang struct rockchip_thermal_sensor *sensor = _sensor; 88214848502SCaesar Wang struct rockchip_thermal_data *thermal = sensor->thermal; 88314848502SCaesar Wang const struct rockchip_tsadc_chip *tsadc = thermal->chip; 88414848502SCaesar Wang 88514848502SCaesar Wang dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n", 88614848502SCaesar Wang __func__, sensor->id, low, high); 88714848502SCaesar Wang 88814848502SCaesar Wang tsadc->set_alarm_temp(tsadc->table, 88914848502SCaesar Wang sensor->id, thermal->regs, high); 89014848502SCaesar Wang 89114848502SCaesar Wang return 0; 89214848502SCaesar Wang } 89314848502SCaesar Wang 89417e8351aSSascha Hauer static int rockchip_thermal_get_temp(void *_sensor, int *out_temp) 895cbac8f63SCaesar Wang { 896cbac8f63SCaesar Wang struct rockchip_thermal_sensor *sensor = _sensor; 897cbac8f63SCaesar Wang struct rockchip_thermal_data *thermal = sensor->thermal; 898cbac8f63SCaesar Wang const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip; 899cbac8f63SCaesar Wang int retval; 900cbac8f63SCaesar Wang 901ce74110dSCaesar Wang retval = tsadc->get_temp(tsadc->table, 902ce74110dSCaesar Wang sensor->id, thermal->regs, out_temp); 90317e8351aSSascha Hauer dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n", 904cbac8f63SCaesar Wang sensor->id, *out_temp, retval); 905cbac8f63SCaesar Wang 906cbac8f63SCaesar Wang return retval; 907cbac8f63SCaesar Wang } 908cbac8f63SCaesar Wang 909cbac8f63SCaesar Wang static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = { 910cbac8f63SCaesar Wang .get_temp = rockchip_thermal_get_temp, 91114848502SCaesar Wang .set_trips = rockchip_thermal_set_trips, 912cbac8f63SCaesar Wang }; 913cbac8f63SCaesar Wang 914cbac8f63SCaesar Wang static int rockchip_configure_from_dt(struct device *dev, 915cbac8f63SCaesar Wang struct device_node *np, 916cbac8f63SCaesar Wang struct rockchip_thermal_data *thermal) 917cbac8f63SCaesar Wang { 918cbac8f63SCaesar Wang u32 shut_temp, tshut_mode, tshut_polarity; 919cbac8f63SCaesar Wang 920cbac8f63SCaesar Wang if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) { 921cbac8f63SCaesar Wang dev_warn(dev, 922437df217SCaesar Wang "Missing tshut temp property, using default %d\n", 923cbac8f63SCaesar Wang thermal->chip->tshut_temp); 924cbac8f63SCaesar Wang thermal->tshut_temp = thermal->chip->tshut_temp; 925cbac8f63SCaesar Wang } else { 92643b4eb9fSCaesar Wang if (shut_temp > INT_MAX) { 927437df217SCaesar Wang dev_err(dev, "Invalid tshut temperature specified: %d\n", 92843b4eb9fSCaesar Wang shut_temp); 929cbac8f63SCaesar Wang return -ERANGE; 930cbac8f63SCaesar Wang } 93143b4eb9fSCaesar Wang thermal->tshut_temp = shut_temp; 93243b4eb9fSCaesar Wang } 933cbac8f63SCaesar Wang 934cbac8f63SCaesar Wang if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) { 935cbac8f63SCaesar Wang dev_warn(dev, 936cbac8f63SCaesar Wang "Missing tshut mode property, using default (%s)\n", 937cbac8f63SCaesar Wang thermal->chip->tshut_mode == TSHUT_MODE_GPIO ? 938cbac8f63SCaesar Wang "gpio" : "cru"); 939cbac8f63SCaesar Wang thermal->tshut_mode = thermal->chip->tshut_mode; 940cbac8f63SCaesar Wang } else { 941cbac8f63SCaesar Wang thermal->tshut_mode = tshut_mode; 942cbac8f63SCaesar Wang } 943cbac8f63SCaesar Wang 944cbac8f63SCaesar Wang if (thermal->tshut_mode > 1) { 945cbac8f63SCaesar Wang dev_err(dev, "Invalid tshut mode specified: %d\n", 946cbac8f63SCaesar Wang thermal->tshut_mode); 947cbac8f63SCaesar Wang return -EINVAL; 948cbac8f63SCaesar Wang } 949cbac8f63SCaesar Wang 950cbac8f63SCaesar Wang if (of_property_read_u32(np, "rockchip,hw-tshut-polarity", 951cbac8f63SCaesar Wang &tshut_polarity)) { 952cbac8f63SCaesar Wang dev_warn(dev, 953cbac8f63SCaesar Wang "Missing tshut-polarity property, using default (%s)\n", 954cbac8f63SCaesar Wang thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ? 955cbac8f63SCaesar Wang "low" : "high"); 956cbac8f63SCaesar Wang thermal->tshut_polarity = thermal->chip->tshut_polarity; 957cbac8f63SCaesar Wang } else { 958cbac8f63SCaesar Wang thermal->tshut_polarity = tshut_polarity; 959cbac8f63SCaesar Wang } 960cbac8f63SCaesar Wang 961cbac8f63SCaesar Wang if (thermal->tshut_polarity > 1) { 962cbac8f63SCaesar Wang dev_err(dev, "Invalid tshut-polarity specified: %d\n", 963cbac8f63SCaesar Wang thermal->tshut_polarity); 964cbac8f63SCaesar Wang return -EINVAL; 965cbac8f63SCaesar Wang } 966cbac8f63SCaesar Wang 967b9484763SCaesar Wang /* The tsadc wont to handle the error in here since some SoCs didn't 968b9484763SCaesar Wang * need this property. 969b9484763SCaesar Wang */ 970b9484763SCaesar Wang thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); 971ce62abaeSShawn Lin if (IS_ERR(thermal->grf)) 972ce62abaeSShawn Lin dev_warn(dev, "Missing rockchip,grf property\n"); 973b9484763SCaesar Wang 974cbac8f63SCaesar Wang return 0; 975cbac8f63SCaesar Wang } 976cbac8f63SCaesar Wang 977cbac8f63SCaesar Wang static int 978cbac8f63SCaesar Wang rockchip_thermal_register_sensor(struct platform_device *pdev, 979cbac8f63SCaesar Wang struct rockchip_thermal_data *thermal, 980cbac8f63SCaesar Wang struct rockchip_thermal_sensor *sensor, 9811d98b618SCaesar Wang int id) 982cbac8f63SCaesar Wang { 983cbac8f63SCaesar Wang const struct rockchip_tsadc_chip *tsadc = thermal->chip; 984cbac8f63SCaesar Wang int error; 985cbac8f63SCaesar Wang 986cbac8f63SCaesar Wang tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode); 987ce74110dSCaesar Wang tsadc->set_tshut_temp(tsadc->table, id, thermal->regs, 988ce74110dSCaesar Wang thermal->tshut_temp); 989cbac8f63SCaesar Wang 990cbac8f63SCaesar Wang sensor->thermal = thermal; 991cbac8f63SCaesar Wang sensor->id = id; 9922633ad19SEduardo Valentin sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id, 9932633ad19SEduardo Valentin sensor, &rockchip_of_thermal_ops); 994cbac8f63SCaesar Wang if (IS_ERR(sensor->tzd)) { 995cbac8f63SCaesar Wang error = PTR_ERR(sensor->tzd); 996cbac8f63SCaesar Wang dev_err(&pdev->dev, "failed to register sensor %d: %d\n", 997cbac8f63SCaesar Wang id, error); 998cbac8f63SCaesar Wang return error; 999cbac8f63SCaesar Wang } 1000cbac8f63SCaesar Wang 1001cbac8f63SCaesar Wang return 0; 1002cbac8f63SCaesar Wang } 1003cbac8f63SCaesar Wang 100413c1cfdaSCaesar Wang /** 1005cbac8f63SCaesar Wang * Reset TSADC Controller, reset all tsadc registers. 1006cbac8f63SCaesar Wang */ 1007cbac8f63SCaesar Wang static void rockchip_thermal_reset_controller(struct reset_control *reset) 1008cbac8f63SCaesar Wang { 1009cbac8f63SCaesar Wang reset_control_assert(reset); 1010cbac8f63SCaesar Wang usleep_range(10, 20); 1011cbac8f63SCaesar Wang reset_control_deassert(reset); 1012cbac8f63SCaesar Wang } 1013cbac8f63SCaesar Wang 1014cbac8f63SCaesar Wang static int rockchip_thermal_probe(struct platform_device *pdev) 1015cbac8f63SCaesar Wang { 1016cbac8f63SCaesar Wang struct device_node *np = pdev->dev.of_node; 1017cbac8f63SCaesar Wang struct rockchip_thermal_data *thermal; 1018cbac8f63SCaesar Wang const struct of_device_id *match; 1019cbac8f63SCaesar Wang struct resource *res; 1020cbac8f63SCaesar Wang int irq; 10212633ad19SEduardo Valentin int i; 1022cbac8f63SCaesar Wang int error; 1023cbac8f63SCaesar Wang 1024cbac8f63SCaesar Wang match = of_match_node(of_rockchip_thermal_match, np); 1025cbac8f63SCaesar Wang if (!match) 1026cbac8f63SCaesar Wang return -ENXIO; 1027cbac8f63SCaesar Wang 1028cbac8f63SCaesar Wang irq = platform_get_irq(pdev, 0); 1029cbac8f63SCaesar Wang if (irq < 0) { 1030cbac8f63SCaesar Wang dev_err(&pdev->dev, "no irq resource?\n"); 1031cbac8f63SCaesar Wang return -EINVAL; 1032cbac8f63SCaesar Wang } 1033cbac8f63SCaesar Wang 1034cbac8f63SCaesar Wang thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data), 1035cbac8f63SCaesar Wang GFP_KERNEL); 1036cbac8f63SCaesar Wang if (!thermal) 1037cbac8f63SCaesar Wang return -ENOMEM; 1038cbac8f63SCaesar Wang 1039cbac8f63SCaesar Wang thermal->pdev = pdev; 1040cbac8f63SCaesar Wang 1041cbac8f63SCaesar Wang thermal->chip = (const struct rockchip_tsadc_chip *)match->data; 1042cbac8f63SCaesar Wang if (!thermal->chip) 1043cbac8f63SCaesar Wang return -EINVAL; 1044cbac8f63SCaesar Wang 1045cbac8f63SCaesar Wang res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1046cbac8f63SCaesar Wang thermal->regs = devm_ioremap_resource(&pdev->dev, res); 1047cbac8f63SCaesar Wang if (IS_ERR(thermal->regs)) 1048cbac8f63SCaesar Wang return PTR_ERR(thermal->regs); 1049cbac8f63SCaesar Wang 1050cbac8f63SCaesar Wang thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb"); 1051cbac8f63SCaesar Wang if (IS_ERR(thermal->reset)) { 1052cbac8f63SCaesar Wang error = PTR_ERR(thermal->reset); 1053cbac8f63SCaesar Wang dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error); 1054cbac8f63SCaesar Wang return error; 1055cbac8f63SCaesar Wang } 1056cbac8f63SCaesar Wang 1057cbac8f63SCaesar Wang thermal->clk = devm_clk_get(&pdev->dev, "tsadc"); 1058cbac8f63SCaesar Wang if (IS_ERR(thermal->clk)) { 1059cbac8f63SCaesar Wang error = PTR_ERR(thermal->clk); 1060cbac8f63SCaesar Wang dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error); 1061cbac8f63SCaesar Wang return error; 1062cbac8f63SCaesar Wang } 1063cbac8f63SCaesar Wang 1064cbac8f63SCaesar Wang thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk"); 1065cbac8f63SCaesar Wang if (IS_ERR(thermal->pclk)) { 10660d0a2bf6SDan Carpenter error = PTR_ERR(thermal->pclk); 1067cbac8f63SCaesar Wang dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n", 1068cbac8f63SCaesar Wang error); 1069cbac8f63SCaesar Wang return error; 1070cbac8f63SCaesar Wang } 1071cbac8f63SCaesar Wang 1072cbac8f63SCaesar Wang error = clk_prepare_enable(thermal->clk); 1073cbac8f63SCaesar Wang if (error) { 1074cbac8f63SCaesar Wang dev_err(&pdev->dev, "failed to enable converter clock: %d\n", 1075cbac8f63SCaesar Wang error); 1076cbac8f63SCaesar Wang return error; 1077cbac8f63SCaesar Wang } 1078cbac8f63SCaesar Wang 1079cbac8f63SCaesar Wang error = clk_prepare_enable(thermal->pclk); 1080cbac8f63SCaesar Wang if (error) { 1081cbac8f63SCaesar Wang dev_err(&pdev->dev, "failed to enable pclk: %d\n", error); 1082cbac8f63SCaesar Wang goto err_disable_clk; 1083cbac8f63SCaesar Wang } 1084cbac8f63SCaesar Wang 1085cbac8f63SCaesar Wang rockchip_thermal_reset_controller(thermal->reset); 1086cbac8f63SCaesar Wang 1087cbac8f63SCaesar Wang error = rockchip_configure_from_dt(&pdev->dev, np, thermal); 1088cbac8f63SCaesar Wang if (error) { 1089cbac8f63SCaesar Wang dev_err(&pdev->dev, "failed to parse device tree data: %d\n", 1090cbac8f63SCaesar Wang error); 1091cbac8f63SCaesar Wang goto err_disable_pclk; 1092cbac8f63SCaesar Wang } 1093cbac8f63SCaesar Wang 1094b9484763SCaesar Wang thermal->chip->initialize(thermal->grf, thermal->regs, 1095b9484763SCaesar Wang thermal->tshut_polarity); 1096cbac8f63SCaesar Wang 10971d98b618SCaesar Wang for (i = 0; i < thermal->chip->chn_num; i++) { 1098cbac8f63SCaesar Wang error = rockchip_thermal_register_sensor(pdev, thermal, 10991d98b618SCaesar Wang &thermal->sensors[i], 11001d98b618SCaesar Wang thermal->chip->chn_id[i]); 1101cbac8f63SCaesar Wang if (error) { 1102cbac8f63SCaesar Wang dev_err(&pdev->dev, 11031d98b618SCaesar Wang "failed to register sensor[%d] : error = %d\n", 11041d98b618SCaesar Wang i, error); 1105cbac8f63SCaesar Wang goto err_disable_pclk; 1106cbac8f63SCaesar Wang } 1107cbac8f63SCaesar Wang } 1108cbac8f63SCaesar Wang 1109cbac8f63SCaesar Wang error = devm_request_threaded_irq(&pdev->dev, irq, NULL, 1110cbac8f63SCaesar Wang &rockchip_thermal_alarm_irq_thread, 1111cbac8f63SCaesar Wang IRQF_ONESHOT, 1112cbac8f63SCaesar Wang "rockchip_thermal", thermal); 1113cbac8f63SCaesar Wang if (error) { 1114cbac8f63SCaesar Wang dev_err(&pdev->dev, 1115cbac8f63SCaesar Wang "failed to request tsadc irq: %d\n", error); 11162633ad19SEduardo Valentin goto err_disable_pclk; 1117cbac8f63SCaesar Wang } 1118cbac8f63SCaesar Wang 1119cbac8f63SCaesar Wang thermal->chip->control(thermal->regs, true); 1120cbac8f63SCaesar Wang 11211d98b618SCaesar Wang for (i = 0; i < thermal->chip->chn_num; i++) 1122cbac8f63SCaesar Wang rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); 1123cbac8f63SCaesar Wang 1124cbac8f63SCaesar Wang platform_set_drvdata(pdev, thermal); 1125cbac8f63SCaesar Wang 1126cbac8f63SCaesar Wang return 0; 1127cbac8f63SCaesar Wang 1128cbac8f63SCaesar Wang err_disable_pclk: 1129cbac8f63SCaesar Wang clk_disable_unprepare(thermal->pclk); 1130cbac8f63SCaesar Wang err_disable_clk: 1131cbac8f63SCaesar Wang clk_disable_unprepare(thermal->clk); 1132cbac8f63SCaesar Wang 1133cbac8f63SCaesar Wang return error; 1134cbac8f63SCaesar Wang } 1135cbac8f63SCaesar Wang 1136cbac8f63SCaesar Wang static int rockchip_thermal_remove(struct platform_device *pdev) 1137cbac8f63SCaesar Wang { 1138cbac8f63SCaesar Wang struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); 1139cbac8f63SCaesar Wang int i; 1140cbac8f63SCaesar Wang 11411d98b618SCaesar Wang for (i = 0; i < thermal->chip->chn_num; i++) { 1142cbac8f63SCaesar Wang struct rockchip_thermal_sensor *sensor = &thermal->sensors[i]; 1143cbac8f63SCaesar Wang 1144cbac8f63SCaesar Wang rockchip_thermal_toggle_sensor(sensor, false); 1145cbac8f63SCaesar Wang } 1146cbac8f63SCaesar Wang 1147cbac8f63SCaesar Wang thermal->chip->control(thermal->regs, false); 1148cbac8f63SCaesar Wang 1149cbac8f63SCaesar Wang clk_disable_unprepare(thermal->pclk); 1150cbac8f63SCaesar Wang clk_disable_unprepare(thermal->clk); 1151cbac8f63SCaesar Wang 1152cbac8f63SCaesar Wang return 0; 1153cbac8f63SCaesar Wang } 1154cbac8f63SCaesar Wang 1155cbac8f63SCaesar Wang static int __maybe_unused rockchip_thermal_suspend(struct device *dev) 1156cbac8f63SCaesar Wang { 1157cbac8f63SCaesar Wang struct platform_device *pdev = to_platform_device(dev); 1158cbac8f63SCaesar Wang struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); 1159cbac8f63SCaesar Wang int i; 1160cbac8f63SCaesar Wang 11611d98b618SCaesar Wang for (i = 0; i < thermal->chip->chn_num; i++) 1162cbac8f63SCaesar Wang rockchip_thermal_toggle_sensor(&thermal->sensors[i], false); 1163cbac8f63SCaesar Wang 1164cbac8f63SCaesar Wang thermal->chip->control(thermal->regs, false); 1165cbac8f63SCaesar Wang 1166cbac8f63SCaesar Wang clk_disable(thermal->pclk); 1167cbac8f63SCaesar Wang clk_disable(thermal->clk); 1168cbac8f63SCaesar Wang 11697e38a5b1SCaesar Wang pinctrl_pm_select_sleep_state(dev); 11707e38a5b1SCaesar Wang 1171cbac8f63SCaesar Wang return 0; 1172cbac8f63SCaesar Wang } 1173cbac8f63SCaesar Wang 1174cbac8f63SCaesar Wang static int __maybe_unused rockchip_thermal_resume(struct device *dev) 1175cbac8f63SCaesar Wang { 1176cbac8f63SCaesar Wang struct platform_device *pdev = to_platform_device(dev); 1177cbac8f63SCaesar Wang struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev); 1178cbac8f63SCaesar Wang int i; 1179cbac8f63SCaesar Wang int error; 1180cbac8f63SCaesar Wang 1181cbac8f63SCaesar Wang error = clk_enable(thermal->clk); 1182cbac8f63SCaesar Wang if (error) 1183cbac8f63SCaesar Wang return error; 1184cbac8f63SCaesar Wang 1185cbac8f63SCaesar Wang error = clk_enable(thermal->pclk); 1186ab5b52f1SShawn Lin if (error) { 1187ab5b52f1SShawn Lin clk_disable(thermal->clk); 1188cbac8f63SCaesar Wang return error; 1189ab5b52f1SShawn Lin } 1190cbac8f63SCaesar Wang 1191cbac8f63SCaesar Wang rockchip_thermal_reset_controller(thermal->reset); 1192cbac8f63SCaesar Wang 1193b9484763SCaesar Wang thermal->chip->initialize(thermal->grf, thermal->regs, 1194b9484763SCaesar Wang thermal->tshut_polarity); 1195cbac8f63SCaesar Wang 11961d98b618SCaesar Wang for (i = 0; i < thermal->chip->chn_num; i++) { 11971d98b618SCaesar Wang int id = thermal->sensors[i].id; 1198cbac8f63SCaesar Wang 1199cbac8f63SCaesar Wang thermal->chip->set_tshut_mode(id, thermal->regs, 1200cbac8f63SCaesar Wang thermal->tshut_mode); 1201ce74110dSCaesar Wang thermal->chip->set_tshut_temp(thermal->chip->table, 1202ce74110dSCaesar Wang id, thermal->regs, 1203cbac8f63SCaesar Wang thermal->tshut_temp); 1204cbac8f63SCaesar Wang } 1205cbac8f63SCaesar Wang 1206cbac8f63SCaesar Wang thermal->chip->control(thermal->regs, true); 1207cbac8f63SCaesar Wang 12081d98b618SCaesar Wang for (i = 0; i < thermal->chip->chn_num; i++) 1209cbac8f63SCaesar Wang rockchip_thermal_toggle_sensor(&thermal->sensors[i], true); 1210cbac8f63SCaesar Wang 12117e38a5b1SCaesar Wang pinctrl_pm_select_default_state(dev); 12127e38a5b1SCaesar Wang 1213cbac8f63SCaesar Wang return 0; 1214cbac8f63SCaesar Wang } 1215cbac8f63SCaesar Wang 1216cbac8f63SCaesar Wang static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops, 1217cbac8f63SCaesar Wang rockchip_thermal_suspend, rockchip_thermal_resume); 1218cbac8f63SCaesar Wang 1219cbac8f63SCaesar Wang static struct platform_driver rockchip_thermal_driver = { 1220cbac8f63SCaesar Wang .driver = { 1221cbac8f63SCaesar Wang .name = "rockchip-thermal", 1222cbac8f63SCaesar Wang .pm = &rockchip_thermal_pm_ops, 1223cbac8f63SCaesar Wang .of_match_table = of_rockchip_thermal_match, 1224cbac8f63SCaesar Wang }, 1225cbac8f63SCaesar Wang .probe = rockchip_thermal_probe, 1226cbac8f63SCaesar Wang .remove = rockchip_thermal_remove, 1227cbac8f63SCaesar Wang }; 1228cbac8f63SCaesar Wang 1229cbac8f63SCaesar Wang module_platform_driver(rockchip_thermal_driver); 1230cbac8f63SCaesar Wang 1231cbac8f63SCaesar Wang MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver"); 1232cbac8f63SCaesar Wang MODULE_AUTHOR("Rockchip, Inc."); 1233cbac8f63SCaesar Wang MODULE_LICENSE("GPL v2"); 1234cbac8f63SCaesar Wang MODULE_ALIAS("platform:rockchip-thermal"); 1235