1 // SPDX-License-Identifier: GPL-2.0
2 //
3 // Copyright 2016 Freescale Semiconductor, Inc.
4 
5 #include <linux/clk.h>
6 #include <linux/module.h>
7 #include <linux/platform_device.h>
8 #include <linux/err.h>
9 #include <linux/io.h>
10 #include <linux/of.h>
11 #include <linux/of_address.h>
12 #include <linux/thermal.h>
13 
14 #include "thermal_core.h"
15 
16 #define SITES_MAX		16
17 #define TMR_DISABLE		0x0
18 #define TMR_ME			0x80000000
19 #define TMR_ALPF		0x0c000000
20 #define TMR_ALPF_V2		0x03000000
21 #define TMTMIR_DEFAULT	0x0000000f
22 #define TIER_DISABLE	0x0
23 #define TEUMR0_V2		0x51009c00
24 #define TMU_VER1		0x1
25 #define TMU_VER2		0x2
26 
27 /*
28  * QorIQ TMU Registers
29  */
30 struct qoriq_tmu_site_regs {
31 	u32 tritsr;		/* Immediate Temperature Site Register */
32 	u32 tratsr;		/* Average Temperature Site Register */
33 	u8 res0[0x8];
34 };
35 
36 struct qoriq_tmu_regs_v1 {
37 	u32 tmr;		/* Mode Register */
38 	u32 tsr;		/* Status Register */
39 	u32 tmtmir;		/* Temperature measurement interval Register */
40 	u8 res0[0x14];
41 	u32 tier;		/* Interrupt Enable Register */
42 	u32 tidr;		/* Interrupt Detect Register */
43 	u32 tiscr;		/* Interrupt Site Capture Register */
44 	u32 ticscr;		/* Interrupt Critical Site Capture Register */
45 	u8 res1[0x10];
46 	u32 tmhtcrh;		/* High Temperature Capture Register */
47 	u32 tmhtcrl;		/* Low Temperature Capture Register */
48 	u8 res2[0x8];
49 	u32 tmhtitr;		/* High Temperature Immediate Threshold */
50 	u32 tmhtatr;		/* High Temperature Average Threshold */
51 	u32 tmhtactr;	/* High Temperature Average Crit Threshold */
52 	u8 res3[0x24];
53 	u32 ttcfgr;		/* Temperature Configuration Register */
54 	u32 tscfgr;		/* Sensor Configuration Register */
55 	u8 res4[0x78];
56 	struct qoriq_tmu_site_regs site[SITES_MAX];
57 	u8 res5[0x9f8];
58 	u32 ipbrr0;		/* IP Block Revision Register 0 */
59 	u32 ipbrr1;		/* IP Block Revision Register 1 */
60 	u8 res6[0x310];
61 	u32 ttrcr[4];		/* Temperature Range Control Register */
62 };
63 
64 struct qoriq_tmu_regs_v2 {
65 	u32 tmr;		/* Mode Register */
66 	u32 tsr;		/* Status Register */
67 	u32 tmsr;		/* monitor site register */
68 	u32 tmtmir;		/* Temperature measurement interval Register */
69 	u8 res0[0x10];
70 	u32 tier;		/* Interrupt Enable Register */
71 	u32 tidr;		/* Interrupt Detect Register */
72 	u8 res1[0x8];
73 	u32 tiiscr;		/* interrupt immediate site capture register */
74 	u32 tiascr;		/* interrupt average site capture register */
75 	u32 ticscr;		/* Interrupt Critical Site Capture Register */
76 	u32 res2;
77 	u32 tmhtcr;		/* monitor high temperature capture register */
78 	u32 tmltcr;		/* monitor low temperature capture register */
79 	u32 tmrtrcr;	/* monitor rising temperature rate capture register */
80 	u32 tmftrcr;	/* monitor falling temperature rate capture register */
81 	u32 tmhtitr;	/* High Temperature Immediate Threshold */
82 	u32 tmhtatr;	/* High Temperature Average Threshold */
83 	u32 tmhtactr;	/* High Temperature Average Crit Threshold */
84 	u32 res3;
85 	u32 tmltitr;	/* monitor low temperature immediate threshold */
86 	u32 tmltatr;	/* monitor low temperature average threshold register */
87 	u32 tmltactr;	/* monitor low temperature average critical threshold */
88 	u32 res4;
89 	u32 tmrtrctr;	/* monitor rising temperature rate critical threshold */
90 	u32 tmftrctr;	/* monitor falling temperature rate critical threshold*/
91 	u8 res5[0x8];
92 	u32 ttcfgr;	/* Temperature Configuration Register */
93 	u32 tscfgr;	/* Sensor Configuration Register */
94 	u8 res6[0x78];
95 	struct qoriq_tmu_site_regs site[SITES_MAX];
96 	u8 res7[0x9f8];
97 	u32 ipbrr0;		/* IP Block Revision Register 0 */
98 	u32 ipbrr1;		/* IP Block Revision Register 1 */
99 	u8 res8[0x300];
100 	u32 teumr0;
101 	u32 teumr1;
102 	u32 teumr2;
103 	u32 res9;
104 	u32 ttrcr[4];	/* Temperature Range Control Register */
105 };
106 
107 struct qoriq_tmu_data;
108 
109 /*
110  * Thermal zone data
111  */
112 struct qoriq_sensor {
113 	struct thermal_zone_device	*tzd;
114 	struct qoriq_tmu_data		*qdata;
115 	int				id;
116 };
117 
118 struct qoriq_tmu_data {
119 	int ver;
120 	struct qoriq_tmu_regs_v1 __iomem *regs;
121 	struct qoriq_tmu_regs_v2 __iomem *regs_v2;
122 	struct clk *clk;
123 	bool little_endian;
124 	struct qoriq_sensor	*sensor[SITES_MAX];
125 };
126 
127 static void tmu_write(struct qoriq_tmu_data *p, u32 val, void __iomem *addr)
128 {
129 	if (p->little_endian)
130 		iowrite32(val, addr);
131 	else
132 		iowrite32be(val, addr);
133 }
134 
135 static u32 tmu_read(struct qoriq_tmu_data *p, void __iomem *addr)
136 {
137 	if (p->little_endian)
138 		return ioread32(addr);
139 	else
140 		return ioread32be(addr);
141 }
142 
143 static int tmu_get_temp(void *p, int *temp)
144 {
145 	struct qoriq_sensor *qsensor = p;
146 	struct qoriq_tmu_data *qdata = qsensor->qdata;
147 	u32 val;
148 
149 	val = tmu_read(qdata, &qdata->regs->site[qsensor->id].tritsr);
150 	*temp = (val & 0xff) * 1000;
151 
152 	return 0;
153 }
154 
155 static const struct thermal_zone_of_device_ops tmu_tz_ops = {
156 	.get_temp = tmu_get_temp,
157 };
158 
159 static int qoriq_tmu_register_tmu_zone(struct platform_device *pdev)
160 {
161 	struct qoriq_tmu_data *qdata = platform_get_drvdata(pdev);
162 	int id, sites = 0;
163 
164 	for (id = 0; id < SITES_MAX; id++) {
165 		qdata->sensor[id] = devm_kzalloc(&pdev->dev,
166 				sizeof(struct qoriq_sensor), GFP_KERNEL);
167 		if (!qdata->sensor[id])
168 			return -ENOMEM;
169 
170 		qdata->sensor[id]->id = id;
171 		qdata->sensor[id]->qdata = qdata;
172 		qdata->sensor[id]->tzd = devm_thermal_zone_of_sensor_register(
173 				&pdev->dev, id, qdata->sensor[id], &tmu_tz_ops);
174 		if (IS_ERR(qdata->sensor[id]->tzd)) {
175 			if (PTR_ERR(qdata->sensor[id]->tzd) == -ENODEV)
176 				continue;
177 			else
178 				return PTR_ERR(qdata->sensor[id]->tzd);
179 		}
180 
181 		if (qdata->ver == TMU_VER1)
182 			sites |= 0x1 << (15 - id);
183 		else
184 			sites |= 0x1 << id;
185 	}
186 
187 	/* Enable monitoring */
188 	if (sites != 0) {
189 		if (qdata->ver == TMU_VER1) {
190 			tmu_write(qdata, sites | TMR_ME | TMR_ALPF,
191 					&qdata->regs->tmr);
192 		} else {
193 			tmu_write(qdata, sites, &qdata->regs_v2->tmsr);
194 			tmu_write(qdata, TMR_ME | TMR_ALPF_V2,
195 					&qdata->regs_v2->tmr);
196 		}
197 	}
198 
199 	return 0;
200 }
201 
202 static int qoriq_tmu_calibration(struct platform_device *pdev)
203 {
204 	int i, val, len;
205 	u32 range[4];
206 	const u32 *calibration;
207 	struct device_node *np = pdev->dev.of_node;
208 	struct qoriq_tmu_data *data = platform_get_drvdata(pdev);
209 
210 	len = of_property_count_u32_elems(np, "fsl,tmu-range");
211 	if (len < 0 || len > 4) {
212 		dev_err(&pdev->dev, "invalid range data.\n");
213 		return len;
214 	}
215 
216 	val = of_property_read_u32_array(np, "fsl,tmu-range", range, len);
217 	if (val != 0) {
218 		dev_err(&pdev->dev, "failed to read range data.\n");
219 		return val;
220 	}
221 
222 	/* Init temperature range registers */
223 	for (i = 0; i < len; i++)
224 		tmu_write(data, range[i], &data->regs->ttrcr[i]);
225 
226 	calibration = of_get_property(np, "fsl,tmu-calibration", &len);
227 	if (calibration == NULL || len % 8) {
228 		dev_err(&pdev->dev, "invalid calibration data.\n");
229 		return -ENODEV;
230 	}
231 
232 	for (i = 0; i < len; i += 8, calibration += 2) {
233 		val = of_read_number(calibration, 1);
234 		tmu_write(data, val, &data->regs->ttcfgr);
235 		val = of_read_number(calibration + 1, 1);
236 		tmu_write(data, val, &data->regs->tscfgr);
237 	}
238 
239 	return 0;
240 }
241 
242 static void qoriq_tmu_init_device(struct qoriq_tmu_data *data)
243 {
244 	/* Disable interrupt, using polling instead */
245 	tmu_write(data, TIER_DISABLE, &data->regs->tier);
246 
247 	/* Set update_interval */
248 	if (data->ver == TMU_VER1) {
249 		tmu_write(data, TMTMIR_DEFAULT, &data->regs->tmtmir);
250 	} else {
251 		tmu_write(data, TMTMIR_DEFAULT, &data->regs_v2->tmtmir);
252 		tmu_write(data, TEUMR0_V2, &data->regs_v2->teumr0);
253 	}
254 
255 	/* Disable monitoring */
256 	tmu_write(data, TMR_DISABLE, &data->regs->tmr);
257 }
258 
259 static int qoriq_tmu_probe(struct platform_device *pdev)
260 {
261 	int ret;
262 	u32 ver;
263 	struct qoriq_tmu_data *data;
264 	struct device_node *np = pdev->dev.of_node;
265 
266 	data = devm_kzalloc(&pdev->dev, sizeof(struct qoriq_tmu_data),
267 			    GFP_KERNEL);
268 	if (!data)
269 		return -ENOMEM;
270 
271 	platform_set_drvdata(pdev, data);
272 
273 	data->little_endian = of_property_read_bool(np, "little-endian");
274 
275 	data->regs = devm_platform_ioremap_resource(pdev, 0);
276 	if (IS_ERR(data->regs)) {
277 		dev_err(&pdev->dev, "Failed to get memory region\n");
278 		return PTR_ERR(data->regs);
279 	}
280 
281 	data->clk = devm_clk_get_optional(&pdev->dev, NULL);
282 	if (IS_ERR(data->clk))
283 		return PTR_ERR(data->clk);
284 
285 	ret = clk_prepare_enable(data->clk);
286 	if (ret) {
287 		dev_err(&pdev->dev, "Failed to enable clock\n");
288 		return ret;
289 	}
290 
291 	/* version register offset at: 0xbf8 on both v1 and v2 */
292 	ver = tmu_read(data, &data->regs->ipbrr0);
293 	data->ver = (ver >> 8) & 0xff;
294 	if (data->ver == TMU_VER2)
295 		data->regs_v2 = (void __iomem *)data->regs;
296 
297 	qoriq_tmu_init_device(data);	/* TMU initialization */
298 
299 	ret = qoriq_tmu_calibration(pdev);	/* TMU calibration */
300 	if (ret < 0)
301 		goto err;
302 
303 	ret = qoriq_tmu_register_tmu_zone(pdev);
304 	if (ret < 0) {
305 		dev_err(&pdev->dev, "Failed to register sensors\n");
306 		ret = -ENODEV;
307 		goto err;
308 	}
309 
310 	return 0;
311 
312 err:
313 	clk_disable_unprepare(data->clk);
314 	platform_set_drvdata(pdev, NULL);
315 
316 	return ret;
317 }
318 
319 static int qoriq_tmu_remove(struct platform_device *pdev)
320 {
321 	struct qoriq_tmu_data *data = platform_get_drvdata(pdev);
322 
323 	/* Disable monitoring */
324 	tmu_write(data, TMR_DISABLE, &data->regs->tmr);
325 
326 	clk_disable_unprepare(data->clk);
327 
328 	platform_set_drvdata(pdev, NULL);
329 
330 	return 0;
331 }
332 
333 static int __maybe_unused qoriq_tmu_suspend(struct device *dev)
334 {
335 	u32 tmr;
336 	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
337 
338 	/* Disable monitoring */
339 	tmr = tmu_read(data, &data->regs->tmr);
340 	tmr &= ~TMR_ME;
341 	tmu_write(data, tmr, &data->regs->tmr);
342 
343 	clk_disable_unprepare(data->clk);
344 
345 	return 0;
346 }
347 
348 static int __maybe_unused qoriq_tmu_resume(struct device *dev)
349 {
350 	u32 tmr;
351 	int ret;
352 	struct qoriq_tmu_data *data = dev_get_drvdata(dev);
353 
354 	ret = clk_prepare_enable(data->clk);
355 	if (ret)
356 		return ret;
357 
358 	/* Enable monitoring */
359 	tmr = tmu_read(data, &data->regs->tmr);
360 	tmr |= TMR_ME;
361 	tmu_write(data, tmr, &data->regs->tmr);
362 
363 	return 0;
364 }
365 
366 static SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops,
367 			 qoriq_tmu_suspend, qoriq_tmu_resume);
368 
369 static const struct of_device_id qoriq_tmu_match[] = {
370 	{ .compatible = "fsl,qoriq-tmu", },
371 	{ .compatible = "fsl,imx8mq-tmu", },
372 	{},
373 };
374 MODULE_DEVICE_TABLE(of, qoriq_tmu_match);
375 
376 static struct platform_driver qoriq_tmu = {
377 	.driver	= {
378 		.name		= "qoriq_thermal",
379 		.pm		= &qoriq_tmu_pm_ops,
380 		.of_match_table	= qoriq_tmu_match,
381 	},
382 	.probe	= qoriq_tmu_probe,
383 	.remove	= qoriq_tmu_remove,
384 };
385 module_platform_driver(qoriq_tmu);
386 
387 MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>");
388 MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver");
389 MODULE_LICENSE("GPL v2");
390