1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef __QCOM_TSENS_H__ 7 #define __QCOM_TSENS_H__ 8 9 #define ONE_PT_CALIB 0x1 10 #define ONE_PT_CALIB2 0x2 11 #define TWO_PT_CALIB 0x3 12 #define CAL_DEGC_PT1 30 13 #define CAL_DEGC_PT2 120 14 #define SLOPE_FACTOR 1000 15 #define SLOPE_DEFAULT 3200 16 #define TIMEOUT_US 100 17 #define THRESHOLD_MAX_ADC_CODE 0x3ff 18 #define THRESHOLD_MIN_ADC_CODE 0x0 19 20 #include <linux/interrupt.h> 21 #include <linux/thermal.h> 22 #include <linux/regmap.h> 23 #include <linux/slab.h> 24 25 struct tsens_priv; 26 27 /* IP version numbers in ascending order */ 28 enum tsens_ver { 29 VER_0 = 0, 30 VER_0_1, 31 VER_1_X, 32 VER_2_X, 33 }; 34 35 enum tsens_irq_type { 36 LOWER, 37 UPPER, 38 CRITICAL, 39 }; 40 41 /** 42 * struct tsens_sensor - data for each sensor connected to the tsens device 43 * @priv: tsens device instance that this sensor is connected to 44 * @tzd: pointer to the thermal zone that this sensor is in 45 * @offset: offset of temperature adjustment curve 46 * @hw_id: HW ID can be used in case of platform-specific IDs 47 * @slope: slope of temperature adjustment curve 48 * @status: 8960-specific variable to track 8960 and 8660 status register offset 49 */ 50 struct tsens_sensor { 51 struct tsens_priv *priv; 52 struct thermal_zone_device *tzd; 53 int offset; 54 unsigned int hw_id; 55 int slope; 56 u32 status; 57 }; 58 59 /** 60 * struct tsens_ops - operations as supported by the tsens device 61 * @init: Function to initialize the tsens device 62 * @calibrate: Function to calibrate the tsens device 63 * @get_temp: Function which returns the temp in millidegC 64 * @enable: Function to enable (clocks/power) tsens device 65 * @disable: Function to disable the tsens device 66 * @suspend: Function to suspend the tsens device 67 * @resume: Function to resume the tsens device 68 * @get_trend: Function to get the thermal/temp trend 69 */ 70 struct tsens_ops { 71 /* mandatory callbacks */ 72 int (*init)(struct tsens_priv *priv); 73 int (*calibrate)(struct tsens_priv *priv); 74 int (*get_temp)(const struct tsens_sensor *s, int *temp); 75 /* optional callbacks */ 76 int (*enable)(struct tsens_priv *priv, int i); 77 void (*disable)(struct tsens_priv *priv); 78 int (*suspend)(struct tsens_priv *priv); 79 int (*resume)(struct tsens_priv *priv); 80 int (*get_trend)(struct tsens_sensor *s, enum thermal_trend *trend); 81 }; 82 83 #define REG_FIELD_FOR_EACH_SENSOR11(_name, _offset, _startbit, _stopbit) \ 84 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \ 85 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \ 86 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \ 87 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \ 88 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \ 89 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \ 90 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \ 91 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \ 92 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \ 93 [_name##_##9] = REG_FIELD(_offset + 36, _startbit, _stopbit), \ 94 [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit) 95 96 #define REG_FIELD_FOR_EACH_SENSOR16(_name, _offset, _startbit, _stopbit) \ 97 [_name##_##0] = REG_FIELD(_offset, _startbit, _stopbit), \ 98 [_name##_##1] = REG_FIELD(_offset + 4, _startbit, _stopbit), \ 99 [_name##_##2] = REG_FIELD(_offset + 8, _startbit, _stopbit), \ 100 [_name##_##3] = REG_FIELD(_offset + 12, _startbit, _stopbit), \ 101 [_name##_##4] = REG_FIELD(_offset + 16, _startbit, _stopbit), \ 102 [_name##_##5] = REG_FIELD(_offset + 20, _startbit, _stopbit), \ 103 [_name##_##6] = REG_FIELD(_offset + 24, _startbit, _stopbit), \ 104 [_name##_##7] = REG_FIELD(_offset + 28, _startbit, _stopbit), \ 105 [_name##_##8] = REG_FIELD(_offset + 32, _startbit, _stopbit), \ 106 [_name##_##9] = REG_FIELD(_offset + 36, _startbit, _stopbit), \ 107 [_name##_##10] = REG_FIELD(_offset + 40, _startbit, _stopbit), \ 108 [_name##_##11] = REG_FIELD(_offset + 44, _startbit, _stopbit), \ 109 [_name##_##12] = REG_FIELD(_offset + 48, _startbit, _stopbit), \ 110 [_name##_##13] = REG_FIELD(_offset + 52, _startbit, _stopbit), \ 111 [_name##_##14] = REG_FIELD(_offset + 56, _startbit, _stopbit), \ 112 [_name##_##15] = REG_FIELD(_offset + 60, _startbit, _stopbit) 113 114 #define REG_FIELD_SPLIT_BITS_0_15(_name, _offset) \ 115 [_name##_##0] = REG_FIELD(_offset, 0, 0), \ 116 [_name##_##1] = REG_FIELD(_offset, 1, 1), \ 117 [_name##_##2] = REG_FIELD(_offset, 2, 2), \ 118 [_name##_##3] = REG_FIELD(_offset, 3, 3), \ 119 [_name##_##4] = REG_FIELD(_offset, 4, 4), \ 120 [_name##_##5] = REG_FIELD(_offset, 5, 5), \ 121 [_name##_##6] = REG_FIELD(_offset, 6, 6), \ 122 [_name##_##7] = REG_FIELD(_offset, 7, 7), \ 123 [_name##_##8] = REG_FIELD(_offset, 8, 8), \ 124 [_name##_##9] = REG_FIELD(_offset, 9, 9), \ 125 [_name##_##10] = REG_FIELD(_offset, 10, 10), \ 126 [_name##_##11] = REG_FIELD(_offset, 11, 11), \ 127 [_name##_##12] = REG_FIELD(_offset, 12, 12), \ 128 [_name##_##13] = REG_FIELD(_offset, 13, 13), \ 129 [_name##_##14] = REG_FIELD(_offset, 14, 14), \ 130 [_name##_##15] = REG_FIELD(_offset, 15, 15) 131 132 #define REG_FIELD_SPLIT_BITS_16_31(_name, _offset) \ 133 [_name##_##0] = REG_FIELD(_offset, 16, 16), \ 134 [_name##_##1] = REG_FIELD(_offset, 17, 17), \ 135 [_name##_##2] = REG_FIELD(_offset, 18, 18), \ 136 [_name##_##3] = REG_FIELD(_offset, 19, 19), \ 137 [_name##_##4] = REG_FIELD(_offset, 20, 20), \ 138 [_name##_##5] = REG_FIELD(_offset, 21, 21), \ 139 [_name##_##6] = REG_FIELD(_offset, 22, 22), \ 140 [_name##_##7] = REG_FIELD(_offset, 23, 23), \ 141 [_name##_##8] = REG_FIELD(_offset, 24, 24), \ 142 [_name##_##9] = REG_FIELD(_offset, 25, 25), \ 143 [_name##_##10] = REG_FIELD(_offset, 26, 26), \ 144 [_name##_##11] = REG_FIELD(_offset, 27, 27), \ 145 [_name##_##12] = REG_FIELD(_offset, 28, 28), \ 146 [_name##_##13] = REG_FIELD(_offset, 29, 29), \ 147 [_name##_##14] = REG_FIELD(_offset, 30, 30), \ 148 [_name##_##15] = REG_FIELD(_offset, 31, 31) 149 150 /* 151 * reg_field IDs to use as an index into an array 152 * If you change the order of the entries, check the devm_regmap_field_alloc() 153 * calls in init_common() 154 */ 155 enum regfield_ids { 156 /* ----- SROT ------ */ 157 /* HW_VER */ 158 VER_MAJOR, 159 VER_MINOR, 160 VER_STEP, 161 /* CTRL_OFFSET */ 162 TSENS_EN, 163 TSENS_SW_RST, 164 SENSOR_EN, 165 CODE_OR_TEMP, 166 167 /* ----- TM ------ */ 168 /* TRDY */ 169 TRDY, 170 /* INTERRUPT ENABLE */ 171 INT_EN, /* v2+ has separate enables for crit, upper and lower irq */ 172 /* STATUS */ 173 LAST_TEMP_0, /* Last temperature reading */ 174 LAST_TEMP_1, 175 LAST_TEMP_2, 176 LAST_TEMP_3, 177 LAST_TEMP_4, 178 LAST_TEMP_5, 179 LAST_TEMP_6, 180 LAST_TEMP_7, 181 LAST_TEMP_8, 182 LAST_TEMP_9, 183 LAST_TEMP_10, 184 LAST_TEMP_11, 185 LAST_TEMP_12, 186 LAST_TEMP_13, 187 LAST_TEMP_14, 188 LAST_TEMP_15, 189 VALID_0, /* VALID reading or not */ 190 VALID_1, 191 VALID_2, 192 VALID_3, 193 VALID_4, 194 VALID_5, 195 VALID_6, 196 VALID_7, 197 VALID_8, 198 VALID_9, 199 VALID_10, 200 VALID_11, 201 VALID_12, 202 VALID_13, 203 VALID_14, 204 VALID_15, 205 LOWER_STATUS_0, /* LOWER threshold violated */ 206 LOWER_STATUS_1, 207 LOWER_STATUS_2, 208 LOWER_STATUS_3, 209 LOWER_STATUS_4, 210 LOWER_STATUS_5, 211 LOWER_STATUS_6, 212 LOWER_STATUS_7, 213 LOWER_STATUS_8, 214 LOWER_STATUS_9, 215 LOWER_STATUS_10, 216 LOWER_STATUS_11, 217 LOWER_STATUS_12, 218 LOWER_STATUS_13, 219 LOWER_STATUS_14, 220 LOWER_STATUS_15, 221 LOW_INT_STATUS_0, /* LOWER interrupt status */ 222 LOW_INT_STATUS_1, 223 LOW_INT_STATUS_2, 224 LOW_INT_STATUS_3, 225 LOW_INT_STATUS_4, 226 LOW_INT_STATUS_5, 227 LOW_INT_STATUS_6, 228 LOW_INT_STATUS_7, 229 LOW_INT_STATUS_8, 230 LOW_INT_STATUS_9, 231 LOW_INT_STATUS_10, 232 LOW_INT_STATUS_11, 233 LOW_INT_STATUS_12, 234 LOW_INT_STATUS_13, 235 LOW_INT_STATUS_14, 236 LOW_INT_STATUS_15, 237 LOW_INT_CLEAR_0, /* LOWER interrupt clear */ 238 LOW_INT_CLEAR_1, 239 LOW_INT_CLEAR_2, 240 LOW_INT_CLEAR_3, 241 LOW_INT_CLEAR_4, 242 LOW_INT_CLEAR_5, 243 LOW_INT_CLEAR_6, 244 LOW_INT_CLEAR_7, 245 LOW_INT_CLEAR_8, 246 LOW_INT_CLEAR_9, 247 LOW_INT_CLEAR_10, 248 LOW_INT_CLEAR_11, 249 LOW_INT_CLEAR_12, 250 LOW_INT_CLEAR_13, 251 LOW_INT_CLEAR_14, 252 LOW_INT_CLEAR_15, 253 LOW_INT_MASK_0, /* LOWER interrupt mask */ 254 LOW_INT_MASK_1, 255 LOW_INT_MASK_2, 256 LOW_INT_MASK_3, 257 LOW_INT_MASK_4, 258 LOW_INT_MASK_5, 259 LOW_INT_MASK_6, 260 LOW_INT_MASK_7, 261 LOW_INT_MASK_8, 262 LOW_INT_MASK_9, 263 LOW_INT_MASK_10, 264 LOW_INT_MASK_11, 265 LOW_INT_MASK_12, 266 LOW_INT_MASK_13, 267 LOW_INT_MASK_14, 268 LOW_INT_MASK_15, 269 LOW_THRESH_0, /* LOWER threshold values */ 270 LOW_THRESH_1, 271 LOW_THRESH_2, 272 LOW_THRESH_3, 273 LOW_THRESH_4, 274 LOW_THRESH_5, 275 LOW_THRESH_6, 276 LOW_THRESH_7, 277 LOW_THRESH_8, 278 LOW_THRESH_9, 279 LOW_THRESH_10, 280 LOW_THRESH_11, 281 LOW_THRESH_12, 282 LOW_THRESH_13, 283 LOW_THRESH_14, 284 LOW_THRESH_15, 285 UPPER_STATUS_0, /* UPPER threshold violated */ 286 UPPER_STATUS_1, 287 UPPER_STATUS_2, 288 UPPER_STATUS_3, 289 UPPER_STATUS_4, 290 UPPER_STATUS_5, 291 UPPER_STATUS_6, 292 UPPER_STATUS_7, 293 UPPER_STATUS_8, 294 UPPER_STATUS_9, 295 UPPER_STATUS_10, 296 UPPER_STATUS_11, 297 UPPER_STATUS_12, 298 UPPER_STATUS_13, 299 UPPER_STATUS_14, 300 UPPER_STATUS_15, 301 UP_INT_STATUS_0, /* UPPER interrupt status */ 302 UP_INT_STATUS_1, 303 UP_INT_STATUS_2, 304 UP_INT_STATUS_3, 305 UP_INT_STATUS_4, 306 UP_INT_STATUS_5, 307 UP_INT_STATUS_6, 308 UP_INT_STATUS_7, 309 UP_INT_STATUS_8, 310 UP_INT_STATUS_9, 311 UP_INT_STATUS_10, 312 UP_INT_STATUS_11, 313 UP_INT_STATUS_12, 314 UP_INT_STATUS_13, 315 UP_INT_STATUS_14, 316 UP_INT_STATUS_15, 317 UP_INT_CLEAR_0, /* UPPER interrupt clear */ 318 UP_INT_CLEAR_1, 319 UP_INT_CLEAR_2, 320 UP_INT_CLEAR_3, 321 UP_INT_CLEAR_4, 322 UP_INT_CLEAR_5, 323 UP_INT_CLEAR_6, 324 UP_INT_CLEAR_7, 325 UP_INT_CLEAR_8, 326 UP_INT_CLEAR_9, 327 UP_INT_CLEAR_10, 328 UP_INT_CLEAR_11, 329 UP_INT_CLEAR_12, 330 UP_INT_CLEAR_13, 331 UP_INT_CLEAR_14, 332 UP_INT_CLEAR_15, 333 UP_INT_MASK_0, /* UPPER interrupt mask */ 334 UP_INT_MASK_1, 335 UP_INT_MASK_2, 336 UP_INT_MASK_3, 337 UP_INT_MASK_4, 338 UP_INT_MASK_5, 339 UP_INT_MASK_6, 340 UP_INT_MASK_7, 341 UP_INT_MASK_8, 342 UP_INT_MASK_9, 343 UP_INT_MASK_10, 344 UP_INT_MASK_11, 345 UP_INT_MASK_12, 346 UP_INT_MASK_13, 347 UP_INT_MASK_14, 348 UP_INT_MASK_15, 349 UP_THRESH_0, /* UPPER threshold values */ 350 UP_THRESH_1, 351 UP_THRESH_2, 352 UP_THRESH_3, 353 UP_THRESH_4, 354 UP_THRESH_5, 355 UP_THRESH_6, 356 UP_THRESH_7, 357 UP_THRESH_8, 358 UP_THRESH_9, 359 UP_THRESH_10, 360 UP_THRESH_11, 361 UP_THRESH_12, 362 UP_THRESH_13, 363 UP_THRESH_14, 364 UP_THRESH_15, 365 CRITICAL_STATUS_0, /* CRITICAL threshold violated */ 366 CRITICAL_STATUS_1, 367 CRITICAL_STATUS_2, 368 CRITICAL_STATUS_3, 369 CRITICAL_STATUS_4, 370 CRITICAL_STATUS_5, 371 CRITICAL_STATUS_6, 372 CRITICAL_STATUS_7, 373 CRITICAL_STATUS_8, 374 CRITICAL_STATUS_9, 375 CRITICAL_STATUS_10, 376 CRITICAL_STATUS_11, 377 CRITICAL_STATUS_12, 378 CRITICAL_STATUS_13, 379 CRITICAL_STATUS_14, 380 CRITICAL_STATUS_15, 381 CRIT_INT_STATUS_0, /* CRITICAL interrupt status */ 382 CRIT_INT_STATUS_1, 383 CRIT_INT_STATUS_2, 384 CRIT_INT_STATUS_3, 385 CRIT_INT_STATUS_4, 386 CRIT_INT_STATUS_5, 387 CRIT_INT_STATUS_6, 388 CRIT_INT_STATUS_7, 389 CRIT_INT_STATUS_8, 390 CRIT_INT_STATUS_9, 391 CRIT_INT_STATUS_10, 392 CRIT_INT_STATUS_11, 393 CRIT_INT_STATUS_12, 394 CRIT_INT_STATUS_13, 395 CRIT_INT_STATUS_14, 396 CRIT_INT_STATUS_15, 397 CRIT_INT_CLEAR_0, /* CRITICAL interrupt clear */ 398 CRIT_INT_CLEAR_1, 399 CRIT_INT_CLEAR_2, 400 CRIT_INT_CLEAR_3, 401 CRIT_INT_CLEAR_4, 402 CRIT_INT_CLEAR_5, 403 CRIT_INT_CLEAR_6, 404 CRIT_INT_CLEAR_7, 405 CRIT_INT_CLEAR_8, 406 CRIT_INT_CLEAR_9, 407 CRIT_INT_CLEAR_10, 408 CRIT_INT_CLEAR_11, 409 CRIT_INT_CLEAR_12, 410 CRIT_INT_CLEAR_13, 411 CRIT_INT_CLEAR_14, 412 CRIT_INT_CLEAR_15, 413 CRIT_INT_MASK_0, /* CRITICAL interrupt mask */ 414 CRIT_INT_MASK_1, 415 CRIT_INT_MASK_2, 416 CRIT_INT_MASK_3, 417 CRIT_INT_MASK_4, 418 CRIT_INT_MASK_5, 419 CRIT_INT_MASK_6, 420 CRIT_INT_MASK_7, 421 CRIT_INT_MASK_8, 422 CRIT_INT_MASK_9, 423 CRIT_INT_MASK_10, 424 CRIT_INT_MASK_11, 425 CRIT_INT_MASK_12, 426 CRIT_INT_MASK_13, 427 CRIT_INT_MASK_14, 428 CRIT_INT_MASK_15, 429 CRIT_THRESH_0, /* CRITICAL threshold values */ 430 CRIT_THRESH_1, 431 CRIT_THRESH_2, 432 CRIT_THRESH_3, 433 CRIT_THRESH_4, 434 CRIT_THRESH_5, 435 CRIT_THRESH_6, 436 CRIT_THRESH_7, 437 CRIT_THRESH_8, 438 CRIT_THRESH_9, 439 CRIT_THRESH_10, 440 CRIT_THRESH_11, 441 CRIT_THRESH_12, 442 CRIT_THRESH_13, 443 CRIT_THRESH_14, 444 CRIT_THRESH_15, 445 446 /* WATCHDOG */ 447 WDOG_BARK_STATUS, 448 WDOG_BARK_CLEAR, 449 WDOG_BARK_MASK, 450 WDOG_BARK_COUNT, 451 452 /* CYCLE COMPLETION MONITOR */ 453 CC_MON_STATUS, 454 CC_MON_CLEAR, 455 CC_MON_MASK, 456 457 MIN_STATUS_0, /* MIN threshold violated */ 458 MIN_STATUS_1, 459 MIN_STATUS_2, 460 MIN_STATUS_3, 461 MIN_STATUS_4, 462 MIN_STATUS_5, 463 MIN_STATUS_6, 464 MIN_STATUS_7, 465 MIN_STATUS_8, 466 MIN_STATUS_9, 467 MIN_STATUS_10, 468 MIN_STATUS_11, 469 MIN_STATUS_12, 470 MIN_STATUS_13, 471 MIN_STATUS_14, 472 MIN_STATUS_15, 473 MAX_STATUS_0, /* MAX threshold violated */ 474 MAX_STATUS_1, 475 MAX_STATUS_2, 476 MAX_STATUS_3, 477 MAX_STATUS_4, 478 MAX_STATUS_5, 479 MAX_STATUS_6, 480 MAX_STATUS_7, 481 MAX_STATUS_8, 482 MAX_STATUS_9, 483 MAX_STATUS_10, 484 MAX_STATUS_11, 485 MAX_STATUS_12, 486 MAX_STATUS_13, 487 MAX_STATUS_14, 488 MAX_STATUS_15, 489 490 /* Keep last */ 491 MAX_REGFIELDS 492 }; 493 494 /** 495 * struct tsens_features - Features supported by the IP 496 * @ver_major: Major number of IP version 497 * @crit_int: does the IP support critical interrupts? 498 * @adc: do the sensors only output adc code (instead of temperature)? 499 * @srot_split: does the IP neatly splits the register space into SROT and TM, 500 * with SROT only being available to secure boot firmware? 501 * @has_watchdog: does this IP support watchdog functionality? 502 * @max_sensors: maximum sensors supported by this version of the IP 503 */ 504 struct tsens_features { 505 unsigned int ver_major; 506 unsigned int crit_int:1; 507 unsigned int adc:1; 508 unsigned int srot_split:1; 509 unsigned int has_watchdog:1; 510 unsigned int max_sensors; 511 }; 512 513 /** 514 * struct tsens_plat_data - tsens compile-time platform data 515 * @num_sensors: Number of sensors supported by platform 516 * @ops: operations the tsens instance supports 517 * @hw_ids: Subset of sensors ids supported by platform, if not the first n 518 * @feat: features of the IP 519 * @fields: bitfield locations 520 */ 521 struct tsens_plat_data { 522 const u32 num_sensors; 523 const struct tsens_ops *ops; 524 unsigned int *hw_ids; 525 struct tsens_features *feat; 526 const struct reg_field *fields; 527 }; 528 529 /** 530 * struct tsens_context - Registers to be saved/restored across a context loss 531 * @threshold: Threshold register value 532 * @control: Control register value 533 */ 534 struct tsens_context { 535 int threshold; 536 int control; 537 }; 538 539 /** 540 * struct tsens_priv - private data for each instance of the tsens IP 541 * @dev: pointer to struct device 542 * @num_sensors: number of sensors enabled on this device 543 * @tm_map: pointer to TM register address space 544 * @srot_map: pointer to SROT register address space 545 * @tm_offset: deal with old device trees that don't address TM and SROT 546 * address space separately 547 * @ul_lock: lock while processing upper/lower threshold interrupts 548 * @crit_lock: lock while processing critical threshold interrupts 549 * @rf: array of regmap_fields used to store value of the field 550 * @ctx: registers to be saved and restored during suspend/resume 551 * @feat: features of the IP 552 * @fields: bitfield locations 553 * @ops: pointer to list of callbacks supported by this device 554 * @debug_root: pointer to debugfs dentry for all tsens 555 * @debug: pointer to debugfs dentry for tsens controller 556 * @sensor: list of sensors attached to this device 557 */ 558 struct tsens_priv { 559 struct device *dev; 560 u32 num_sensors; 561 struct regmap *tm_map; 562 struct regmap *srot_map; 563 u32 tm_offset; 564 565 /* lock for upper/lower threshold interrupts */ 566 spinlock_t ul_lock; 567 568 struct regmap_field *rf[MAX_REGFIELDS]; 569 struct tsens_context ctx; 570 struct tsens_features *feat; 571 const struct reg_field *fields; 572 const struct tsens_ops *ops; 573 574 struct dentry *debug_root; 575 struct dentry *debug; 576 577 struct tsens_sensor sensor[]; 578 }; 579 580 char *qfprom_read(struct device *dev, const char *cname); 581 void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode); 582 int init_common(struct tsens_priv *priv); 583 int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp); 584 int get_temp_common(const struct tsens_sensor *s, int *temp); 585 586 /* TSENS target */ 587 extern struct tsens_plat_data data_8960; 588 589 /* TSENS v0.1 targets */ 590 extern struct tsens_plat_data data_8916, data_8939, data_8974, data_9607; 591 592 /* TSENS v1 targets */ 593 extern struct tsens_plat_data data_tsens_v1, data_8976; 594 595 /* TSENS v2 targets */ 596 extern struct tsens_plat_data data_8996, data_tsens_v2; 597 598 #endif /* __QCOM_TSENS_H__ */ 599