1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2020 Linaro Limited
4  *
5  * Based on original driver:
6  * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved.
7  *
8  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
9  */
10 
11 #include <linux/bitfield.h>
12 #include <linux/iio/adc/qcom-vadc-common.h>
13 #include <linux/iio/consumer.h>
14 #include <linux/interrupt.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20 #include <linux/thermal.h>
21 
22 #include <asm/unaligned.h>
23 
24 #include "../thermal_hwmon.h"
25 
26 /*
27  * Thermal monitoring block consists of 8 (ADC_TM5_NUM_CHANNELS) channels. Each
28  * channel is programmed to use one of ADC channels for voltage comparison.
29  * Voltages are programmed using ADC codes, so we have to convert temp to
30  * voltage and then to ADC code value.
31  *
32  * Configuration of TM channels must match configuration of corresponding ADC
33  * channels.
34  */
35 
36 #define ADC5_MAX_CHANNEL                        0xc0
37 #define ADC_TM5_NUM_CHANNELS		8
38 
39 #define ADC_TM5_STATUS_LOW			0x0a
40 
41 #define ADC_TM5_STATUS_HIGH			0x0b
42 
43 #define ADC_TM5_NUM_BTM				0x0f
44 
45 #define ADC_TM5_ADC_DIG_PARAM			0x42
46 
47 #define ADC_TM5_FAST_AVG_CTL			(ADC_TM5_ADC_DIG_PARAM + 1)
48 #define ADC_TM5_FAST_AVG_EN				BIT(7)
49 
50 #define ADC_TM5_MEAS_INTERVAL_CTL		(ADC_TM5_ADC_DIG_PARAM + 2)
51 #define ADC_TM5_TIMER1					3 /* 3.9ms */
52 
53 #define ADC_TM5_MEAS_INTERVAL_CTL2		(ADC_TM5_ADC_DIG_PARAM + 3)
54 #define ADC_TM5_MEAS_INTERVAL_CTL2_MASK			0xf0
55 #define ADC_TM5_TIMER2					10 /* 1 second */
56 #define ADC_TM5_MEAS_INTERVAL_CTL3_MASK			0xf
57 #define ADC_TM5_TIMER3					4 /* 4 second */
58 
59 #define ADC_TM_EN_CTL1				0x46
60 #define ADC_TM_EN					BIT(7)
61 #define ADC_TM_CONV_REQ				0x47
62 #define ADC_TM_CONV_REQ_EN				BIT(7)
63 
64 #define ADC_TM5_M_CHAN_BASE			0x60
65 
66 #define ADC_TM5_M_ADC_CH_SEL_CTL(n)		(ADC_TM5_M_CHAN_BASE + ((n) * 8) + 0)
67 #define ADC_TM5_M_LOW_THR0(n)			(ADC_TM5_M_CHAN_BASE + ((n) * 8) + 1)
68 #define ADC_TM5_M_LOW_THR1(n)			(ADC_TM5_M_CHAN_BASE + ((n) * 8) + 2)
69 #define ADC_TM5_M_HIGH_THR0(n)			(ADC_TM5_M_CHAN_BASE + ((n) * 8) + 3)
70 #define ADC_TM5_M_HIGH_THR1(n)			(ADC_TM5_M_CHAN_BASE + ((n) * 8) + 4)
71 #define ADC_TM5_M_MEAS_INTERVAL_CTL(n)		(ADC_TM5_M_CHAN_BASE + ((n) * 8) + 5)
72 #define ADC_TM5_M_CTL(n)			(ADC_TM5_M_CHAN_BASE + ((n) * 8) + 6)
73 #define ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK		0xf
74 #define ADC_TM5_M_CTL_CAL_SEL_MASK			0x30
75 #define ADC_TM5_M_CTL_CAL_VAL				0x40
76 #define ADC_TM5_M_EN(n)				(ADC_TM5_M_CHAN_BASE + ((n) * 8) + 7)
77 #define ADC_TM5_M_MEAS_EN				BIT(7)
78 #define ADC_TM5_M_HIGH_THR_INT_EN			BIT(1)
79 #define ADC_TM5_M_LOW_THR_INT_EN			BIT(0)
80 
81 #define ADC_TM_GEN2_STATUS1			0x08
82 #define ADC_TM_GEN2_STATUS_LOW_SET		0x09
83 #define ADC_TM_GEN2_STATUS_LOW_CLR		0x0a
84 #define ADC_TM_GEN2_STATUS_HIGH_SET		0x0b
85 #define ADC_TM_GEN2_STATUS_HIGH_CLR		0x0c
86 
87 #define ADC_TM_GEN2_CFG_HS_SET			0x0d
88 #define ADC_TM_GEN2_CFG_HS_FLAG			BIT(0)
89 #define ADC_TM_GEN2_CFG_HS_CLR			0x0e
90 
91 #define ADC_TM_GEN2_SID				0x40
92 
93 #define ADC_TM_GEN2_CH_CTL			0x41
94 #define ADC_TM_GEN2_TM_CH_SEL			GENMASK(7, 5)
95 #define ADC_TM_GEN2_MEAS_INT_SEL		GENMASK(3, 2)
96 
97 #define ADC_TM_GEN2_ADC_DIG_PARAM		0x42
98 #define ADC_TM_GEN2_CTL_CAL_SEL			GENMASK(5, 4)
99 #define ADC_TM_GEN2_CTL_DEC_RATIO_MASK		GENMASK(3, 2)
100 
101 #define ADC_TM_GEN2_FAST_AVG_CTL		0x43
102 #define ADC_TM_GEN2_FAST_AVG_EN			BIT(7)
103 
104 #define ADC_TM_GEN2_ADC_CH_SEL_CTL		0x44
105 
106 #define ADC_TM_GEN2_DELAY_CTL			0x45
107 #define ADC_TM_GEN2_HW_SETTLE_DELAY		GENMASK(3, 0)
108 
109 #define ADC_TM_GEN2_EN_CTL1			0x46
110 #define ADC_TM_GEN2_EN				BIT(7)
111 
112 #define ADC_TM_GEN2_CONV_REQ			0x47
113 #define ADC_TM_GEN2_CONV_REQ_EN			BIT(7)
114 
115 #define ADC_TM_GEN2_LOW_THR0			0x49
116 #define ADC_TM_GEN2_LOW_THR1			0x4a
117 #define ADC_TM_GEN2_HIGH_THR0			0x4b
118 #define ADC_TM_GEN2_HIGH_THR1			0x4c
119 #define ADC_TM_GEN2_LOWER_MASK(n)		((n) & GENMASK(7, 0))
120 #define ADC_TM_GEN2_UPPER_MASK(n)		(((n) & GENMASK(15, 8)) >> 8)
121 
122 #define ADC_TM_GEN2_MEAS_IRQ_EN			0x4d
123 #define ADC_TM_GEN2_MEAS_EN			BIT(7)
124 #define ADC_TM5_GEN2_HIGH_THR_INT_EN		BIT(1)
125 #define ADC_TM5_GEN2_LOW_THR_INT_EN		BIT(0)
126 
127 #define ADC_TM_GEN2_MEAS_INT_LSB		0x50
128 #define ADC_TM_GEN2_MEAS_INT_MSB		0x51
129 #define ADC_TM_GEN2_MEAS_INT_MODE		0x52
130 
131 #define ADC_TM_GEN2_Mn_DATA0(n)			((n * 2) + 0xa0)
132 #define ADC_TM_GEN2_Mn_DATA1(n)			((n * 2) + 0xa1)
133 #define ADC_TM_GEN2_DATA_SHIFT			8
134 
135 enum adc5_timer_select {
136 	ADC5_TIMER_SEL_1 = 0,
137 	ADC5_TIMER_SEL_2,
138 	ADC5_TIMER_SEL_3,
139 	ADC5_TIMER_SEL_NONE,
140 };
141 
142 enum adc5_gen {
143 	ADC_TM5,
144 	ADC_TM_HC,
145 	ADC_TM5_GEN2,
146 	ADC_TM5_MAX
147 };
148 
149 enum adc_tm5_cal_method {
150 	ADC_TM5_NO_CAL = 0,
151 	ADC_TM5_RATIOMETRIC_CAL,
152 	ADC_TM5_ABSOLUTE_CAL
153 };
154 
155 enum adc_tm_gen2_time_select {
156 	MEAS_INT_50MS = 0,
157 	MEAS_INT_100MS,
158 	MEAS_INT_1S,
159 	MEAS_INT_SET,
160 	MEAS_INT_NONE,
161 };
162 
163 struct adc_tm5_chip;
164 struct adc_tm5_channel;
165 
166 struct adc_tm5_data {
167 	const u32 full_scale_code_volt;
168 	unsigned int *decimation;
169 	unsigned int *hw_settle;
170 	int (*disable_channel)(struct adc_tm5_channel *channel);
171 	int (*configure)(struct adc_tm5_channel *channel, int low, int high);
172 	irqreturn_t (*isr)(int irq, void *data);
173 	int (*init)(struct adc_tm5_chip *chip);
174 	char *irq_name;
175 	int gen;
176 };
177 
178 /**
179  * struct adc_tm5_channel - ADC Thermal Monitoring channel data.
180  * @channel: channel number.
181  * @adc_channel: corresponding ADC channel number.
182  * @cal_method: calibration method.
183  * @prescale: channel scaling performed on the input signal.
184  * @hw_settle_time: the time between AMUX being configured and the
185  *	start of conversion.
186  * @decimation: sampling rate supported for the channel.
187  * @avg_samples: ability to provide single result from the ADC
188  *	that is an average of multiple measurements.
189  * @high_thr_en: channel upper voltage threshold enable state.
190  * @low_thr_en: channel lower voltage threshold enable state.
191  * @meas_en: recurring measurement enable state
192  * @iio: IIO channel instance used by this channel.
193  * @chip: ADC TM chip instance.
194  * @tzd: thermal zone device used by this channel.
195  */
196 struct adc_tm5_channel {
197 	unsigned int		channel;
198 	unsigned int		adc_channel;
199 	enum adc_tm5_cal_method	cal_method;
200 	unsigned int		prescale;
201 	unsigned int		hw_settle_time;
202 	unsigned int		decimation;	/* For Gen2 ADC_TM */
203 	unsigned int		avg_samples;	/* For Gen2 ADC_TM */
204 	bool			high_thr_en;	/* For Gen2 ADC_TM */
205 	bool			low_thr_en;	/* For Gen2 ADC_TM */
206 	bool			meas_en;	/* For Gen2 ADC_TM */
207 	struct iio_channel	*iio;
208 	struct adc_tm5_chip	*chip;
209 	struct thermal_zone_device *tzd;
210 };
211 
212 /**
213  * struct adc_tm5_chip - ADC Thermal Monitoring properties
214  * @regmap: SPMI ADC5 Thermal Monitoring  peripheral register map field.
215  * @dev: SPMI ADC5 device.
216  * @data: software configuration data.
217  * @channels: array of ADC TM channel data.
218  * @nchannels: amount of channels defined/allocated
219  * @decimation: sampling rate supported for the channel.
220  *      Applies to all channels, used only on Gen1 ADC_TM.
221  * @avg_samples: ability to provide single result from the ADC
222  *      that is an average of multiple measurements. Applies to all
223  *      channels, used only on Gen1 ADC_TM.
224  * @base: base address of TM registers.
225  * @adc_mutex_lock: ADC_TM mutex lock, used only on Gen2 ADC_TM.
226  *      It is used to ensure only one ADC channel configuration
227  *      is done at a time using the shared set of configuration
228  *      registers.
229  */
230 struct adc_tm5_chip {
231 	struct regmap		*regmap;
232 	struct device		*dev;
233 	const struct adc_tm5_data	*data;
234 	struct adc_tm5_channel	*channels;
235 	unsigned int		nchannels;
236 	unsigned int		decimation;
237 	unsigned int		avg_samples;
238 	u16			base;
239 	struct mutex		adc_mutex_lock;
240 };
241 
242 static int adc_tm5_read(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len)
243 {
244 	return regmap_bulk_read(adc_tm->regmap, adc_tm->base + offset, data, len);
245 }
246 
247 static int adc_tm5_write(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len)
248 {
249 	return regmap_bulk_write(adc_tm->regmap, adc_tm->base + offset, data, len);
250 }
251 
252 static int adc_tm5_reg_update(struct adc_tm5_chip *adc_tm, u16 offset, u8 mask, u8 val)
253 {
254 	return regmap_write_bits(adc_tm->regmap, adc_tm->base + offset, mask, val);
255 }
256 
257 static irqreturn_t adc_tm5_isr(int irq, void *data)
258 {
259 	struct adc_tm5_chip *chip = data;
260 	u8 status_low, status_high, ctl;
261 	int ret, i;
262 
263 	ret = adc_tm5_read(chip, ADC_TM5_STATUS_LOW, &status_low, sizeof(status_low));
264 	if (unlikely(ret)) {
265 		dev_err(chip->dev, "read status low failed: %d\n", ret);
266 		return IRQ_HANDLED;
267 	}
268 
269 	ret = adc_tm5_read(chip, ADC_TM5_STATUS_HIGH, &status_high, sizeof(status_high));
270 	if (unlikely(ret)) {
271 		dev_err(chip->dev, "read status high failed: %d\n", ret);
272 		return IRQ_HANDLED;
273 	}
274 
275 	for (i = 0; i < chip->nchannels; i++) {
276 		bool upper_set = false, lower_set = false;
277 		unsigned int ch = chip->channels[i].channel;
278 
279 		/* No TZD, we warned at the boot time */
280 		if (!chip->channels[i].tzd)
281 			continue;
282 
283 		ret = adc_tm5_read(chip, ADC_TM5_M_EN(ch), &ctl, sizeof(ctl));
284 		if (unlikely(ret)) {
285 			dev_err(chip->dev, "ctl read failed: %d, channel %d\n", ret, i);
286 			continue;
287 		}
288 
289 		if (!(ctl & ADC_TM5_M_MEAS_EN))
290 			continue;
291 
292 		lower_set = (status_low & BIT(ch)) &&
293 			(ctl & ADC_TM5_M_LOW_THR_INT_EN);
294 
295 		upper_set = (status_high & BIT(ch)) &&
296 			(ctl & ADC_TM5_M_HIGH_THR_INT_EN);
297 
298 		if (upper_set || lower_set)
299 			thermal_zone_device_update(chip->channels[i].tzd,
300 						   THERMAL_EVENT_UNSPECIFIED);
301 	}
302 
303 	return IRQ_HANDLED;
304 }
305 
306 static irqreturn_t adc_tm5_gen2_isr(int irq, void *data)
307 {
308 	struct adc_tm5_chip *chip = data;
309 	u8 status_low, status_high;
310 	int ret, i;
311 
312 	ret = adc_tm5_read(chip, ADC_TM_GEN2_STATUS_LOW_CLR, &status_low, sizeof(status_low));
313 	if (ret) {
314 		dev_err(chip->dev, "read status_low failed: %d\n", ret);
315 		return IRQ_HANDLED;
316 	}
317 
318 	ret = adc_tm5_read(chip, ADC_TM_GEN2_STATUS_HIGH_CLR, &status_high, sizeof(status_high));
319 	if (ret) {
320 		dev_err(chip->dev, "read status_high failed: %d\n", ret);
321 		return IRQ_HANDLED;
322 	}
323 
324 	ret = adc_tm5_write(chip, ADC_TM_GEN2_STATUS_LOW_CLR, &status_low, sizeof(status_low));
325 	if (ret < 0) {
326 		dev_err(chip->dev, "clear status low failed with %d\n", ret);
327 		return IRQ_HANDLED;
328 	}
329 
330 	ret = adc_tm5_write(chip, ADC_TM_GEN2_STATUS_HIGH_CLR, &status_high, sizeof(status_high));
331 	if (ret < 0) {
332 		dev_err(chip->dev, "clear status high failed with %d\n", ret);
333 		return IRQ_HANDLED;
334 	}
335 
336 	for (i = 0; i < chip->nchannels; i++) {
337 		bool upper_set = false, lower_set = false;
338 		unsigned int ch = chip->channels[i].channel;
339 
340 		/* No TZD, we warned at the boot time */
341 		if (!chip->channels[i].tzd)
342 			continue;
343 
344 		if (!chip->channels[i].meas_en)
345 			continue;
346 
347 		lower_set = (status_low & BIT(ch)) &&
348 			(chip->channels[i].low_thr_en);
349 
350 		upper_set = (status_high & BIT(ch)) &&
351 			(chip->channels[i].high_thr_en);
352 
353 		if (upper_set || lower_set)
354 			thermal_zone_device_update(chip->channels[i].tzd,
355 						   THERMAL_EVENT_UNSPECIFIED);
356 	}
357 
358 	return IRQ_HANDLED;
359 }
360 
361 static int adc_tm5_get_temp(struct thermal_zone_device *tz, int *temp)
362 {
363 	struct adc_tm5_channel *channel = tz->devdata;
364 	int ret;
365 
366 	if (!channel || !channel->iio)
367 		return -EINVAL;
368 
369 	ret = iio_read_channel_processed(channel->iio, temp);
370 	if (ret < 0)
371 		return ret;
372 
373 	if (ret != IIO_VAL_INT)
374 		return -EINVAL;
375 
376 	return 0;
377 }
378 
379 static int adc_tm5_disable_channel(struct adc_tm5_channel *channel)
380 {
381 	struct adc_tm5_chip *chip = channel->chip;
382 	unsigned int reg = ADC_TM5_M_EN(channel->channel);
383 
384 	return adc_tm5_reg_update(chip, reg,
385 				  ADC_TM5_M_MEAS_EN |
386 				  ADC_TM5_M_HIGH_THR_INT_EN |
387 				  ADC_TM5_M_LOW_THR_INT_EN,
388 				  0);
389 }
390 
391 #define ADC_TM_GEN2_POLL_DELAY_MIN_US		100
392 #define ADC_TM_GEN2_POLL_DELAY_MAX_US		110
393 #define ADC_TM_GEN2_POLL_RETRY_COUNT		3
394 
395 static int32_t adc_tm5_gen2_conv_req(struct adc_tm5_chip *chip)
396 {
397 	int ret;
398 	u8 data;
399 	unsigned int count;
400 
401 	data = ADC_TM_GEN2_EN;
402 	ret = adc_tm5_write(chip, ADC_TM_GEN2_EN_CTL1, &data, 1);
403 	if (ret < 0) {
404 		dev_err(chip->dev, "adc-tm enable failed with %d\n", ret);
405 		return ret;
406 	}
407 
408 	data = ADC_TM_GEN2_CFG_HS_FLAG;
409 	ret = adc_tm5_write(chip, ADC_TM_GEN2_CFG_HS_SET, &data, 1);
410 	if (ret < 0) {
411 		dev_err(chip->dev, "adc-tm handshake failed with %d\n", ret);
412 		return ret;
413 	}
414 
415 	data = ADC_TM_GEN2_CONV_REQ_EN;
416 	ret = adc_tm5_write(chip, ADC_TM_GEN2_CONV_REQ, &data, 1);
417 	if (ret < 0) {
418 		dev_err(chip->dev, "adc-tm request conversion failed with %d\n", ret);
419 		return ret;
420 	}
421 
422 	/*
423 	 * SW sets a handshake bit and waits for PBS to clear it
424 	 * before the next conversion request can be queued.
425 	 */
426 
427 	for (count = 0; count < ADC_TM_GEN2_POLL_RETRY_COUNT; count++) {
428 		ret = adc_tm5_read(chip, ADC_TM_GEN2_CFG_HS_SET, &data, sizeof(data));
429 		if (ret < 0) {
430 			dev_err(chip->dev, "adc-tm read failed with %d\n", ret);
431 			return ret;
432 		}
433 
434 		if (!(data & ADC_TM_GEN2_CFG_HS_FLAG))
435 			return ret;
436 		usleep_range(ADC_TM_GEN2_POLL_DELAY_MIN_US,
437 			ADC_TM_GEN2_POLL_DELAY_MAX_US);
438 	}
439 
440 	dev_err(chip->dev, "adc-tm conversion request handshake timed out\n");
441 
442 	return -ETIMEDOUT;
443 }
444 
445 static int adc_tm5_gen2_disable_channel(struct adc_tm5_channel *channel)
446 {
447 	struct adc_tm5_chip *chip = channel->chip;
448 	int ret;
449 	u8 val;
450 
451 	mutex_lock(&chip->adc_mutex_lock);
452 
453 	channel->meas_en = false;
454 	channel->high_thr_en = false;
455 	channel->low_thr_en = false;
456 
457 	ret = adc_tm5_read(chip, ADC_TM_GEN2_CH_CTL, &val, sizeof(val));
458 	if (ret < 0) {
459 		dev_err(chip->dev, "adc-tm block read failed with %d\n", ret);
460 		goto disable_fail;
461 	}
462 
463 	val &= ~ADC_TM_GEN2_TM_CH_SEL;
464 	val |= FIELD_PREP(ADC_TM_GEN2_TM_CH_SEL, channel->channel);
465 
466 	ret = adc_tm5_write(chip, ADC_TM_GEN2_CH_CTL, &val, 1);
467 	if (ret < 0) {
468 		dev_err(chip->dev, "adc-tm channel disable failed with %d\n", ret);
469 		goto disable_fail;
470 	}
471 
472 	val = 0;
473 	ret = adc_tm5_write(chip, ADC_TM_GEN2_MEAS_IRQ_EN, &val, 1);
474 	if (ret < 0) {
475 		dev_err(chip->dev, "adc-tm interrupt disable failed with %d\n", ret);
476 		goto disable_fail;
477 	}
478 
479 
480 	ret = adc_tm5_gen2_conv_req(channel->chip);
481 	if (ret < 0)
482 		dev_err(chip->dev, "adc-tm channel configure failed with %d\n", ret);
483 
484 disable_fail:
485 	mutex_unlock(&chip->adc_mutex_lock);
486 	return ret;
487 }
488 
489 static int adc_tm5_enable(struct adc_tm5_chip *chip)
490 {
491 	int ret;
492 	u8 data;
493 
494 	data = ADC_TM_EN;
495 	ret = adc_tm5_write(chip, ADC_TM_EN_CTL1, &data, sizeof(data));
496 	if (ret < 0) {
497 		dev_err(chip->dev, "adc-tm enable failed\n");
498 		return ret;
499 	}
500 
501 	data = ADC_TM_CONV_REQ_EN;
502 	ret = adc_tm5_write(chip, ADC_TM_CONV_REQ, &data, sizeof(data));
503 	if (ret < 0) {
504 		dev_err(chip->dev, "adc-tm request conversion failed\n");
505 		return ret;
506 	}
507 
508 	return 0;
509 }
510 
511 static int adc_tm5_configure(struct adc_tm5_channel *channel, int low, int high)
512 {
513 	struct adc_tm5_chip *chip = channel->chip;
514 	u8 buf[8];
515 	u16 reg = ADC_TM5_M_ADC_CH_SEL_CTL(channel->channel);
516 	int ret;
517 
518 	ret = adc_tm5_read(chip, reg, buf, sizeof(buf));
519 	if (ret) {
520 		dev_err(chip->dev, "channel %d params read failed: %d\n", channel->channel, ret);
521 		return ret;
522 	}
523 
524 	buf[0] = channel->adc_channel;
525 
526 	/* High temperature corresponds to low voltage threshold */
527 	if (high != INT_MAX) {
528 		u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale,
529 				chip->data->full_scale_code_volt, high);
530 
531 		put_unaligned_le16(adc_code, &buf[1]);
532 		buf[7] |= ADC_TM5_M_LOW_THR_INT_EN;
533 	} else {
534 		buf[7] &= ~ADC_TM5_M_LOW_THR_INT_EN;
535 	}
536 
537 	/* Low temperature corresponds to high voltage threshold */
538 	if (low != -INT_MAX) {
539 		u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale,
540 				chip->data->full_scale_code_volt, low);
541 
542 		put_unaligned_le16(adc_code, &buf[3]);
543 		buf[7] |= ADC_TM5_M_HIGH_THR_INT_EN;
544 	} else {
545 		buf[7] &= ~ADC_TM5_M_HIGH_THR_INT_EN;
546 	}
547 
548 	buf[5] = ADC5_TIMER_SEL_2;
549 
550 	/* Set calibration select, hw_settle delay */
551 	buf[6] &= ~ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK;
552 	buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK, channel->hw_settle_time);
553 	buf[6] &= ~ADC_TM5_M_CTL_CAL_SEL_MASK;
554 	buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_CAL_SEL_MASK, channel->cal_method);
555 
556 	buf[7] |= ADC_TM5_M_MEAS_EN;
557 
558 	ret = adc_tm5_write(chip, reg, buf, sizeof(buf));
559 	if (ret) {
560 		dev_err(chip->dev, "channel %d params write failed: %d\n", channel->channel, ret);
561 		return ret;
562 	}
563 
564 	return adc_tm5_enable(chip);
565 }
566 
567 static int adc_tm5_gen2_configure(struct adc_tm5_channel *channel, int low, int high)
568 {
569 	struct adc_tm5_chip *chip = channel->chip;
570 	int ret;
571 	u8 buf[14];
572 	u16 adc_code;
573 
574 	mutex_lock(&chip->adc_mutex_lock);
575 
576 	channel->meas_en = true;
577 
578 	ret = adc_tm5_read(chip, ADC_TM_GEN2_SID, buf, sizeof(buf));
579 	if (ret < 0) {
580 		dev_err(chip->dev, "adc-tm block read failed with %d\n", ret);
581 		goto config_fail;
582 	}
583 
584 	/* Set SID from virtual channel number */
585 	buf[0] = channel->adc_channel >> 8;
586 
587 	/* Set TM channel number used and measurement interval */
588 	buf[1] &= ~ADC_TM_GEN2_TM_CH_SEL;
589 	buf[1] |= FIELD_PREP(ADC_TM_GEN2_TM_CH_SEL, channel->channel);
590 	buf[1] &= ~ADC_TM_GEN2_MEAS_INT_SEL;
591 	buf[1] |= FIELD_PREP(ADC_TM_GEN2_MEAS_INT_SEL, MEAS_INT_1S);
592 
593 	buf[2] &= ~ADC_TM_GEN2_CTL_DEC_RATIO_MASK;
594 	buf[2] |= FIELD_PREP(ADC_TM_GEN2_CTL_DEC_RATIO_MASK, channel->decimation);
595 	buf[2] &= ~ADC_TM_GEN2_CTL_CAL_SEL;
596 	buf[2] |= FIELD_PREP(ADC_TM_GEN2_CTL_CAL_SEL, channel->cal_method);
597 
598 	buf[3] = channel->avg_samples | ADC_TM_GEN2_FAST_AVG_EN;
599 
600 	buf[4] = channel->adc_channel & 0xff;
601 
602 	buf[5] = channel->hw_settle_time & ADC_TM_GEN2_HW_SETTLE_DELAY;
603 
604 	/* High temperature corresponds to low voltage threshold */
605 	if (high != INT_MAX) {
606 		channel->low_thr_en = true;
607 		adc_code = qcom_adc_tm5_gen2_temp_res_scale(high);
608 		put_unaligned_le16(adc_code, &buf[9]);
609 	} else {
610 		channel->low_thr_en = false;
611 	}
612 
613 	/* Low temperature corresponds to high voltage threshold */
614 	if (low != -INT_MAX) {
615 		channel->high_thr_en = true;
616 		adc_code = qcom_adc_tm5_gen2_temp_res_scale(low);
617 		put_unaligned_le16(adc_code, &buf[11]);
618 	} else {
619 		channel->high_thr_en = false;
620 	}
621 
622 	buf[13] = ADC_TM_GEN2_MEAS_EN;
623 	if (channel->high_thr_en)
624 		buf[13] |= ADC_TM5_GEN2_HIGH_THR_INT_EN;
625 	if (channel->low_thr_en)
626 		buf[13] |= ADC_TM5_GEN2_LOW_THR_INT_EN;
627 
628 	ret = adc_tm5_write(chip, ADC_TM_GEN2_SID, buf, sizeof(buf));
629 	if (ret) {
630 		dev_err(chip->dev, "channel %d params write failed: %d\n", channel->channel, ret);
631 		goto config_fail;
632 	}
633 
634 	ret = adc_tm5_gen2_conv_req(channel->chip);
635 	if (ret < 0)
636 		dev_err(chip->dev, "adc-tm channel configure failed with %d\n", ret);
637 
638 config_fail:
639 	mutex_unlock(&chip->adc_mutex_lock);
640 	return ret;
641 }
642 
643 static int adc_tm5_set_trips(struct thermal_zone_device *tz, int low, int high)
644 {
645 	struct adc_tm5_channel *channel = tz->devdata;
646 	struct adc_tm5_chip *chip;
647 	int ret;
648 
649 	if (!channel)
650 		return -EINVAL;
651 
652 	chip = channel->chip;
653 	dev_dbg(chip->dev, "%d:low(mdegC):%d, high(mdegC):%d\n",
654 		channel->channel, low, high);
655 
656 	if (high == INT_MAX && low <= -INT_MAX)
657 		ret = chip->data->disable_channel(channel);
658 	else
659 		ret = chip->data->configure(channel, low, high);
660 
661 	return ret;
662 }
663 
664 static const struct thermal_zone_device_ops adc_tm5_thermal_ops = {
665 	.get_temp = adc_tm5_get_temp,
666 	.set_trips = adc_tm5_set_trips,
667 };
668 
669 static int adc_tm5_register_tzd(struct adc_tm5_chip *adc_tm)
670 {
671 	unsigned int i;
672 	struct thermal_zone_device *tzd;
673 
674 	for (i = 0; i < adc_tm->nchannels; i++) {
675 		adc_tm->channels[i].chip = adc_tm;
676 		tzd = devm_thermal_of_zone_register(adc_tm->dev,
677 						    adc_tm->channels[i].channel,
678 						    &adc_tm->channels[i],
679 						    &adc_tm5_thermal_ops);
680 		if (IS_ERR(tzd)) {
681 			if (PTR_ERR(tzd) == -ENODEV) {
682 				dev_dbg(adc_tm->dev, "thermal sensor on channel %d is not used\n",
683 					 adc_tm->channels[i].channel);
684 				continue;
685 			}
686 
687 			dev_err(adc_tm->dev, "Error registering TZ zone for channel %d: %ld\n",
688 				adc_tm->channels[i].channel, PTR_ERR(tzd));
689 			return PTR_ERR(tzd);
690 		}
691 		adc_tm->channels[i].tzd = tzd;
692 		if (devm_thermal_add_hwmon_sysfs(tzd))
693 			dev_warn(adc_tm->dev,
694 				 "Failed to add hwmon sysfs attributes\n");
695 	}
696 
697 	return 0;
698 }
699 
700 static int adc_tm_hc_init(struct adc_tm5_chip *chip)
701 {
702 	unsigned int i;
703 	u8 buf[2];
704 	int ret;
705 
706 	for (i = 0; i < chip->nchannels; i++) {
707 		if (chip->channels[i].channel >= ADC_TM5_NUM_CHANNELS) {
708 			dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel);
709 			return -EINVAL;
710 		}
711 	}
712 
713 	buf[0] = chip->decimation;
714 	buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN;
715 
716 	ret = adc_tm5_write(chip, ADC_TM5_ADC_DIG_PARAM, buf, sizeof(buf));
717 	if (ret)
718 		dev_err(chip->dev, "block write failed: %d\n", ret);
719 
720 	return ret;
721 }
722 
723 static int adc_tm5_init(struct adc_tm5_chip *chip)
724 {
725 	u8 buf[4], channels_available;
726 	int ret;
727 	unsigned int i;
728 
729 	ret = adc_tm5_read(chip, ADC_TM5_NUM_BTM,
730 			   &channels_available, sizeof(channels_available));
731 	if (ret) {
732 		dev_err(chip->dev, "read failed for BTM channels\n");
733 		return ret;
734 	}
735 
736 	for (i = 0; i < chip->nchannels; i++) {
737 		if (chip->channels[i].channel >= channels_available) {
738 			dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel);
739 			return -EINVAL;
740 		}
741 	}
742 
743 	buf[0] = chip->decimation;
744 	buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN;
745 	buf[2] = ADC_TM5_TIMER1;
746 	buf[3] = FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL2_MASK, ADC_TM5_TIMER2) |
747 		 FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL3_MASK, ADC_TM5_TIMER3);
748 
749 	ret = adc_tm5_write(chip, ADC_TM5_ADC_DIG_PARAM, buf, sizeof(buf));
750 	if (ret) {
751 		dev_err(chip->dev, "block write failed: %d\n", ret);
752 		return ret;
753 	}
754 
755 	return ret;
756 }
757 
758 static int adc_tm5_gen2_init(struct adc_tm5_chip *chip)
759 {
760 	u8 channels_available;
761 	int ret;
762 	unsigned int i;
763 
764 	ret = adc_tm5_read(chip, ADC_TM5_NUM_BTM,
765 			   &channels_available, sizeof(channels_available));
766 	if (ret) {
767 		dev_err(chip->dev, "read failed for BTM channels\n");
768 		return ret;
769 	}
770 
771 	for (i = 0; i < chip->nchannels; i++) {
772 		if (chip->channels[i].channel >= channels_available) {
773 			dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel);
774 			return -EINVAL;
775 		}
776 	}
777 
778 	mutex_init(&chip->adc_mutex_lock);
779 
780 	return ret;
781 }
782 
783 static int adc_tm5_get_dt_channel_data(struct adc_tm5_chip *adc_tm,
784 				       struct adc_tm5_channel *channel,
785 				       struct device_node *node)
786 {
787 	const char *name = node->name;
788 	u32 chan, value, adc_channel, varr[2];
789 	int ret;
790 	struct device *dev = adc_tm->dev;
791 	struct of_phandle_args args;
792 
793 	ret = of_property_read_u32(node, "reg", &chan);
794 	if (ret) {
795 		dev_err(dev, "%s: invalid channel number %d\n", name, ret);
796 		return ret;
797 	}
798 
799 	if (chan >= ADC_TM5_NUM_CHANNELS) {
800 		dev_err(dev, "%s: channel number too big: %d\n", name, chan);
801 		return -EINVAL;
802 	}
803 
804 	channel->channel = chan;
805 
806 	/*
807 	 * We are tied to PMIC's ADC controller, which always use single
808 	 * argument for channel number.  So don't bother parsing
809 	 * #io-channel-cells, just enforce cell_count = 1.
810 	 */
811 	ret = of_parse_phandle_with_fixed_args(node, "io-channels", 1, 0, &args);
812 	if (ret < 0) {
813 		dev_err(dev, "%s: error parsing ADC channel number %d: %d\n", name, chan, ret);
814 		return ret;
815 	}
816 	of_node_put(args.np);
817 
818 	if (args.args_count != 1) {
819 		dev_err(dev, "%s: invalid args count for ADC channel %d\n", name, chan);
820 		return -EINVAL;
821 	}
822 
823 	adc_channel = args.args[0];
824 	if (adc_tm->data->gen == ADC_TM5_GEN2)
825 		adc_channel &= 0xff;
826 
827 	if (adc_channel >= ADC5_MAX_CHANNEL) {
828 		dev_err(dev, "%s: invalid ADC channel number %d\n", name, chan);
829 		return -EINVAL;
830 	}
831 	channel->adc_channel = args.args[0];
832 
833 	channel->iio = devm_fwnode_iio_channel_get_by_name(adc_tm->dev,
834 							   of_fwnode_handle(node), NULL);
835 	if (IS_ERR(channel->iio)) {
836 		ret = PTR_ERR(channel->iio);
837 		if (ret != -EPROBE_DEFER)
838 			dev_err(dev, "%s: error getting channel: %d\n", name, ret);
839 		return ret;
840 	}
841 
842 	ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2);
843 	if (!ret) {
844 		ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]);
845 		if (ret < 0) {
846 			dev_err(dev, "%s: invalid pre-scaling <%d %d>\n",
847 				name, varr[0], varr[1]);
848 			return ret;
849 		}
850 		channel->prescale = ret;
851 	} else {
852 		/* 1:1 prescale is index 0 */
853 		channel->prescale = 0;
854 	}
855 
856 	ret = of_property_read_u32(node, "qcom,hw-settle-time-us", &value);
857 	if (!ret) {
858 		ret = qcom_adc5_hw_settle_time_from_dt(value, adc_tm->data->hw_settle);
859 		if (ret < 0) {
860 			dev_err(dev, "%s invalid hw-settle-time-us %d us\n",
861 				name, value);
862 			return ret;
863 		}
864 		channel->hw_settle_time = ret;
865 	} else {
866 		channel->hw_settle_time = VADC_DEF_HW_SETTLE_TIME;
867 	}
868 
869 	if (of_property_read_bool(node, "qcom,ratiometric"))
870 		channel->cal_method = ADC_TM5_RATIOMETRIC_CAL;
871 	else
872 		channel->cal_method = ADC_TM5_ABSOLUTE_CAL;
873 
874 	if (adc_tm->data->gen == ADC_TM5_GEN2) {
875 		ret = of_property_read_u32(node, "qcom,decimation", &value);
876 		if (!ret) {
877 			ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation);
878 			if (ret < 0) {
879 				dev_err(dev, "invalid decimation %d\n", value);
880 				return ret;
881 			}
882 			channel->decimation = ret;
883 		} else {
884 			channel->decimation = ADC5_DECIMATION_DEFAULT;
885 		}
886 
887 		ret = of_property_read_u32(node, "qcom,avg-samples", &value);
888 		if (!ret) {
889 			ret = qcom_adc5_avg_samples_from_dt(value);
890 			if (ret < 0) {
891 				dev_err(dev, "invalid avg-samples %d\n", value);
892 				return ret;
893 			}
894 			channel->avg_samples = ret;
895 		} else {
896 			channel->avg_samples = VADC_DEF_AVG_SAMPLES;
897 		}
898 	}
899 
900 	return 0;
901 }
902 
903 static const struct adc_tm5_data adc_tm5_data_pmic = {
904 	.full_scale_code_volt = 0x70e4,
905 	.decimation = (unsigned int []) { 250, 420, 840 },
906 	.hw_settle = (unsigned int []) { 15, 100, 200, 300, 400, 500, 600, 700,
907 					 1000, 2000, 4000, 8000, 16000, 32000,
908 					 64000, 128000 },
909 	.disable_channel = adc_tm5_disable_channel,
910 	.configure = adc_tm5_configure,
911 	.isr = adc_tm5_isr,
912 	.init = adc_tm5_init,
913 	.irq_name = "pm-adc-tm5",
914 	.gen = ADC_TM5,
915 };
916 
917 static const struct adc_tm5_data adc_tm_hc_data_pmic = {
918 	.full_scale_code_volt = 0x70e4,
919 	.decimation = (unsigned int []) { 256, 512, 1024 },
920 	.hw_settle = (unsigned int []) { 0, 100, 200, 300, 400, 500, 600, 700,
921 					 1000, 2000, 4000, 6000, 8000, 10000 },
922 	.disable_channel = adc_tm5_disable_channel,
923 	.configure = adc_tm5_configure,
924 	.isr = adc_tm5_isr,
925 	.init = adc_tm_hc_init,
926 	.irq_name = "pm-adc-tm5",
927 	.gen = ADC_TM_HC,
928 };
929 
930 static const struct adc_tm5_data adc_tm5_gen2_data_pmic = {
931 	.full_scale_code_volt = 0x70e4,
932 	.decimation = (unsigned int []) { 85, 340, 1360 },
933 	.hw_settle = (unsigned int []) { 15, 100, 200, 300, 400, 500, 600, 700,
934 					 1000, 2000, 4000, 8000, 16000, 32000,
935 					 64000, 128000 },
936 	.disable_channel = adc_tm5_gen2_disable_channel,
937 	.configure = adc_tm5_gen2_configure,
938 	.isr = adc_tm5_gen2_isr,
939 	.init = adc_tm5_gen2_init,
940 	.irq_name = "pm-adc-tm5-gen2",
941 	.gen = ADC_TM5_GEN2,
942 };
943 
944 static int adc_tm5_get_dt_data(struct adc_tm5_chip *adc_tm, struct device_node *node)
945 {
946 	struct adc_tm5_channel *channels;
947 	struct device_node *child;
948 	u32 value;
949 	int ret;
950 	struct device *dev = adc_tm->dev;
951 
952 	adc_tm->nchannels = of_get_available_child_count(node);
953 	if (!adc_tm->nchannels)
954 		return -EINVAL;
955 
956 	adc_tm->channels = devm_kcalloc(dev, adc_tm->nchannels,
957 					sizeof(*adc_tm->channels), GFP_KERNEL);
958 	if (!adc_tm->channels)
959 		return -ENOMEM;
960 
961 	channels = adc_tm->channels;
962 
963 	adc_tm->data = of_device_get_match_data(dev);
964 	if (!adc_tm->data)
965 		adc_tm->data = &adc_tm5_data_pmic;
966 
967 	ret = of_property_read_u32(node, "qcom,decimation", &value);
968 	if (!ret) {
969 		ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation);
970 		if (ret < 0) {
971 			dev_err(dev, "invalid decimation %d\n", value);
972 			return ret;
973 		}
974 		adc_tm->decimation = ret;
975 	} else {
976 		adc_tm->decimation = ADC5_DECIMATION_DEFAULT;
977 	}
978 
979 	ret = of_property_read_u32(node, "qcom,avg-samples", &value);
980 	if (!ret) {
981 		ret = qcom_adc5_avg_samples_from_dt(value);
982 		if (ret < 0) {
983 			dev_err(dev, "invalid avg-samples %d\n", value);
984 			return ret;
985 		}
986 		adc_tm->avg_samples = ret;
987 	} else {
988 		adc_tm->avg_samples = VADC_DEF_AVG_SAMPLES;
989 	}
990 
991 	for_each_available_child_of_node(node, child) {
992 		ret = adc_tm5_get_dt_channel_data(adc_tm, channels, child);
993 		if (ret) {
994 			of_node_put(child);
995 			return ret;
996 		}
997 
998 		channels++;
999 	}
1000 
1001 	return 0;
1002 }
1003 
1004 static int adc_tm5_probe(struct platform_device *pdev)
1005 {
1006 	struct device_node *node = pdev->dev.of_node;
1007 	struct device *dev = &pdev->dev;
1008 	struct adc_tm5_chip *adc_tm;
1009 	struct regmap *regmap;
1010 	int ret, irq;
1011 	u32 reg;
1012 
1013 	regmap = dev_get_regmap(dev->parent, NULL);
1014 	if (!regmap)
1015 		return -ENODEV;
1016 
1017 	ret = of_property_read_u32(node, "reg", &reg);
1018 	if (ret)
1019 		return ret;
1020 
1021 	adc_tm = devm_kzalloc(&pdev->dev, sizeof(*adc_tm), GFP_KERNEL);
1022 	if (!adc_tm)
1023 		return -ENOMEM;
1024 
1025 	adc_tm->regmap = regmap;
1026 	adc_tm->dev = dev;
1027 	adc_tm->base = reg;
1028 
1029 	irq = platform_get_irq(pdev, 0);
1030 	if (irq < 0)
1031 		return irq;
1032 
1033 	ret = adc_tm5_get_dt_data(adc_tm, node);
1034 	if (ret)
1035 		return dev_err_probe(dev, ret, "get dt data failed\n");
1036 
1037 	ret = adc_tm->data->init(adc_tm);
1038 	if (ret) {
1039 		dev_err(dev, "adc-tm init failed\n");
1040 		return ret;
1041 	}
1042 
1043 	ret = adc_tm5_register_tzd(adc_tm);
1044 	if (ret) {
1045 		dev_err(dev, "tzd register failed\n");
1046 		return ret;
1047 	}
1048 
1049 	return devm_request_threaded_irq(dev, irq, NULL, adc_tm->data->isr,
1050 			IRQF_ONESHOT, adc_tm->data->irq_name, adc_tm);
1051 }
1052 
1053 static const struct of_device_id adc_tm5_match_table[] = {
1054 	{
1055 		.compatible = "qcom,spmi-adc-tm5",
1056 		.data = &adc_tm5_data_pmic,
1057 	},
1058 	{
1059 		.compatible = "qcom,spmi-adc-tm-hc",
1060 		.data = &adc_tm_hc_data_pmic,
1061 	},
1062 	{
1063 		.compatible = "qcom,spmi-adc-tm5-gen2",
1064 		.data = &adc_tm5_gen2_data_pmic,
1065 	},
1066 	{ }
1067 };
1068 MODULE_DEVICE_TABLE(of, adc_tm5_match_table);
1069 
1070 static struct platform_driver adc_tm5_driver = {
1071 	.driver = {
1072 		.name = "qcom-spmi-adc-tm5",
1073 		.of_match_table = adc_tm5_match_table,
1074 	},
1075 	.probe = adc_tm5_probe,
1076 };
1077 module_platform_driver(adc_tm5_driver);
1078 
1079 MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver");
1080 MODULE_LICENSE("GPL v2");
1081