1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/debugfs.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of_device.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 #include <linux/thermal.h> 20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h> 21 22 #define LVTS_MONCTL0(__base) (__base + 0x0000) 23 #define LVTS_MONCTL1(__base) (__base + 0x0004) 24 #define LVTS_MONCTL2(__base) (__base + 0x0008) 25 #define LVTS_MONINT(__base) (__base + 0x000C) 26 #define LVTS_MONINTSTS(__base) (__base + 0x0010) 27 #define LVTS_MONIDET0(__base) (__base + 0x0014) 28 #define LVTS_MONIDET1(__base) (__base + 0x0018) 29 #define LVTS_MONIDET2(__base) (__base + 0x001C) 30 #define LVTS_MONIDET3(__base) (__base + 0x0020) 31 #define LVTS_H2NTHRE(__base) (__base + 0x0024) 32 #define LVTS_HTHRE(__base) (__base + 0x0028) 33 #define LVTS_OFFSETH(__base) (__base + 0x0030) 34 #define LVTS_OFFSETL(__base) (__base + 0x0034) 35 #define LVTS_MSRCTL0(__base) (__base + 0x0038) 36 #define LVTS_MSRCTL1(__base) (__base + 0x003C) 37 #define LVTS_TSSEL(__base) (__base + 0x0040) 38 #define LVTS_CALSCALE(__base) (__base + 0x0048) 39 #define LVTS_ID(__base) (__base + 0x004C) 40 #define LVTS_CONFIG(__base) (__base + 0x0050) 41 #define LVTS_EDATA00(__base) (__base + 0x0054) 42 #define LVTS_EDATA01(__base) (__base + 0x0058) 43 #define LVTS_EDATA02(__base) (__base + 0x005C) 44 #define LVTS_EDATA03(__base) (__base + 0x0060) 45 #define LVTS_MSR0(__base) (__base + 0x0090) 46 #define LVTS_MSR1(__base) (__base + 0x0094) 47 #define LVTS_MSR2(__base) (__base + 0x0098) 48 #define LVTS_MSR3(__base) (__base + 0x009C) 49 #define LVTS_IMMD0(__base) (__base + 0x00A0) 50 #define LVTS_IMMD1(__base) (__base + 0x00A4) 51 #define LVTS_IMMD2(__base) (__base + 0x00A8) 52 #define LVTS_IMMD3(__base) (__base + 0x00AC) 53 #define LVTS_PROTCTL(__base) (__base + 0x00C0) 54 #define LVTS_PROTTA(__base) (__base + 0x00C4) 55 #define LVTS_PROTTB(__base) (__base + 0x00C8) 56 #define LVTS_PROTTC(__base) (__base + 0x00CC) 57 #define LVTS_CLKEN(__base) (__base + 0x00E4) 58 59 #define LVTS_PERIOD_UNIT ((118 * 1000) / (256 * 38)) 60 #define LVTS_GROUP_INTERVAL 1 61 #define LVTS_FILTER_INTERVAL 1 62 #define LVTS_SENSOR_INTERVAL 1 63 #define LVTS_HW_FILTER 0x2 64 #define LVTS_TSSEL_CONF 0x13121110 65 #define LVTS_CALSCALE_CONF 0x300 66 #define LVTS_MONINT_CONF 0x9FBF7BDE 67 68 #define LVTS_INT_SENSOR0 0x0009001F 69 #define LVTS_INT_SENSOR1 0x001203E0 70 #define LVTS_INT_SENSOR2 0x00247C00 71 #define LVTS_INT_SENSOR3 0x1FC00000 72 73 #define LVTS_SENSOR_MAX 4 74 #define LVTS_GOLDEN_TEMP_MAX 62 75 #define LVTS_GOLDEN_TEMP_DEFAULT 50 76 #define LVTS_COEFF_A -250460 77 #define LVTS_COEFF_B 250460 78 79 #define LVTS_MSR_IMMEDIATE_MODE 0 80 #define LVTS_MSR_FILTERED_MODE 1 81 82 #define LVTS_HW_SHUTDOWN_MT8195 105000 83 84 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; 85 static int coeff_b = LVTS_COEFF_B; 86 87 struct lvts_sensor_data { 88 int dt_id; 89 }; 90 91 struct lvts_ctrl_data { 92 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; 93 int cal_offset[LVTS_SENSOR_MAX]; 94 int hw_tshut_temp; 95 int num_lvts_sensor; 96 int offset; 97 int mode; 98 }; 99 100 struct lvts_data { 101 const struct lvts_ctrl_data *lvts_ctrl; 102 int num_lvts_ctrl; 103 }; 104 105 struct lvts_sensor { 106 struct thermal_zone_device *tz; 107 void __iomem *msr; 108 void __iomem *base; 109 int id; 110 int dt_id; 111 }; 112 113 struct lvts_ctrl { 114 struct lvts_sensor sensors[LVTS_SENSOR_MAX]; 115 u32 calibration[LVTS_SENSOR_MAX]; 116 u32 hw_tshut_raw_temp; 117 int num_lvts_sensor; 118 int mode; 119 void __iomem *base; 120 }; 121 122 struct lvts_domain { 123 struct lvts_ctrl *lvts_ctrl; 124 struct reset_control *reset; 125 struct clk *clk; 126 int num_lvts_ctrl; 127 void __iomem *base; 128 size_t calib_len; 129 u8 *calib; 130 #ifdef CONFIG_DEBUG_FS 131 struct dentry *dom_dentry; 132 #endif 133 }; 134 135 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS 136 137 #define LVTS_DEBUG_FS_REGS(__reg) \ 138 { \ 139 .name = __stringify(__reg), \ 140 .offset = __reg(0), \ 141 } 142 143 static const struct debugfs_reg32 lvts_regs[] = { 144 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), 145 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), 146 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), 147 LVTS_DEBUG_FS_REGS(LVTS_MONINT), 148 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), 149 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), 150 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), 151 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), 152 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), 153 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), 154 LVTS_DEBUG_FS_REGS(LVTS_HTHRE), 155 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), 156 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), 157 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), 158 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), 159 LVTS_DEBUG_FS_REGS(LVTS_TSSEL), 160 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), 161 LVTS_DEBUG_FS_REGS(LVTS_ID), 162 LVTS_DEBUG_FS_REGS(LVTS_CONFIG), 163 LVTS_DEBUG_FS_REGS(LVTS_EDATA00), 164 LVTS_DEBUG_FS_REGS(LVTS_EDATA01), 165 LVTS_DEBUG_FS_REGS(LVTS_EDATA02), 166 LVTS_DEBUG_FS_REGS(LVTS_EDATA03), 167 LVTS_DEBUG_FS_REGS(LVTS_MSR0), 168 LVTS_DEBUG_FS_REGS(LVTS_MSR1), 169 LVTS_DEBUG_FS_REGS(LVTS_MSR2), 170 LVTS_DEBUG_FS_REGS(LVTS_MSR3), 171 LVTS_DEBUG_FS_REGS(LVTS_IMMD0), 172 LVTS_DEBUG_FS_REGS(LVTS_IMMD1), 173 LVTS_DEBUG_FS_REGS(LVTS_IMMD2), 174 LVTS_DEBUG_FS_REGS(LVTS_IMMD3), 175 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), 176 LVTS_DEBUG_FS_REGS(LVTS_PROTTA), 177 LVTS_DEBUG_FS_REGS(LVTS_PROTTB), 178 LVTS_DEBUG_FS_REGS(LVTS_PROTTC), 179 LVTS_DEBUG_FS_REGS(LVTS_CLKEN), 180 }; 181 182 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) 183 { 184 struct debugfs_regset32 *regset; 185 struct lvts_ctrl *lvts_ctrl; 186 struct dentry *dentry; 187 char name[64]; 188 int i; 189 190 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); 191 if (!lvts_td->dom_dentry) 192 return 0; 193 194 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 195 196 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 197 198 sprintf(name, "controller%d", i); 199 dentry = debugfs_create_dir(name, lvts_td->dom_dentry); 200 if (!dentry) 201 continue; 202 203 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 204 if (!regset) 205 continue; 206 207 regset->base = lvts_ctrl->base; 208 regset->regs = lvts_regs; 209 regset->nregs = ARRAY_SIZE(lvts_regs); 210 211 debugfs_create_regset32("registers", 0400, dentry, regset); 212 } 213 214 return 0; 215 } 216 217 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) 218 { 219 debugfs_remove_recursive(lvts_td->dom_dentry); 220 } 221 222 #else 223 224 static inline int lvts_debugfs_init(struct device *dev, 225 struct lvts_domain *lvts_td) 226 { 227 return 0; 228 } 229 230 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } 231 232 #endif 233 234 static int lvts_raw_to_temp(u32 raw_temp) 235 { 236 int temperature; 237 238 temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14; 239 temperature += coeff_b; 240 241 return temperature; 242 } 243 244 static u32 lvts_temp_to_raw(int temperature) 245 { 246 u32 raw_temp = ((s64)(coeff_b - temperature)) << 14; 247 248 raw_temp = div_s64(raw_temp, -LVTS_COEFF_A); 249 250 return raw_temp; 251 } 252 253 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) 254 { 255 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 256 void __iomem *msr = lvts_sensor->msr; 257 u32 value; 258 259 /* 260 * Measurement registers: 261 * 262 * LVTS_MSR[0-3] / LVTS_IMMD[0-3] 263 * 264 * Bits: 265 * 266 * 32-17: Unused 267 * 16 : Valid temperature 268 * 15-0 : Raw temperature 269 */ 270 value = readl(msr); 271 272 /* 273 * As the thermal zone temperature will read before the 274 * hardware sensor is fully initialized, we have to check the 275 * validity of the temperature returned when reading the 276 * measurement register. The thermal controller will set the 277 * valid bit temperature only when it is totally initialized. 278 * 279 * Otherwise, we may end up with garbage values out of the 280 * functionning temperature and directly jump to a system 281 * shutdown. 282 */ 283 if (!(value & BIT(16))) 284 return -EAGAIN; 285 286 *temp = lvts_raw_to_temp(value & 0xFFFF); 287 288 return 0; 289 } 290 291 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) 292 { 293 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 294 void __iomem *base = lvts_sensor->base; 295 u32 raw_low = lvts_temp_to_raw(low); 296 u32 raw_high = lvts_temp_to_raw(high); 297 298 /* 299 * Hot to normal temperature threshold 300 * 301 * LVTS_H2NTHRE 302 * 303 * Bits: 304 * 305 * 14-0 : Raw temperature for threshold 306 */ 307 if (low != -INT_MAX) { 308 pr_debug("%s: Setting low limit temperature interrupt: %d\n", 309 thermal_zone_device_type(tz), low); 310 writel(raw_low, LVTS_H2NTHRE(base)); 311 } 312 313 /* 314 * Hot temperature threshold 315 * 316 * LVTS_HTHRE 317 * 318 * Bits: 319 * 320 * 14-0 : Raw temperature for threshold 321 */ 322 pr_debug("%s: Setting high limit temperature interrupt: %d\n", 323 thermal_zone_device_type(tz), high); 324 writel(raw_high, LVTS_HTHRE(base)); 325 326 return 0; 327 } 328 329 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) 330 { 331 irqreturn_t iret = IRQ_NONE; 332 u32 value; 333 u32 masks[] = { 334 LVTS_INT_SENSOR0, 335 LVTS_INT_SENSOR1, 336 LVTS_INT_SENSOR2, 337 LVTS_INT_SENSOR3 338 }; 339 int i; 340 341 /* 342 * Interrupt monitoring status 343 * 344 * LVTS_MONINTST 345 * 346 * Bits: 347 * 348 * 31 : Interrupt for stage 3 349 * 30 : Interrupt for stage 2 350 * 29 : Interrupt for state 1 351 * 28 : Interrupt using filter on sensor 3 352 * 353 * 27 : Interrupt using immediate on sensor 3 354 * 26 : Interrupt normal to hot on sensor 3 355 * 25 : Interrupt high offset on sensor 3 356 * 24 : Interrupt low offset on sensor 3 357 * 358 * 23 : Interrupt hot threshold on sensor 3 359 * 22 : Interrupt cold threshold on sensor 3 360 * 21 : Interrupt using filter on sensor 2 361 * 20 : Interrupt using filter on sensor 1 362 * 363 * 19 : Interrupt using filter on sensor 0 364 * 18 : Interrupt using immediate on sensor 2 365 * 17 : Interrupt using immediate on sensor 1 366 * 16 : Interrupt using immediate on sensor 0 367 * 368 * 15 : Interrupt device access timeout interrupt 369 * 14 : Interrupt normal to hot on sensor 2 370 * 13 : Interrupt high offset interrupt on sensor 2 371 * 12 : Interrupt low offset interrupt on sensor 2 372 * 373 * 11 : Interrupt hot threshold on sensor 2 374 * 10 : Interrupt cold threshold on sensor 2 375 * 9 : Interrupt normal to hot on sensor 1 376 * 8 : Interrupt high offset interrupt on sensor 1 377 * 378 * 7 : Interrupt low offset interrupt on sensor 1 379 * 6 : Interrupt hot threshold on sensor 1 380 * 5 : Interrupt cold threshold on sensor 1 381 * 4 : Interrupt normal to hot on sensor 0 382 * 383 * 3 : Interrupt high offset interrupt on sensor 0 384 * 2 : Interrupt low offset interrupt on sensor 0 385 * 1 : Interrupt hot threshold on sensor 0 386 * 0 : Interrupt cold threshold on sensor 0 387 * 388 * We are interested in the sensor(s) responsible of the 389 * interrupt event. We update the thermal framework with the 390 * thermal zone associated with the sensor. The framework will 391 * take care of the rest whatever the kind of interrupt, we 392 * are only interested in which sensor raised the interrupt. 393 * 394 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 395 * => 0x1FC00000 396 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 397 * => 0x00247C00 398 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 399 * => 0X001203E0 400 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 401 * => 0x0009001F 402 */ 403 value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); 404 405 /* 406 * Let's figure out which sensors raised the interrupt 407 * 408 * NOTE: the masks array must be ordered with the index 409 * corresponding to the sensor id eg. index=0, mask for 410 * sensor0. 411 */ 412 for (i = 0; i < ARRAY_SIZE(masks); i++) { 413 414 if (!(value & masks[i])) 415 continue; 416 417 thermal_zone_device_update(lvts_ctrl->sensors[i].tz, 418 THERMAL_TRIP_VIOLATED); 419 iret = IRQ_HANDLED; 420 } 421 422 /* 423 * Write back to clear the interrupt status (W1C) 424 */ 425 writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); 426 427 return iret; 428 } 429 430 /* 431 * Temperature interrupt handler. Even if the driver supports more 432 * interrupt modes, we use the interrupt when the temperature crosses 433 * the hot threshold the way up and the way down (modulo the 434 * hysteresis). 435 * 436 * Each thermal domain has a couple of interrupts, one for hardware 437 * reset and another one for all the thermal events happening on the 438 * different sensors. 439 * 440 * The interrupt is configured for thermal events when crossing the 441 * hot temperature limit. At each interrupt, we check in every 442 * controller if there is an interrupt pending. 443 */ 444 static irqreturn_t lvts_irq_handler(int irq, void *data) 445 { 446 struct lvts_domain *lvts_td = data; 447 irqreturn_t aux, iret = IRQ_NONE; 448 int i; 449 450 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 451 452 aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl); 453 if (aux != IRQ_HANDLED) 454 continue; 455 456 iret = IRQ_HANDLED; 457 } 458 459 return iret; 460 } 461 462 static struct thermal_zone_device_ops lvts_ops = { 463 .get_temp = lvts_get_temp, 464 .set_trips = lvts_set_trips, 465 }; 466 467 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 468 const struct lvts_ctrl_data *lvts_ctrl_data) 469 { 470 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; 471 void __iomem *msr_regs[] = { 472 LVTS_MSR0(lvts_ctrl->base), 473 LVTS_MSR1(lvts_ctrl->base), 474 LVTS_MSR2(lvts_ctrl->base), 475 LVTS_MSR3(lvts_ctrl->base) 476 }; 477 478 void __iomem *imm_regs[] = { 479 LVTS_IMMD0(lvts_ctrl->base), 480 LVTS_IMMD1(lvts_ctrl->base), 481 LVTS_IMMD2(lvts_ctrl->base), 482 LVTS_IMMD3(lvts_ctrl->base) 483 }; 484 485 int i; 486 487 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { 488 489 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; 490 491 /* 492 * At this point, we don't know which id matches which 493 * sensor. Let's set arbitrally the id from the index. 494 */ 495 lvts_sensor[i].id = i; 496 497 /* 498 * The thermal zone registration will set the trip 499 * point interrupt in the thermal controller 500 * register. But this one will be reset in the 501 * initialization after. So we need to post pone the 502 * thermal zone creation after the controller is 503 * setup. For this reason, we store the device tree 504 * node id from the data in the sensor structure 505 */ 506 lvts_sensor[i].dt_id = dt_id; 507 508 /* 509 * We assign the base address of the thermal 510 * controller as a back pointer. So it will be 511 * accessible from the different thermal framework ops 512 * as we pass the lvts_sensor pointer as thermal zone 513 * private data. 514 */ 515 lvts_sensor[i].base = lvts_ctrl->base; 516 517 /* 518 * Each sensor has its own register address to read from. 519 */ 520 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? 521 imm_regs[i] : msr_regs[i]; 522 }; 523 524 lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; 525 526 return 0; 527 } 528 529 /* 530 * The efuse blob values follows the sensor enumeration per thermal 531 * controller. The decoding of the stream is as follow: 532 * 533 * stream index map for MCU Domain : 534 * 535 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 536 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 537 * 538 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 539 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 540 * 541 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 542 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 543 * 544 * stream index map for AP Domain : 545 * 546 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 547 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A 548 * 549 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 550 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 551 * 552 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> 553 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F 554 * 555 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> 556 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 557 * 558 * The data description gives the offset of the calibration data in 559 * this bytes stream for each sensor. 560 */ 561 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 562 const struct lvts_ctrl_data *lvts_ctrl_data, 563 u8 *efuse_calibration) 564 { 565 int i; 566 567 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) 568 memcpy(&lvts_ctrl->calibration[i], 569 efuse_calibration + lvts_ctrl_data->cal_offset[i], 2); 570 571 return 0; 572 } 573 574 /* 575 * The efuse bytes stream can be split into different chunk of 576 * nvmems. This function reads and concatenate those into a single 577 * buffer so it can be read sequentially when initializing the 578 * calibration data. 579 */ 580 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, 581 const struct lvts_data *lvts_data) 582 { 583 struct device_node *np = dev_of_node(dev); 584 struct nvmem_cell *cell; 585 struct property *prop; 586 const char *cell_name; 587 588 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { 589 size_t len; 590 u8 *efuse; 591 592 cell = of_nvmem_cell_get(np, cell_name); 593 if (IS_ERR(cell)) { 594 dev_err(dev, "Failed to get cell '%s'\n", cell_name); 595 return PTR_ERR(cell); 596 } 597 598 efuse = nvmem_cell_read(cell, &len); 599 600 nvmem_cell_put(cell); 601 602 if (IS_ERR(efuse)) { 603 dev_err(dev, "Failed to read cell '%s'\n", cell_name); 604 return PTR_ERR(efuse); 605 } 606 607 lvts_td->calib = devm_krealloc(dev, lvts_td->calib, 608 lvts_td->calib_len + len, GFP_KERNEL); 609 if (!lvts_td->calib) 610 return -ENOMEM; 611 612 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); 613 614 lvts_td->calib_len += len; 615 616 kfree(efuse); 617 } 618 619 return 0; 620 } 621 622 static int lvts_golden_temp_init(struct device *dev, u32 *value) 623 { 624 u32 gt; 625 626 gt = (*value) >> 24; 627 628 if (gt && gt < LVTS_GOLDEN_TEMP_MAX) 629 golden_temp = gt; 630 631 coeff_b = golden_temp * 500 + LVTS_COEFF_B; 632 633 return 0; 634 } 635 636 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, 637 const struct lvts_data *lvts_data) 638 { 639 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; 640 struct lvts_ctrl *lvts_ctrl; 641 int i, ret; 642 643 /* 644 * Create the calibration bytes stream from efuse data 645 */ 646 ret = lvts_calibration_read(dev, lvts_td, lvts_data); 647 if (ret) 648 return ret; 649 650 /* 651 * The golden temp information is contained in the first chunk 652 * of efuse data. 653 */ 654 ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib); 655 if (ret) 656 return ret; 657 658 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); 659 if (!lvts_ctrl) 660 return -ENOMEM; 661 662 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { 663 664 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; 665 666 ret = lvts_sensor_init(dev, &lvts_ctrl[i], 667 &lvts_data->lvts_ctrl[i]); 668 if (ret) 669 return ret; 670 671 ret = lvts_calibration_init(dev, &lvts_ctrl[i], 672 &lvts_data->lvts_ctrl[i], 673 lvts_td->calib); 674 if (ret) 675 return ret; 676 677 /* 678 * The mode the ctrl will use to read the temperature 679 * (filtered or immediate) 680 */ 681 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; 682 683 /* 684 * The temperature to raw temperature must be done 685 * after initializing the calibration. 686 */ 687 lvts_ctrl[i].hw_tshut_raw_temp = 688 lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp); 689 } 690 691 /* 692 * We no longer need the efuse bytes stream, let's free it 693 */ 694 devm_kfree(dev, lvts_td->calib); 695 696 lvts_td->lvts_ctrl = lvts_ctrl; 697 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; 698 699 return 0; 700 } 701 702 /* 703 * At this point the configuration register is the only place in the 704 * driver where we write multiple values. Per hardware constraint, 705 * each write in the configuration register must be separated by a 706 * delay of 2 us. 707 */ 708 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) 709 { 710 int i; 711 712 /* 713 * Configuration register 714 */ 715 for (i = 0; i < nr_cmds; i++) { 716 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); 717 usleep_range(2, 4); 718 } 719 } 720 721 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) 722 { 723 /* 724 * LVTS_PROTCTL : Thermal Protection Sensor Selection 725 * 726 * Bits: 727 * 728 * 19-18 : Sensor to base the protection on 729 * 17-16 : Strategy: 730 * 00 : Average of 4 sensors 731 * 01 : Max of 4 sensors 732 * 10 : Selected sensor with bits 19-18 733 * 11 : Reserved 734 */ 735 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); 736 737 /* 738 * LVTS_PROTTA : Stage 1 temperature threshold 739 * LVTS_PROTTB : Stage 2 temperature threshold 740 * LVTS_PROTTC : Stage 3 temperature threshold 741 * 742 * Bits: 743 * 744 * 14-0: Raw temperature threshold 745 * 746 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); 747 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); 748 */ 749 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); 750 751 /* 752 * LVTS_MONINT : Interrupt configuration register 753 * 754 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS 755 * register, except we set the bits to enable the interrupt. 756 */ 757 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); 758 759 return 0; 760 } 761 762 static int lvts_domain_reset(struct device *dev, struct reset_control *reset) 763 { 764 int ret; 765 766 ret = reset_control_assert(reset); 767 if (ret) 768 return ret; 769 770 return reset_control_deassert(reset); 771 } 772 773 /* 774 * Enable or disable the clocks of a specified thermal controller 775 */ 776 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) 777 { 778 /* 779 * LVTS_CLKEN : Internal LVTS clock 780 * 781 * Bits: 782 * 783 * 0 : enable / disable clock 784 */ 785 writel(enable, LVTS_CLKEN(lvts_ctrl->base)); 786 787 return 0; 788 } 789 790 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) 791 { 792 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; 793 794 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 795 796 /* 797 * LVTS_ID : Get ID and status of the thermal controller 798 * 799 * Bits: 800 * 801 * 0-5 : thermal controller id 802 * 7 : thermal controller connection is valid 803 */ 804 id = readl(LVTS_ID(lvts_ctrl->base)); 805 if (!(id & BIT(7))) 806 return -EIO; 807 808 return 0; 809 } 810 811 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) 812 { 813 /* 814 * Write device mask: 0xC1030000 815 */ 816 u32 cmds[] = { 817 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 818 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, 819 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, 820 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 821 }; 822 823 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 824 825 return 0; 826 } 827 828 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) 829 { 830 int i; 831 void __iomem *lvts_edata[] = { 832 LVTS_EDATA00(lvts_ctrl->base), 833 LVTS_EDATA01(lvts_ctrl->base), 834 LVTS_EDATA02(lvts_ctrl->base), 835 LVTS_EDATA03(lvts_ctrl->base) 836 }; 837 838 /* 839 * LVTS_EDATA0X : Efuse calibration reference value for sensor X 840 * 841 * Bits: 842 * 843 * 20-0 : Efuse value for normalization data 844 */ 845 for (i = 0; i < LVTS_SENSOR_MAX; i++) 846 writel(lvts_ctrl->calibration[i], lvts_edata[i]); 847 848 return 0; 849 } 850 851 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) 852 { 853 u32 value; 854 855 /* 856 * LVTS_TSSEL : Sensing point index numbering 857 * 858 * Bits: 859 * 860 * 31-24: ADC Sense 3 861 * 23-16: ADC Sense 2 862 * 15-8 : ADC Sense 1 863 * 7-0 : ADC Sense 0 864 */ 865 value = LVTS_TSSEL_CONF; 866 writel(value, LVTS_TSSEL(lvts_ctrl->base)); 867 868 /* 869 * LVTS_CALSCALE : ADC voltage round 870 */ 871 value = 0x300; 872 value = LVTS_CALSCALE_CONF; 873 874 /* 875 * LVTS_MSRCTL0 : Sensor filtering strategy 876 * 877 * Filters: 878 * 879 * 000 : One sample 880 * 001 : Avg 2 samples 881 * 010 : 4 samples, drop min and max, avg 2 samples 882 * 011 : 6 samples, drop min and max, avg 4 samples 883 * 100 : 10 samples, drop min and max, avg 8 samples 884 * 101 : 18 samples, drop min and max, avg 16 samples 885 * 886 * Bits: 887 * 888 * 0-2 : Sensor0 filter 889 * 3-5 : Sensor1 filter 890 * 6-8 : Sensor2 filter 891 * 9-11 : Sensor3 filter 892 */ 893 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | 894 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; 895 writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); 896 897 /* 898 * LVTS_MSRCTL1 : Measurement control 899 * 900 * Bits: 901 * 902 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 903 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 904 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 905 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 906 * 907 * That configuration will ignore the filtering and the delays 908 * introduced below in MONCTL1 and MONCTL2 909 */ 910 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { 911 value = BIT(9) | BIT(6) | BIT(5) | BIT(4); 912 writel(value, LVTS_MSRCTL1(lvts_ctrl->base)); 913 } 914 915 /* 916 * LVTS_MONCTL1 : Period unit and group interval configuration 917 * 918 * The clock source of LVTS thermal controller is 26MHz. 919 * 920 * The period unit is a time base for all the interval delays 921 * specified in the registers. By default we use 12. The time 922 * conversion is done by multiplying by 256 and 1/26.10^6 923 * 924 * An interval delay multiplied by the period unit gives the 925 * duration in seconds. 926 * 927 * - Filter interval delay is a delay between two samples of 928 * the same sensor. 929 * 930 * - Sensor interval delay is a delay between two samples of 931 * different sensors. 932 * 933 * - Group interval delay is a delay between different rounds. 934 * 935 * For example: 936 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, 937 * and two sensors, TS1 and TS2, are in a LVTS thermal controller 938 * and then 939 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us 940 * Filter interval delay = 1 * Period unit = 118.149us 941 * Sensor interval delay = 2 * Period unit = 236.298us 942 * Group interval delay = 1 * Period unit = 118.149us 943 * 944 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... 945 * <--> Filter interval delay 946 * <--> Sensor interval delay 947 * <--> Group interval delay 948 * Bits: 949 * 29 - 20 : Group interval 950 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) 951 * or an interrupt everytime the hot threshold is crossed (0) 952 * 9 - 0 : Period unit 953 * 954 */ 955 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; 956 writel(value, LVTS_MONCTL1(lvts_ctrl->base)); 957 958 /* 959 * LVTS_MONCTL2 : Filtering and sensor interval 960 * 961 * Bits: 962 * 963 * 25-16 : Interval unit in PERIOD_UNIT between sample on 964 * the same sensor, filter interval 965 * 9-0 : Interval unit in PERIOD_UNIT between each sensor 966 * 967 */ 968 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; 969 writel(value, LVTS_MONCTL2(lvts_ctrl->base)); 970 971 return lvts_irq_init(lvts_ctrl); 972 } 973 974 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) 975 { 976 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; 977 struct thermal_zone_device *tz; 978 u32 sensor_map = 0; 979 int i; 980 981 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { 982 983 int dt_id = lvts_sensors[i].dt_id; 984 985 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], 986 &lvts_ops); 987 if (IS_ERR(tz)) { 988 /* 989 * This thermal zone is not described in the 990 * device tree. It is not an error from the 991 * thermal OF code POV, we just continue. 992 */ 993 if (PTR_ERR(tz) == -ENODEV) 994 continue; 995 996 return PTR_ERR(tz); 997 } 998 999 /* 1000 * The thermal zone pointer will be needed in the 1001 * interrupt handler, we store it in the sensor 1002 * structure. The thermal domain structure will be 1003 * passed to the interrupt handler private data as the 1004 * interrupt is shared for all the controller 1005 * belonging to the thermal domain. 1006 */ 1007 lvts_sensors[i].tz = tz; 1008 1009 /* 1010 * This sensor was correctly associated with a thermal 1011 * zone, let's set the corresponding bit in the sensor 1012 * map, so we can enable the temperature monitoring in 1013 * the hardware thermal controller. 1014 */ 1015 sensor_map |= BIT(i); 1016 } 1017 1018 /* 1019 * Bits: 1020 * 9: Single point access flow 1021 * 0-3: Enable sensing point 0-3 1022 * 1023 * The initialization of the thermal zones give us 1024 * which sensor point to enable. If any thermal zone 1025 * was not described in the device tree, it won't be 1026 * enabled here in the sensor map. 1027 */ 1028 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 1029 1030 return 0; 1031 } 1032 1033 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, 1034 const struct lvts_data *lvts_data) 1035 { 1036 struct lvts_ctrl *lvts_ctrl; 1037 int i, ret; 1038 1039 ret = lvts_ctrl_init(dev, lvts_td, lvts_data); 1040 if (ret) 1041 return ret; 1042 1043 ret = lvts_domain_reset(dev, lvts_td->reset); 1044 if (ret) { 1045 dev_dbg(dev, "Failed to reset domain"); 1046 return ret; 1047 } 1048 1049 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1050 1051 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 1052 1053 /* 1054 * Initialization steps: 1055 * 1056 * - Enable the clock 1057 * - Connect to the LVTS 1058 * - Initialize the LVTS 1059 * - Prepare the calibration data 1060 * - Select monitored sensors 1061 * [ Configure sampling ] 1062 * [ Configure the interrupt ] 1063 * - Start measurement 1064 */ 1065 ret = lvts_ctrl_set_enable(lvts_ctrl, true); 1066 if (ret) { 1067 dev_dbg(dev, "Failed to enable LVTS clock"); 1068 return ret; 1069 } 1070 1071 ret = lvts_ctrl_connect(dev, lvts_ctrl); 1072 if (ret) { 1073 dev_dbg(dev, "Failed to connect to LVTS controller"); 1074 return ret; 1075 } 1076 1077 ret = lvts_ctrl_initialize(dev, lvts_ctrl); 1078 if (ret) { 1079 dev_dbg(dev, "Failed to initialize controller"); 1080 return ret; 1081 } 1082 1083 ret = lvts_ctrl_calibrate(dev, lvts_ctrl); 1084 if (ret) { 1085 dev_dbg(dev, "Failed to calibrate controller"); 1086 return ret; 1087 } 1088 1089 ret = lvts_ctrl_configure(dev, lvts_ctrl); 1090 if (ret) { 1091 dev_dbg(dev, "Failed to configure controller"); 1092 return ret; 1093 } 1094 1095 ret = lvts_ctrl_start(dev, lvts_ctrl); 1096 if (ret) { 1097 dev_dbg(dev, "Failed to start controller"); 1098 return ret; 1099 } 1100 } 1101 1102 return lvts_debugfs_init(dev, lvts_td); 1103 } 1104 1105 static int lvts_probe(struct platform_device *pdev) 1106 { 1107 const struct lvts_data *lvts_data; 1108 struct lvts_domain *lvts_td; 1109 struct device *dev = &pdev->dev; 1110 struct resource *res; 1111 int irq, ret; 1112 1113 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); 1114 if (!lvts_td) 1115 return -ENOMEM; 1116 1117 lvts_data = of_device_get_match_data(dev); 1118 1119 lvts_td->clk = devm_clk_get_enabled(dev, NULL); 1120 if (IS_ERR(lvts_td->clk)) 1121 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); 1122 1123 res = platform_get_mem_or_io(pdev, 0); 1124 if (!res) 1125 return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); 1126 1127 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1128 if (IS_ERR(lvts_td->base)) 1129 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); 1130 1131 lvts_td->reset = devm_reset_control_get_by_index(dev, 0); 1132 if (IS_ERR(lvts_td->reset)) 1133 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); 1134 1135 irq = platform_get_irq(pdev, 0); 1136 if (irq < 0) 1137 return dev_err_probe(dev, irq, "No irq resource\n"); 1138 1139 ret = lvts_domain_init(dev, lvts_td, lvts_data); 1140 if (ret) 1141 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); 1142 1143 /* 1144 * At this point the LVTS is initialized and enabled. We can 1145 * safely enable the interrupt. 1146 */ 1147 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, 1148 IRQF_ONESHOT, dev_name(dev), lvts_td); 1149 if (ret) 1150 return dev_err_probe(dev, ret, "Failed to request interrupt\n"); 1151 1152 platform_set_drvdata(pdev, lvts_td); 1153 1154 return 0; 1155 } 1156 1157 static int lvts_remove(struct platform_device *pdev) 1158 { 1159 struct lvts_domain *lvts_td; 1160 int i; 1161 1162 lvts_td = platform_get_drvdata(pdev); 1163 1164 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1165 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1166 1167 lvts_debugfs_exit(lvts_td); 1168 1169 return 0; 1170 } 1171 1172 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { 1173 { 1174 .cal_offset = { 0x04, 0x07 }, 1175 .lvts_sensor = { 1176 { .dt_id = MT8195_MCU_BIG_CPU0 }, 1177 { .dt_id = MT8195_MCU_BIG_CPU1 } 1178 }, 1179 .num_lvts_sensor = 2, 1180 .offset = 0x0, 1181 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1182 }, 1183 { 1184 .cal_offset = { 0x0d, 0x10 }, 1185 .lvts_sensor = { 1186 { .dt_id = MT8195_MCU_BIG_CPU2 }, 1187 { .dt_id = MT8195_MCU_BIG_CPU3 } 1188 }, 1189 .num_lvts_sensor = 2, 1190 .offset = 0x100, 1191 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1192 }, 1193 { 1194 .cal_offset = { 0x16, 0x19, 0x1c, 0x1f }, 1195 .lvts_sensor = { 1196 { .dt_id = MT8195_MCU_LITTLE_CPU0 }, 1197 { .dt_id = MT8195_MCU_LITTLE_CPU1 }, 1198 { .dt_id = MT8195_MCU_LITTLE_CPU2 }, 1199 { .dt_id = MT8195_MCU_LITTLE_CPU3 } 1200 }, 1201 .num_lvts_sensor = 4, 1202 .offset = 0x200, 1203 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1204 } 1205 }; 1206 1207 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { 1208 { 1209 .cal_offset = { 0x25, 0x28 }, 1210 .lvts_sensor = { 1211 { .dt_id = MT8195_AP_VPU0 }, 1212 { .dt_id = MT8195_AP_VPU1 } 1213 }, 1214 .num_lvts_sensor = 2, 1215 .offset = 0x0, 1216 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1217 }, 1218 { 1219 .cal_offset = { 0x2e, 0x31 }, 1220 .lvts_sensor = { 1221 { .dt_id = MT8195_AP_GPU0 }, 1222 { .dt_id = MT8195_AP_GPU1 } 1223 }, 1224 .num_lvts_sensor = 2, 1225 .offset = 0x100, 1226 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1227 }, 1228 { 1229 .cal_offset = { 0x37, 0x3a, 0x3d }, 1230 .lvts_sensor = { 1231 { .dt_id = MT8195_AP_VDEC }, 1232 { .dt_id = MT8195_AP_IMG }, 1233 { .dt_id = MT8195_AP_INFRA }, 1234 }, 1235 .num_lvts_sensor = 3, 1236 .offset = 0x200, 1237 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1238 }, 1239 { 1240 .cal_offset = { 0x43, 0x46 }, 1241 .lvts_sensor = { 1242 { .dt_id = MT8195_AP_CAM0 }, 1243 { .dt_id = MT8195_AP_CAM1 } 1244 }, 1245 .num_lvts_sensor = 2, 1246 .offset = 0x300, 1247 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1248 } 1249 }; 1250 1251 static const struct lvts_data mt8195_lvts_mcu_data = { 1252 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, 1253 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), 1254 }; 1255 1256 static const struct lvts_data mt8195_lvts_ap_data = { 1257 .lvts_ctrl = mt8195_lvts_ap_data_ctrl, 1258 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), 1259 }; 1260 1261 static const struct of_device_id lvts_of_match[] = { 1262 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, 1263 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, 1264 {}, 1265 }; 1266 MODULE_DEVICE_TABLE(of, lvts_of_match); 1267 1268 static struct platform_driver lvts_driver = { 1269 .probe = lvts_probe, 1270 .remove = lvts_remove, 1271 .driver = { 1272 .name = "mtk-lvts-thermal", 1273 .of_match_table = lvts_of_match, 1274 }, 1275 }; 1276 module_platform_driver(lvts_driver); 1277 1278 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>"); 1279 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); 1280 MODULE_LICENSE("GPL"); 1281