1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/debugfs.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 #include <linux/thermal.h> 20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h> 21 22 #include "../thermal_hwmon.h" 23 24 #define LVTS_MONCTL0(__base) (__base + 0x0000) 25 #define LVTS_MONCTL1(__base) (__base + 0x0004) 26 #define LVTS_MONCTL2(__base) (__base + 0x0008) 27 #define LVTS_MONINT(__base) (__base + 0x000C) 28 #define LVTS_MONINTSTS(__base) (__base + 0x0010) 29 #define LVTS_MONIDET0(__base) (__base + 0x0014) 30 #define LVTS_MONIDET1(__base) (__base + 0x0018) 31 #define LVTS_MONIDET2(__base) (__base + 0x001C) 32 #define LVTS_MONIDET3(__base) (__base + 0x0020) 33 #define LVTS_H2NTHRE(__base) (__base + 0x0024) 34 #define LVTS_HTHRE(__base) (__base + 0x0028) 35 #define LVTS_OFFSETH(__base) (__base + 0x0030) 36 #define LVTS_OFFSETL(__base) (__base + 0x0034) 37 #define LVTS_MSRCTL0(__base) (__base + 0x0038) 38 #define LVTS_MSRCTL1(__base) (__base + 0x003C) 39 #define LVTS_TSSEL(__base) (__base + 0x0040) 40 #define LVTS_CALSCALE(__base) (__base + 0x0048) 41 #define LVTS_ID(__base) (__base + 0x004C) 42 #define LVTS_CONFIG(__base) (__base + 0x0050) 43 #define LVTS_EDATA00(__base) (__base + 0x0054) 44 #define LVTS_EDATA01(__base) (__base + 0x0058) 45 #define LVTS_EDATA02(__base) (__base + 0x005C) 46 #define LVTS_EDATA03(__base) (__base + 0x0060) 47 #define LVTS_MSR0(__base) (__base + 0x0090) 48 #define LVTS_MSR1(__base) (__base + 0x0094) 49 #define LVTS_MSR2(__base) (__base + 0x0098) 50 #define LVTS_MSR3(__base) (__base + 0x009C) 51 #define LVTS_IMMD0(__base) (__base + 0x00A0) 52 #define LVTS_IMMD1(__base) (__base + 0x00A4) 53 #define LVTS_IMMD2(__base) (__base + 0x00A8) 54 #define LVTS_IMMD3(__base) (__base + 0x00AC) 55 #define LVTS_PROTCTL(__base) (__base + 0x00C0) 56 #define LVTS_PROTTA(__base) (__base + 0x00C4) 57 #define LVTS_PROTTB(__base) (__base + 0x00C8) 58 #define LVTS_PROTTC(__base) (__base + 0x00CC) 59 #define LVTS_CLKEN(__base) (__base + 0x00E4) 60 61 #define LVTS_PERIOD_UNIT 0 62 #define LVTS_GROUP_INTERVAL 0 63 #define LVTS_FILTER_INTERVAL 0 64 #define LVTS_SENSOR_INTERVAL 0 65 #define LVTS_HW_FILTER 0x0 66 #define LVTS_TSSEL_CONF 0x13121110 67 #define LVTS_CALSCALE_CONF 0x300 68 #define LVTS_MONINT_CONF 0x8300318C 69 70 #define LVTS_MONINT_OFFSET_SENSOR0 0xC 71 #define LVTS_MONINT_OFFSET_SENSOR1 0x180 72 #define LVTS_MONINT_OFFSET_SENSOR2 0x3000 73 #define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 74 75 #define LVTS_INT_SENSOR0 0x0009001F 76 #define LVTS_INT_SENSOR1 0x001203E0 77 #define LVTS_INT_SENSOR2 0x00247C00 78 #define LVTS_INT_SENSOR3 0x1FC00000 79 80 #define LVTS_SENSOR_MAX 4 81 #define LVTS_GOLDEN_TEMP_MAX 62 82 #define LVTS_GOLDEN_TEMP_DEFAULT 50 83 #define LVTS_COEFF_A -250460 84 #define LVTS_COEFF_B 250460 85 86 #define LVTS_MSR_IMMEDIATE_MODE 0 87 #define LVTS_MSR_FILTERED_MODE 1 88 89 #define LVTS_MSR_READ_TIMEOUT_US 400 90 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) 91 92 #define LVTS_HW_SHUTDOWN_MT8195 105000 93 94 #define LVTS_MINIMUM_THRESHOLD 20000 95 96 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; 97 static int coeff_b = LVTS_COEFF_B; 98 99 struct lvts_sensor_data { 100 int dt_id; 101 }; 102 103 struct lvts_ctrl_data { 104 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; 105 int cal_offset[LVTS_SENSOR_MAX]; 106 int hw_tshut_temp; 107 int num_lvts_sensor; 108 int offset; 109 int mode; 110 }; 111 112 struct lvts_data { 113 const struct lvts_ctrl_data *lvts_ctrl; 114 int num_lvts_ctrl; 115 }; 116 117 struct lvts_sensor { 118 struct thermal_zone_device *tz; 119 void __iomem *msr; 120 void __iomem *base; 121 int id; 122 int dt_id; 123 int low_thresh; 124 int high_thresh; 125 }; 126 127 struct lvts_ctrl { 128 struct lvts_sensor sensors[LVTS_SENSOR_MAX]; 129 u32 calibration[LVTS_SENSOR_MAX]; 130 u32 hw_tshut_raw_temp; 131 int num_lvts_sensor; 132 int mode; 133 void __iomem *base; 134 int low_thresh; 135 int high_thresh; 136 }; 137 138 struct lvts_domain { 139 struct lvts_ctrl *lvts_ctrl; 140 struct reset_control *reset; 141 struct clk *clk; 142 int num_lvts_ctrl; 143 void __iomem *base; 144 size_t calib_len; 145 u8 *calib; 146 #ifdef CONFIG_DEBUG_FS 147 struct dentry *dom_dentry; 148 #endif 149 }; 150 151 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS 152 153 #define LVTS_DEBUG_FS_REGS(__reg) \ 154 { \ 155 .name = __stringify(__reg), \ 156 .offset = __reg(0), \ 157 } 158 159 static const struct debugfs_reg32 lvts_regs[] = { 160 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), 161 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), 162 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), 163 LVTS_DEBUG_FS_REGS(LVTS_MONINT), 164 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), 165 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), 166 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), 167 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), 168 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), 169 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), 170 LVTS_DEBUG_FS_REGS(LVTS_HTHRE), 171 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), 172 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), 173 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), 174 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), 175 LVTS_DEBUG_FS_REGS(LVTS_TSSEL), 176 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), 177 LVTS_DEBUG_FS_REGS(LVTS_ID), 178 LVTS_DEBUG_FS_REGS(LVTS_CONFIG), 179 LVTS_DEBUG_FS_REGS(LVTS_EDATA00), 180 LVTS_DEBUG_FS_REGS(LVTS_EDATA01), 181 LVTS_DEBUG_FS_REGS(LVTS_EDATA02), 182 LVTS_DEBUG_FS_REGS(LVTS_EDATA03), 183 LVTS_DEBUG_FS_REGS(LVTS_MSR0), 184 LVTS_DEBUG_FS_REGS(LVTS_MSR1), 185 LVTS_DEBUG_FS_REGS(LVTS_MSR2), 186 LVTS_DEBUG_FS_REGS(LVTS_MSR3), 187 LVTS_DEBUG_FS_REGS(LVTS_IMMD0), 188 LVTS_DEBUG_FS_REGS(LVTS_IMMD1), 189 LVTS_DEBUG_FS_REGS(LVTS_IMMD2), 190 LVTS_DEBUG_FS_REGS(LVTS_IMMD3), 191 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), 192 LVTS_DEBUG_FS_REGS(LVTS_PROTTA), 193 LVTS_DEBUG_FS_REGS(LVTS_PROTTB), 194 LVTS_DEBUG_FS_REGS(LVTS_PROTTC), 195 LVTS_DEBUG_FS_REGS(LVTS_CLKEN), 196 }; 197 198 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) 199 { 200 struct debugfs_regset32 *regset; 201 struct lvts_ctrl *lvts_ctrl; 202 struct dentry *dentry; 203 char name[64]; 204 int i; 205 206 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); 207 if (IS_ERR(lvts_td->dom_dentry)) 208 return 0; 209 210 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 211 212 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 213 214 sprintf(name, "controller%d", i); 215 dentry = debugfs_create_dir(name, lvts_td->dom_dentry); 216 if (!dentry) 217 continue; 218 219 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 220 if (!regset) 221 continue; 222 223 regset->base = lvts_ctrl->base; 224 regset->regs = lvts_regs; 225 regset->nregs = ARRAY_SIZE(lvts_regs); 226 227 debugfs_create_regset32("registers", 0400, dentry, regset); 228 } 229 230 return 0; 231 } 232 233 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) 234 { 235 debugfs_remove_recursive(lvts_td->dom_dentry); 236 } 237 238 #else 239 240 static inline int lvts_debugfs_init(struct device *dev, 241 struct lvts_domain *lvts_td) 242 { 243 return 0; 244 } 245 246 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } 247 248 #endif 249 250 static int lvts_raw_to_temp(u32 raw_temp) 251 { 252 int temperature; 253 254 temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14; 255 temperature += coeff_b; 256 257 return temperature; 258 } 259 260 static u32 lvts_temp_to_raw(int temperature) 261 { 262 u32 raw_temp = ((s64)(coeff_b - temperature)) << 14; 263 264 raw_temp = div_s64(raw_temp, -LVTS_COEFF_A); 265 266 return raw_temp; 267 } 268 269 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) 270 { 271 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 272 void __iomem *msr = lvts_sensor->msr; 273 u32 value; 274 int rc; 275 276 /* 277 * Measurement registers: 278 * 279 * LVTS_MSR[0-3] / LVTS_IMMD[0-3] 280 * 281 * Bits: 282 * 283 * 32-17: Unused 284 * 16 : Valid temperature 285 * 15-0 : Raw temperature 286 */ 287 rc = readl_poll_timeout(msr, value, value & BIT(16), 288 LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US); 289 290 /* 291 * As the thermal zone temperature will read before the 292 * hardware sensor is fully initialized, we have to check the 293 * validity of the temperature returned when reading the 294 * measurement register. The thermal controller will set the 295 * valid bit temperature only when it is totally initialized. 296 * 297 * Otherwise, we may end up with garbage values out of the 298 * functionning temperature and directly jump to a system 299 * shutdown. 300 */ 301 if (rc) 302 return -EAGAIN; 303 304 *temp = lvts_raw_to_temp(value & 0xFFFF); 305 306 return 0; 307 } 308 309 static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) 310 { 311 u32 masks[] = { 312 LVTS_MONINT_OFFSET_SENSOR0, 313 LVTS_MONINT_OFFSET_SENSOR1, 314 LVTS_MONINT_OFFSET_SENSOR2, 315 LVTS_MONINT_OFFSET_SENSOR3, 316 }; 317 u32 value = 0; 318 int i; 319 320 value = readl(LVTS_MONINT(lvts_ctrl->base)); 321 322 for (i = 0; i < ARRAY_SIZE(masks); i++) { 323 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 324 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 325 value |= masks[i]; 326 else 327 value &= ~masks[i]; 328 } 329 330 writel(value, LVTS_MONINT(lvts_ctrl->base)); 331 } 332 333 static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high) 334 { 335 int i; 336 337 if (high > lvts_ctrl->high_thresh) 338 return true; 339 340 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) 341 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 342 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 343 return false; 344 345 return true; 346 } 347 348 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) 349 { 350 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 351 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, sensors[lvts_sensor->id]); 352 void __iomem *base = lvts_sensor->base; 353 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD); 354 u32 raw_high = lvts_temp_to_raw(high); 355 bool should_update_thresh; 356 357 lvts_sensor->low_thresh = low; 358 lvts_sensor->high_thresh = high; 359 360 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high); 361 if (should_update_thresh) { 362 lvts_ctrl->high_thresh = high; 363 lvts_ctrl->low_thresh = low; 364 } 365 lvts_update_irq_mask(lvts_ctrl); 366 367 if (!should_update_thresh) 368 return 0; 369 370 /* 371 * Low offset temperature threshold 372 * 373 * LVTS_OFFSETL 374 * 375 * Bits: 376 * 377 * 14-0 : Raw temperature for threshold 378 */ 379 pr_debug("%s: Setting low limit temperature interrupt: %d\n", 380 thermal_zone_device_type(tz), low); 381 writel(raw_low, LVTS_OFFSETL(base)); 382 383 /* 384 * High offset temperature threshold 385 * 386 * LVTS_OFFSETH 387 * 388 * Bits: 389 * 390 * 14-0 : Raw temperature for threshold 391 */ 392 pr_debug("%s: Setting high limit temperature interrupt: %d\n", 393 thermal_zone_device_type(tz), high); 394 writel(raw_high, LVTS_OFFSETH(base)); 395 396 return 0; 397 } 398 399 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) 400 { 401 irqreturn_t iret = IRQ_NONE; 402 u32 value; 403 u32 masks[] = { 404 LVTS_INT_SENSOR0, 405 LVTS_INT_SENSOR1, 406 LVTS_INT_SENSOR2, 407 LVTS_INT_SENSOR3 408 }; 409 int i; 410 411 /* 412 * Interrupt monitoring status 413 * 414 * LVTS_MONINTST 415 * 416 * Bits: 417 * 418 * 31 : Interrupt for stage 3 419 * 30 : Interrupt for stage 2 420 * 29 : Interrupt for state 1 421 * 28 : Interrupt using filter on sensor 3 422 * 423 * 27 : Interrupt using immediate on sensor 3 424 * 26 : Interrupt normal to hot on sensor 3 425 * 25 : Interrupt high offset on sensor 3 426 * 24 : Interrupt low offset on sensor 3 427 * 428 * 23 : Interrupt hot threshold on sensor 3 429 * 22 : Interrupt cold threshold on sensor 3 430 * 21 : Interrupt using filter on sensor 2 431 * 20 : Interrupt using filter on sensor 1 432 * 433 * 19 : Interrupt using filter on sensor 0 434 * 18 : Interrupt using immediate on sensor 2 435 * 17 : Interrupt using immediate on sensor 1 436 * 16 : Interrupt using immediate on sensor 0 437 * 438 * 15 : Interrupt device access timeout interrupt 439 * 14 : Interrupt normal to hot on sensor 2 440 * 13 : Interrupt high offset interrupt on sensor 2 441 * 12 : Interrupt low offset interrupt on sensor 2 442 * 443 * 11 : Interrupt hot threshold on sensor 2 444 * 10 : Interrupt cold threshold on sensor 2 445 * 9 : Interrupt normal to hot on sensor 1 446 * 8 : Interrupt high offset interrupt on sensor 1 447 * 448 * 7 : Interrupt low offset interrupt on sensor 1 449 * 6 : Interrupt hot threshold on sensor 1 450 * 5 : Interrupt cold threshold on sensor 1 451 * 4 : Interrupt normal to hot on sensor 0 452 * 453 * 3 : Interrupt high offset interrupt on sensor 0 454 * 2 : Interrupt low offset interrupt on sensor 0 455 * 1 : Interrupt hot threshold on sensor 0 456 * 0 : Interrupt cold threshold on sensor 0 457 * 458 * We are interested in the sensor(s) responsible of the 459 * interrupt event. We update the thermal framework with the 460 * thermal zone associated with the sensor. The framework will 461 * take care of the rest whatever the kind of interrupt, we 462 * are only interested in which sensor raised the interrupt. 463 * 464 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 465 * => 0x1FC00000 466 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 467 * => 0x00247C00 468 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 469 * => 0X001203E0 470 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 471 * => 0x0009001F 472 */ 473 value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); 474 475 /* 476 * Let's figure out which sensors raised the interrupt 477 * 478 * NOTE: the masks array must be ordered with the index 479 * corresponding to the sensor id eg. index=0, mask for 480 * sensor0. 481 */ 482 for (i = 0; i < ARRAY_SIZE(masks); i++) { 483 484 if (!(value & masks[i])) 485 continue; 486 487 thermal_zone_device_update(lvts_ctrl->sensors[i].tz, 488 THERMAL_TRIP_VIOLATED); 489 iret = IRQ_HANDLED; 490 } 491 492 /* 493 * Write back to clear the interrupt status (W1C) 494 */ 495 writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); 496 497 return iret; 498 } 499 500 /* 501 * Temperature interrupt handler. Even if the driver supports more 502 * interrupt modes, we use the interrupt when the temperature crosses 503 * the hot threshold the way up and the way down (modulo the 504 * hysteresis). 505 * 506 * Each thermal domain has a couple of interrupts, one for hardware 507 * reset and another one for all the thermal events happening on the 508 * different sensors. 509 * 510 * The interrupt is configured for thermal events when crossing the 511 * hot temperature limit. At each interrupt, we check in every 512 * controller if there is an interrupt pending. 513 */ 514 static irqreturn_t lvts_irq_handler(int irq, void *data) 515 { 516 struct lvts_domain *lvts_td = data; 517 irqreturn_t aux, iret = IRQ_NONE; 518 int i; 519 520 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 521 522 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]); 523 if (aux != IRQ_HANDLED) 524 continue; 525 526 iret = IRQ_HANDLED; 527 } 528 529 return iret; 530 } 531 532 static struct thermal_zone_device_ops lvts_ops = { 533 .get_temp = lvts_get_temp, 534 .set_trips = lvts_set_trips, 535 }; 536 537 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 538 const struct lvts_ctrl_data *lvts_ctrl_data) 539 { 540 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; 541 void __iomem *msr_regs[] = { 542 LVTS_MSR0(lvts_ctrl->base), 543 LVTS_MSR1(lvts_ctrl->base), 544 LVTS_MSR2(lvts_ctrl->base), 545 LVTS_MSR3(lvts_ctrl->base) 546 }; 547 548 void __iomem *imm_regs[] = { 549 LVTS_IMMD0(lvts_ctrl->base), 550 LVTS_IMMD1(lvts_ctrl->base), 551 LVTS_IMMD2(lvts_ctrl->base), 552 LVTS_IMMD3(lvts_ctrl->base) 553 }; 554 555 int i; 556 557 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { 558 559 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; 560 561 /* 562 * At this point, we don't know which id matches which 563 * sensor. Let's set arbitrally the id from the index. 564 */ 565 lvts_sensor[i].id = i; 566 567 /* 568 * The thermal zone registration will set the trip 569 * point interrupt in the thermal controller 570 * register. But this one will be reset in the 571 * initialization after. So we need to post pone the 572 * thermal zone creation after the controller is 573 * setup. For this reason, we store the device tree 574 * node id from the data in the sensor structure 575 */ 576 lvts_sensor[i].dt_id = dt_id; 577 578 /* 579 * We assign the base address of the thermal 580 * controller as a back pointer. So it will be 581 * accessible from the different thermal framework ops 582 * as we pass the lvts_sensor pointer as thermal zone 583 * private data. 584 */ 585 lvts_sensor[i].base = lvts_ctrl->base; 586 587 /* 588 * Each sensor has its own register address to read from. 589 */ 590 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? 591 imm_regs[i] : msr_regs[i]; 592 593 lvts_sensor[i].low_thresh = INT_MIN; 594 lvts_sensor[i].high_thresh = INT_MIN; 595 }; 596 597 lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; 598 599 return 0; 600 } 601 602 /* 603 * The efuse blob values follows the sensor enumeration per thermal 604 * controller. The decoding of the stream is as follow: 605 * 606 * stream index map for MCU Domain : 607 * 608 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 609 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 610 * 611 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 612 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 613 * 614 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 615 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 616 * 617 * stream index map for AP Domain : 618 * 619 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 620 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A 621 * 622 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 623 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 624 * 625 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> 626 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F 627 * 628 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> 629 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 630 * 631 * The data description gives the offset of the calibration data in 632 * this bytes stream for each sensor. 633 */ 634 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 635 const struct lvts_ctrl_data *lvts_ctrl_data, 636 u8 *efuse_calibration) 637 { 638 int i; 639 640 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) 641 memcpy(&lvts_ctrl->calibration[i], 642 efuse_calibration + lvts_ctrl_data->cal_offset[i], 2); 643 644 return 0; 645 } 646 647 /* 648 * The efuse bytes stream can be split into different chunk of 649 * nvmems. This function reads and concatenate those into a single 650 * buffer so it can be read sequentially when initializing the 651 * calibration data. 652 */ 653 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, 654 const struct lvts_data *lvts_data) 655 { 656 struct device_node *np = dev_of_node(dev); 657 struct nvmem_cell *cell; 658 struct property *prop; 659 const char *cell_name; 660 661 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { 662 size_t len; 663 u8 *efuse; 664 665 cell = of_nvmem_cell_get(np, cell_name); 666 if (IS_ERR(cell)) { 667 dev_err(dev, "Failed to get cell '%s'\n", cell_name); 668 return PTR_ERR(cell); 669 } 670 671 efuse = nvmem_cell_read(cell, &len); 672 673 nvmem_cell_put(cell); 674 675 if (IS_ERR(efuse)) { 676 dev_err(dev, "Failed to read cell '%s'\n", cell_name); 677 return PTR_ERR(efuse); 678 } 679 680 lvts_td->calib = devm_krealloc(dev, lvts_td->calib, 681 lvts_td->calib_len + len, GFP_KERNEL); 682 if (!lvts_td->calib) 683 return -ENOMEM; 684 685 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); 686 687 lvts_td->calib_len += len; 688 689 kfree(efuse); 690 } 691 692 return 0; 693 } 694 695 static int lvts_golden_temp_init(struct device *dev, u32 *value) 696 { 697 u32 gt; 698 699 gt = (*value) >> 24; 700 701 if (gt && gt < LVTS_GOLDEN_TEMP_MAX) 702 golden_temp = gt; 703 704 coeff_b = golden_temp * 500 + LVTS_COEFF_B; 705 706 return 0; 707 } 708 709 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, 710 const struct lvts_data *lvts_data) 711 { 712 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; 713 struct lvts_ctrl *lvts_ctrl; 714 int i, ret; 715 716 /* 717 * Create the calibration bytes stream from efuse data 718 */ 719 ret = lvts_calibration_read(dev, lvts_td, lvts_data); 720 if (ret) 721 return ret; 722 723 /* 724 * The golden temp information is contained in the first chunk 725 * of efuse data. 726 */ 727 ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib); 728 if (ret) 729 return ret; 730 731 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); 732 if (!lvts_ctrl) 733 return -ENOMEM; 734 735 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { 736 737 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; 738 739 ret = lvts_sensor_init(dev, &lvts_ctrl[i], 740 &lvts_data->lvts_ctrl[i]); 741 if (ret) 742 return ret; 743 744 ret = lvts_calibration_init(dev, &lvts_ctrl[i], 745 &lvts_data->lvts_ctrl[i], 746 lvts_td->calib); 747 if (ret) 748 return ret; 749 750 /* 751 * The mode the ctrl will use to read the temperature 752 * (filtered or immediate) 753 */ 754 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; 755 756 /* 757 * The temperature to raw temperature must be done 758 * after initializing the calibration. 759 */ 760 lvts_ctrl[i].hw_tshut_raw_temp = 761 lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp); 762 763 lvts_ctrl[i].low_thresh = INT_MIN; 764 lvts_ctrl[i].high_thresh = INT_MIN; 765 } 766 767 /* 768 * We no longer need the efuse bytes stream, let's free it 769 */ 770 devm_kfree(dev, lvts_td->calib); 771 772 lvts_td->lvts_ctrl = lvts_ctrl; 773 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; 774 775 return 0; 776 } 777 778 /* 779 * At this point the configuration register is the only place in the 780 * driver where we write multiple values. Per hardware constraint, 781 * each write in the configuration register must be separated by a 782 * delay of 2 us. 783 */ 784 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) 785 { 786 int i; 787 788 /* 789 * Configuration register 790 */ 791 for (i = 0; i < nr_cmds; i++) { 792 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); 793 usleep_range(2, 4); 794 } 795 } 796 797 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) 798 { 799 /* 800 * LVTS_PROTCTL : Thermal Protection Sensor Selection 801 * 802 * Bits: 803 * 804 * 19-18 : Sensor to base the protection on 805 * 17-16 : Strategy: 806 * 00 : Average of 4 sensors 807 * 01 : Max of 4 sensors 808 * 10 : Selected sensor with bits 19-18 809 * 11 : Reserved 810 */ 811 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); 812 813 /* 814 * LVTS_PROTTA : Stage 1 temperature threshold 815 * LVTS_PROTTB : Stage 2 temperature threshold 816 * LVTS_PROTTC : Stage 3 temperature threshold 817 * 818 * Bits: 819 * 820 * 14-0: Raw temperature threshold 821 * 822 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); 823 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); 824 */ 825 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); 826 827 /* 828 * LVTS_MONINT : Interrupt configuration register 829 * 830 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS 831 * register, except we set the bits to enable the interrupt. 832 */ 833 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); 834 835 return 0; 836 } 837 838 static int lvts_domain_reset(struct device *dev, struct reset_control *reset) 839 { 840 int ret; 841 842 ret = reset_control_assert(reset); 843 if (ret) 844 return ret; 845 846 return reset_control_deassert(reset); 847 } 848 849 /* 850 * Enable or disable the clocks of a specified thermal controller 851 */ 852 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) 853 { 854 /* 855 * LVTS_CLKEN : Internal LVTS clock 856 * 857 * Bits: 858 * 859 * 0 : enable / disable clock 860 */ 861 writel(enable, LVTS_CLKEN(lvts_ctrl->base)); 862 863 return 0; 864 } 865 866 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) 867 { 868 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; 869 870 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 871 872 /* 873 * LVTS_ID : Get ID and status of the thermal controller 874 * 875 * Bits: 876 * 877 * 0-5 : thermal controller id 878 * 7 : thermal controller connection is valid 879 */ 880 id = readl(LVTS_ID(lvts_ctrl->base)); 881 if (!(id & BIT(7))) 882 return -EIO; 883 884 return 0; 885 } 886 887 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) 888 { 889 /* 890 * Write device mask: 0xC1030000 891 */ 892 u32 cmds[] = { 893 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 894 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, 895 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, 896 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 897 }; 898 899 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 900 901 return 0; 902 } 903 904 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) 905 { 906 int i; 907 void __iomem *lvts_edata[] = { 908 LVTS_EDATA00(lvts_ctrl->base), 909 LVTS_EDATA01(lvts_ctrl->base), 910 LVTS_EDATA02(lvts_ctrl->base), 911 LVTS_EDATA03(lvts_ctrl->base) 912 }; 913 914 /* 915 * LVTS_EDATA0X : Efuse calibration reference value for sensor X 916 * 917 * Bits: 918 * 919 * 20-0 : Efuse value for normalization data 920 */ 921 for (i = 0; i < LVTS_SENSOR_MAX; i++) 922 writel(lvts_ctrl->calibration[i], lvts_edata[i]); 923 924 return 0; 925 } 926 927 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) 928 { 929 u32 value; 930 931 /* 932 * LVTS_TSSEL : Sensing point index numbering 933 * 934 * Bits: 935 * 936 * 31-24: ADC Sense 3 937 * 23-16: ADC Sense 2 938 * 15-8 : ADC Sense 1 939 * 7-0 : ADC Sense 0 940 */ 941 value = LVTS_TSSEL_CONF; 942 writel(value, LVTS_TSSEL(lvts_ctrl->base)); 943 944 /* 945 * LVTS_CALSCALE : ADC voltage round 946 */ 947 value = 0x300; 948 value = LVTS_CALSCALE_CONF; 949 950 /* 951 * LVTS_MSRCTL0 : Sensor filtering strategy 952 * 953 * Filters: 954 * 955 * 000 : One sample 956 * 001 : Avg 2 samples 957 * 010 : 4 samples, drop min and max, avg 2 samples 958 * 011 : 6 samples, drop min and max, avg 4 samples 959 * 100 : 10 samples, drop min and max, avg 8 samples 960 * 101 : 18 samples, drop min and max, avg 16 samples 961 * 962 * Bits: 963 * 964 * 0-2 : Sensor0 filter 965 * 3-5 : Sensor1 filter 966 * 6-8 : Sensor2 filter 967 * 9-11 : Sensor3 filter 968 */ 969 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | 970 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; 971 writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); 972 973 /* 974 * LVTS_MONCTL1 : Period unit and group interval configuration 975 * 976 * The clock source of LVTS thermal controller is 26MHz. 977 * 978 * The period unit is a time base for all the interval delays 979 * specified in the registers. By default we use 12. The time 980 * conversion is done by multiplying by 256 and 1/26.10^6 981 * 982 * An interval delay multiplied by the period unit gives the 983 * duration in seconds. 984 * 985 * - Filter interval delay is a delay between two samples of 986 * the same sensor. 987 * 988 * - Sensor interval delay is a delay between two samples of 989 * different sensors. 990 * 991 * - Group interval delay is a delay between different rounds. 992 * 993 * For example: 994 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, 995 * and two sensors, TS1 and TS2, are in a LVTS thermal controller 996 * and then 997 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us 998 * Filter interval delay = 1 * Period unit = 118.149us 999 * Sensor interval delay = 2 * Period unit = 236.298us 1000 * Group interval delay = 1 * Period unit = 118.149us 1001 * 1002 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... 1003 * <--> Filter interval delay 1004 * <--> Sensor interval delay 1005 * <--> Group interval delay 1006 * Bits: 1007 * 29 - 20 : Group interval 1008 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) 1009 * or an interrupt everytime the hot threshold is crossed (0) 1010 * 9 - 0 : Period unit 1011 * 1012 */ 1013 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; 1014 writel(value, LVTS_MONCTL1(lvts_ctrl->base)); 1015 1016 /* 1017 * LVTS_MONCTL2 : Filtering and sensor interval 1018 * 1019 * Bits: 1020 * 1021 * 25-16 : Interval unit in PERIOD_UNIT between sample on 1022 * the same sensor, filter interval 1023 * 9-0 : Interval unit in PERIOD_UNIT between each sensor 1024 * 1025 */ 1026 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; 1027 writel(value, LVTS_MONCTL2(lvts_ctrl->base)); 1028 1029 return lvts_irq_init(lvts_ctrl); 1030 } 1031 1032 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1033 { 1034 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; 1035 struct thermal_zone_device *tz; 1036 u32 sensor_map = 0; 1037 int i; 1038 /* 1039 * Bitmaps to enable each sensor on immediate and filtered modes, as 1040 * described in MSRCTL1 and MONCTL0 registers below, respectively. 1041 */ 1042 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) }; 1043 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) }; 1044 1045 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ? 1046 sensor_imm_bitmap : sensor_filt_bitmap; 1047 1048 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { 1049 1050 int dt_id = lvts_sensors[i].dt_id; 1051 1052 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], 1053 &lvts_ops); 1054 if (IS_ERR(tz)) { 1055 /* 1056 * This thermal zone is not described in the 1057 * device tree. It is not an error from the 1058 * thermal OF code POV, we just continue. 1059 */ 1060 if (PTR_ERR(tz) == -ENODEV) 1061 continue; 1062 1063 return PTR_ERR(tz); 1064 } 1065 1066 devm_thermal_add_hwmon_sysfs(dev, tz); 1067 1068 /* 1069 * The thermal zone pointer will be needed in the 1070 * interrupt handler, we store it in the sensor 1071 * structure. The thermal domain structure will be 1072 * passed to the interrupt handler private data as the 1073 * interrupt is shared for all the controller 1074 * belonging to the thermal domain. 1075 */ 1076 lvts_sensors[i].tz = tz; 1077 1078 /* 1079 * This sensor was correctly associated with a thermal 1080 * zone, let's set the corresponding bit in the sensor 1081 * map, so we can enable the temperature monitoring in 1082 * the hardware thermal controller. 1083 */ 1084 sensor_map |= sensor_bitmap[i]; 1085 } 1086 1087 /* 1088 * The initialization of the thermal zones give us 1089 * which sensor point to enable. If any thermal zone 1090 * was not described in the device tree, it won't be 1091 * enabled here in the sensor map. 1092 */ 1093 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { 1094 /* 1095 * LVTS_MSRCTL1 : Measurement control 1096 * 1097 * Bits: 1098 * 1099 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 1100 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 1101 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 1102 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 1103 * 1104 * That configuration will ignore the filtering and the delays 1105 * introduced in MONCTL1 and MONCTL2 1106 */ 1107 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base)); 1108 } else { 1109 /* 1110 * Bits: 1111 * 9: Single point access flow 1112 * 0-3: Enable sensing point 0-3 1113 */ 1114 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 1115 } 1116 1117 return 0; 1118 } 1119 1120 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, 1121 const struct lvts_data *lvts_data) 1122 { 1123 struct lvts_ctrl *lvts_ctrl; 1124 int i, ret; 1125 1126 ret = lvts_ctrl_init(dev, lvts_td, lvts_data); 1127 if (ret) 1128 return ret; 1129 1130 ret = lvts_domain_reset(dev, lvts_td->reset); 1131 if (ret) { 1132 dev_dbg(dev, "Failed to reset domain"); 1133 return ret; 1134 } 1135 1136 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1137 1138 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 1139 1140 /* 1141 * Initialization steps: 1142 * 1143 * - Enable the clock 1144 * - Connect to the LVTS 1145 * - Initialize the LVTS 1146 * - Prepare the calibration data 1147 * - Select monitored sensors 1148 * [ Configure sampling ] 1149 * [ Configure the interrupt ] 1150 * - Start measurement 1151 */ 1152 ret = lvts_ctrl_set_enable(lvts_ctrl, true); 1153 if (ret) { 1154 dev_dbg(dev, "Failed to enable LVTS clock"); 1155 return ret; 1156 } 1157 1158 ret = lvts_ctrl_connect(dev, lvts_ctrl); 1159 if (ret) { 1160 dev_dbg(dev, "Failed to connect to LVTS controller"); 1161 return ret; 1162 } 1163 1164 ret = lvts_ctrl_initialize(dev, lvts_ctrl); 1165 if (ret) { 1166 dev_dbg(dev, "Failed to initialize controller"); 1167 return ret; 1168 } 1169 1170 ret = lvts_ctrl_calibrate(dev, lvts_ctrl); 1171 if (ret) { 1172 dev_dbg(dev, "Failed to calibrate controller"); 1173 return ret; 1174 } 1175 1176 ret = lvts_ctrl_configure(dev, lvts_ctrl); 1177 if (ret) { 1178 dev_dbg(dev, "Failed to configure controller"); 1179 return ret; 1180 } 1181 1182 ret = lvts_ctrl_start(dev, lvts_ctrl); 1183 if (ret) { 1184 dev_dbg(dev, "Failed to start controller"); 1185 return ret; 1186 } 1187 } 1188 1189 return lvts_debugfs_init(dev, lvts_td); 1190 } 1191 1192 static int lvts_probe(struct platform_device *pdev) 1193 { 1194 const struct lvts_data *lvts_data; 1195 struct lvts_domain *lvts_td; 1196 struct device *dev = &pdev->dev; 1197 struct resource *res; 1198 int irq, ret; 1199 1200 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); 1201 if (!lvts_td) 1202 return -ENOMEM; 1203 1204 lvts_data = of_device_get_match_data(dev); 1205 1206 lvts_td->clk = devm_clk_get_enabled(dev, NULL); 1207 if (IS_ERR(lvts_td->clk)) 1208 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); 1209 1210 res = platform_get_mem_or_io(pdev, 0); 1211 if (!res) 1212 return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); 1213 1214 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1215 if (IS_ERR(lvts_td->base)) 1216 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); 1217 1218 lvts_td->reset = devm_reset_control_get_by_index(dev, 0); 1219 if (IS_ERR(lvts_td->reset)) 1220 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); 1221 1222 irq = platform_get_irq(pdev, 0); 1223 if (irq < 0) 1224 return irq; 1225 1226 ret = lvts_domain_init(dev, lvts_td, lvts_data); 1227 if (ret) 1228 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); 1229 1230 /* 1231 * At this point the LVTS is initialized and enabled. We can 1232 * safely enable the interrupt. 1233 */ 1234 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, 1235 IRQF_ONESHOT, dev_name(dev), lvts_td); 1236 if (ret) 1237 return dev_err_probe(dev, ret, "Failed to request interrupt\n"); 1238 1239 platform_set_drvdata(pdev, lvts_td); 1240 1241 return 0; 1242 } 1243 1244 static int lvts_remove(struct platform_device *pdev) 1245 { 1246 struct lvts_domain *lvts_td; 1247 int i; 1248 1249 lvts_td = platform_get_drvdata(pdev); 1250 1251 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1252 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1253 1254 lvts_debugfs_exit(lvts_td); 1255 1256 return 0; 1257 } 1258 1259 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { 1260 { 1261 .cal_offset = { 0x04, 0x07 }, 1262 .lvts_sensor = { 1263 { .dt_id = MT8195_MCU_BIG_CPU0 }, 1264 { .dt_id = MT8195_MCU_BIG_CPU1 } 1265 }, 1266 .num_lvts_sensor = 2, 1267 .offset = 0x0, 1268 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1269 }, 1270 { 1271 .cal_offset = { 0x0d, 0x10 }, 1272 .lvts_sensor = { 1273 { .dt_id = MT8195_MCU_BIG_CPU2 }, 1274 { .dt_id = MT8195_MCU_BIG_CPU3 } 1275 }, 1276 .num_lvts_sensor = 2, 1277 .offset = 0x100, 1278 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1279 }, 1280 { 1281 .cal_offset = { 0x16, 0x19, 0x1c, 0x1f }, 1282 .lvts_sensor = { 1283 { .dt_id = MT8195_MCU_LITTLE_CPU0 }, 1284 { .dt_id = MT8195_MCU_LITTLE_CPU1 }, 1285 { .dt_id = MT8195_MCU_LITTLE_CPU2 }, 1286 { .dt_id = MT8195_MCU_LITTLE_CPU3 } 1287 }, 1288 .num_lvts_sensor = 4, 1289 .offset = 0x200, 1290 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1291 } 1292 }; 1293 1294 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { 1295 { 1296 .cal_offset = { 0x25, 0x28 }, 1297 .lvts_sensor = { 1298 { .dt_id = MT8195_AP_VPU0 }, 1299 { .dt_id = MT8195_AP_VPU1 } 1300 }, 1301 .num_lvts_sensor = 2, 1302 .offset = 0x0, 1303 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1304 }, 1305 { 1306 .cal_offset = { 0x2e, 0x31 }, 1307 .lvts_sensor = { 1308 { .dt_id = MT8195_AP_GPU0 }, 1309 { .dt_id = MT8195_AP_GPU1 } 1310 }, 1311 .num_lvts_sensor = 2, 1312 .offset = 0x100, 1313 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1314 }, 1315 { 1316 .cal_offset = { 0x37, 0x3a, 0x3d }, 1317 .lvts_sensor = { 1318 { .dt_id = MT8195_AP_VDEC }, 1319 { .dt_id = MT8195_AP_IMG }, 1320 { .dt_id = MT8195_AP_INFRA }, 1321 }, 1322 .num_lvts_sensor = 3, 1323 .offset = 0x200, 1324 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1325 }, 1326 { 1327 .cal_offset = { 0x43, 0x46 }, 1328 .lvts_sensor = { 1329 { .dt_id = MT8195_AP_CAM0 }, 1330 { .dt_id = MT8195_AP_CAM1 } 1331 }, 1332 .num_lvts_sensor = 2, 1333 .offset = 0x300, 1334 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1335 } 1336 }; 1337 1338 static const struct lvts_data mt8195_lvts_mcu_data = { 1339 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, 1340 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), 1341 }; 1342 1343 static const struct lvts_data mt8195_lvts_ap_data = { 1344 .lvts_ctrl = mt8195_lvts_ap_data_ctrl, 1345 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), 1346 }; 1347 1348 static const struct of_device_id lvts_of_match[] = { 1349 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, 1350 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, 1351 {}, 1352 }; 1353 MODULE_DEVICE_TABLE(of, lvts_of_match); 1354 1355 static struct platform_driver lvts_driver = { 1356 .probe = lvts_probe, 1357 .remove = lvts_remove, 1358 .driver = { 1359 .name = "mtk-lvts-thermal", 1360 .of_match_table = lvts_of_match, 1361 }, 1362 }; 1363 module_platform_driver(lvts_driver); 1364 1365 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>"); 1366 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); 1367 MODULE_LICENSE("GPL"); 1368