1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/debugfs.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of_device.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 #include <linux/thermal.h> 20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h> 21 22 #include "../thermal_hwmon.h" 23 24 #define LVTS_MONCTL0(__base) (__base + 0x0000) 25 #define LVTS_MONCTL1(__base) (__base + 0x0004) 26 #define LVTS_MONCTL2(__base) (__base + 0x0008) 27 #define LVTS_MONINT(__base) (__base + 0x000C) 28 #define LVTS_MONINTSTS(__base) (__base + 0x0010) 29 #define LVTS_MONIDET0(__base) (__base + 0x0014) 30 #define LVTS_MONIDET1(__base) (__base + 0x0018) 31 #define LVTS_MONIDET2(__base) (__base + 0x001C) 32 #define LVTS_MONIDET3(__base) (__base + 0x0020) 33 #define LVTS_H2NTHRE(__base) (__base + 0x0024) 34 #define LVTS_HTHRE(__base) (__base + 0x0028) 35 #define LVTS_OFFSETH(__base) (__base + 0x0030) 36 #define LVTS_OFFSETL(__base) (__base + 0x0034) 37 #define LVTS_MSRCTL0(__base) (__base + 0x0038) 38 #define LVTS_MSRCTL1(__base) (__base + 0x003C) 39 #define LVTS_TSSEL(__base) (__base + 0x0040) 40 #define LVTS_CALSCALE(__base) (__base + 0x0048) 41 #define LVTS_ID(__base) (__base + 0x004C) 42 #define LVTS_CONFIG(__base) (__base + 0x0050) 43 #define LVTS_EDATA00(__base) (__base + 0x0054) 44 #define LVTS_EDATA01(__base) (__base + 0x0058) 45 #define LVTS_EDATA02(__base) (__base + 0x005C) 46 #define LVTS_EDATA03(__base) (__base + 0x0060) 47 #define LVTS_MSR0(__base) (__base + 0x0090) 48 #define LVTS_MSR1(__base) (__base + 0x0094) 49 #define LVTS_MSR2(__base) (__base + 0x0098) 50 #define LVTS_MSR3(__base) (__base + 0x009C) 51 #define LVTS_IMMD0(__base) (__base + 0x00A0) 52 #define LVTS_IMMD1(__base) (__base + 0x00A4) 53 #define LVTS_IMMD2(__base) (__base + 0x00A8) 54 #define LVTS_IMMD3(__base) (__base + 0x00AC) 55 #define LVTS_PROTCTL(__base) (__base + 0x00C0) 56 #define LVTS_PROTTA(__base) (__base + 0x00C4) 57 #define LVTS_PROTTB(__base) (__base + 0x00C8) 58 #define LVTS_PROTTC(__base) (__base + 0x00CC) 59 #define LVTS_CLKEN(__base) (__base + 0x00E4) 60 61 #define LVTS_PERIOD_UNIT ((118 * 1000) / (256 * 38)) 62 #define LVTS_GROUP_INTERVAL 1 63 #define LVTS_FILTER_INTERVAL 1 64 #define LVTS_SENSOR_INTERVAL 1 65 #define LVTS_HW_FILTER 0x2 66 #define LVTS_TSSEL_CONF 0x13121110 67 #define LVTS_CALSCALE_CONF 0x300 68 #define LVTS_MONINT_CONF 0x9FBF7BDE 69 70 #define LVTS_INT_SENSOR0 0x0009001F 71 #define LVTS_INT_SENSOR1 0x001203E0 72 #define LVTS_INT_SENSOR2 0x00247C00 73 #define LVTS_INT_SENSOR3 0x1FC00000 74 75 #define LVTS_SENSOR_MAX 4 76 #define LVTS_GOLDEN_TEMP_MAX 62 77 #define LVTS_GOLDEN_TEMP_DEFAULT 50 78 #define LVTS_COEFF_A -250460 79 #define LVTS_COEFF_B 250460 80 81 #define LVTS_MSR_IMMEDIATE_MODE 0 82 #define LVTS_MSR_FILTERED_MODE 1 83 84 #define LVTS_HW_SHUTDOWN_MT8195 105000 85 86 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; 87 static int coeff_b = LVTS_COEFF_B; 88 89 struct lvts_sensor_data { 90 int dt_id; 91 }; 92 93 struct lvts_ctrl_data { 94 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; 95 int cal_offset[LVTS_SENSOR_MAX]; 96 int hw_tshut_temp; 97 int num_lvts_sensor; 98 int offset; 99 int mode; 100 }; 101 102 struct lvts_data { 103 const struct lvts_ctrl_data *lvts_ctrl; 104 int num_lvts_ctrl; 105 }; 106 107 struct lvts_sensor { 108 struct thermal_zone_device *tz; 109 void __iomem *msr; 110 void __iomem *base; 111 int id; 112 int dt_id; 113 }; 114 115 struct lvts_ctrl { 116 struct lvts_sensor sensors[LVTS_SENSOR_MAX]; 117 u32 calibration[LVTS_SENSOR_MAX]; 118 u32 hw_tshut_raw_temp; 119 int num_lvts_sensor; 120 int mode; 121 void __iomem *base; 122 }; 123 124 struct lvts_domain { 125 struct lvts_ctrl *lvts_ctrl; 126 struct reset_control *reset; 127 struct clk *clk; 128 int num_lvts_ctrl; 129 void __iomem *base; 130 size_t calib_len; 131 u8 *calib; 132 #ifdef CONFIG_DEBUG_FS 133 struct dentry *dom_dentry; 134 #endif 135 }; 136 137 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS 138 139 #define LVTS_DEBUG_FS_REGS(__reg) \ 140 { \ 141 .name = __stringify(__reg), \ 142 .offset = __reg(0), \ 143 } 144 145 static const struct debugfs_reg32 lvts_regs[] = { 146 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), 147 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), 148 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), 149 LVTS_DEBUG_FS_REGS(LVTS_MONINT), 150 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), 151 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), 152 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), 153 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), 154 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), 155 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), 156 LVTS_DEBUG_FS_REGS(LVTS_HTHRE), 157 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), 158 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), 159 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), 160 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), 161 LVTS_DEBUG_FS_REGS(LVTS_TSSEL), 162 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), 163 LVTS_DEBUG_FS_REGS(LVTS_ID), 164 LVTS_DEBUG_FS_REGS(LVTS_CONFIG), 165 LVTS_DEBUG_FS_REGS(LVTS_EDATA00), 166 LVTS_DEBUG_FS_REGS(LVTS_EDATA01), 167 LVTS_DEBUG_FS_REGS(LVTS_EDATA02), 168 LVTS_DEBUG_FS_REGS(LVTS_EDATA03), 169 LVTS_DEBUG_FS_REGS(LVTS_MSR0), 170 LVTS_DEBUG_FS_REGS(LVTS_MSR1), 171 LVTS_DEBUG_FS_REGS(LVTS_MSR2), 172 LVTS_DEBUG_FS_REGS(LVTS_MSR3), 173 LVTS_DEBUG_FS_REGS(LVTS_IMMD0), 174 LVTS_DEBUG_FS_REGS(LVTS_IMMD1), 175 LVTS_DEBUG_FS_REGS(LVTS_IMMD2), 176 LVTS_DEBUG_FS_REGS(LVTS_IMMD3), 177 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), 178 LVTS_DEBUG_FS_REGS(LVTS_PROTTA), 179 LVTS_DEBUG_FS_REGS(LVTS_PROTTB), 180 LVTS_DEBUG_FS_REGS(LVTS_PROTTC), 181 LVTS_DEBUG_FS_REGS(LVTS_CLKEN), 182 }; 183 184 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) 185 { 186 struct debugfs_regset32 *regset; 187 struct lvts_ctrl *lvts_ctrl; 188 struct dentry *dentry; 189 char name[64]; 190 int i; 191 192 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); 193 if (!lvts_td->dom_dentry) 194 return 0; 195 196 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 197 198 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 199 200 sprintf(name, "controller%d", i); 201 dentry = debugfs_create_dir(name, lvts_td->dom_dentry); 202 if (!dentry) 203 continue; 204 205 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 206 if (!regset) 207 continue; 208 209 regset->base = lvts_ctrl->base; 210 regset->regs = lvts_regs; 211 regset->nregs = ARRAY_SIZE(lvts_regs); 212 213 debugfs_create_regset32("registers", 0400, dentry, regset); 214 } 215 216 return 0; 217 } 218 219 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) 220 { 221 debugfs_remove_recursive(lvts_td->dom_dentry); 222 } 223 224 #else 225 226 static inline int lvts_debugfs_init(struct device *dev, 227 struct lvts_domain *lvts_td) 228 { 229 return 0; 230 } 231 232 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } 233 234 #endif 235 236 static int lvts_raw_to_temp(u32 raw_temp) 237 { 238 int temperature; 239 240 temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14; 241 temperature += coeff_b; 242 243 return temperature; 244 } 245 246 static u32 lvts_temp_to_raw(int temperature) 247 { 248 u32 raw_temp = ((s64)(coeff_b - temperature)) << 14; 249 250 raw_temp = div_s64(raw_temp, -LVTS_COEFF_A); 251 252 return raw_temp; 253 } 254 255 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) 256 { 257 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 258 void __iomem *msr = lvts_sensor->msr; 259 u32 value; 260 261 /* 262 * Measurement registers: 263 * 264 * LVTS_MSR[0-3] / LVTS_IMMD[0-3] 265 * 266 * Bits: 267 * 268 * 32-17: Unused 269 * 16 : Valid temperature 270 * 15-0 : Raw temperature 271 */ 272 value = readl(msr); 273 274 /* 275 * As the thermal zone temperature will read before the 276 * hardware sensor is fully initialized, we have to check the 277 * validity of the temperature returned when reading the 278 * measurement register. The thermal controller will set the 279 * valid bit temperature only when it is totally initialized. 280 * 281 * Otherwise, we may end up with garbage values out of the 282 * functionning temperature and directly jump to a system 283 * shutdown. 284 */ 285 if (!(value & BIT(16))) 286 return -EAGAIN; 287 288 *temp = lvts_raw_to_temp(value & 0xFFFF); 289 290 return 0; 291 } 292 293 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) 294 { 295 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 296 void __iomem *base = lvts_sensor->base; 297 u32 raw_low = lvts_temp_to_raw(low); 298 u32 raw_high = lvts_temp_to_raw(high); 299 300 /* 301 * Hot to normal temperature threshold 302 * 303 * LVTS_H2NTHRE 304 * 305 * Bits: 306 * 307 * 14-0 : Raw temperature for threshold 308 */ 309 if (low != -INT_MAX) { 310 pr_debug("%s: Setting low limit temperature interrupt: %d\n", 311 thermal_zone_device_type(tz), low); 312 writel(raw_low, LVTS_H2NTHRE(base)); 313 } 314 315 /* 316 * Hot temperature threshold 317 * 318 * LVTS_HTHRE 319 * 320 * Bits: 321 * 322 * 14-0 : Raw temperature for threshold 323 */ 324 pr_debug("%s: Setting high limit temperature interrupt: %d\n", 325 thermal_zone_device_type(tz), high); 326 writel(raw_high, LVTS_HTHRE(base)); 327 328 return 0; 329 } 330 331 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) 332 { 333 irqreturn_t iret = IRQ_NONE; 334 u32 value; 335 u32 masks[] = { 336 LVTS_INT_SENSOR0, 337 LVTS_INT_SENSOR1, 338 LVTS_INT_SENSOR2, 339 LVTS_INT_SENSOR3 340 }; 341 int i; 342 343 /* 344 * Interrupt monitoring status 345 * 346 * LVTS_MONINTST 347 * 348 * Bits: 349 * 350 * 31 : Interrupt for stage 3 351 * 30 : Interrupt for stage 2 352 * 29 : Interrupt for state 1 353 * 28 : Interrupt using filter on sensor 3 354 * 355 * 27 : Interrupt using immediate on sensor 3 356 * 26 : Interrupt normal to hot on sensor 3 357 * 25 : Interrupt high offset on sensor 3 358 * 24 : Interrupt low offset on sensor 3 359 * 360 * 23 : Interrupt hot threshold on sensor 3 361 * 22 : Interrupt cold threshold on sensor 3 362 * 21 : Interrupt using filter on sensor 2 363 * 20 : Interrupt using filter on sensor 1 364 * 365 * 19 : Interrupt using filter on sensor 0 366 * 18 : Interrupt using immediate on sensor 2 367 * 17 : Interrupt using immediate on sensor 1 368 * 16 : Interrupt using immediate on sensor 0 369 * 370 * 15 : Interrupt device access timeout interrupt 371 * 14 : Interrupt normal to hot on sensor 2 372 * 13 : Interrupt high offset interrupt on sensor 2 373 * 12 : Interrupt low offset interrupt on sensor 2 374 * 375 * 11 : Interrupt hot threshold on sensor 2 376 * 10 : Interrupt cold threshold on sensor 2 377 * 9 : Interrupt normal to hot on sensor 1 378 * 8 : Interrupt high offset interrupt on sensor 1 379 * 380 * 7 : Interrupt low offset interrupt on sensor 1 381 * 6 : Interrupt hot threshold on sensor 1 382 * 5 : Interrupt cold threshold on sensor 1 383 * 4 : Interrupt normal to hot on sensor 0 384 * 385 * 3 : Interrupt high offset interrupt on sensor 0 386 * 2 : Interrupt low offset interrupt on sensor 0 387 * 1 : Interrupt hot threshold on sensor 0 388 * 0 : Interrupt cold threshold on sensor 0 389 * 390 * We are interested in the sensor(s) responsible of the 391 * interrupt event. We update the thermal framework with the 392 * thermal zone associated with the sensor. The framework will 393 * take care of the rest whatever the kind of interrupt, we 394 * are only interested in which sensor raised the interrupt. 395 * 396 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 397 * => 0x1FC00000 398 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 399 * => 0x00247C00 400 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 401 * => 0X001203E0 402 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 403 * => 0x0009001F 404 */ 405 value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); 406 407 /* 408 * Let's figure out which sensors raised the interrupt 409 * 410 * NOTE: the masks array must be ordered with the index 411 * corresponding to the sensor id eg. index=0, mask for 412 * sensor0. 413 */ 414 for (i = 0; i < ARRAY_SIZE(masks); i++) { 415 416 if (!(value & masks[i])) 417 continue; 418 419 thermal_zone_device_update(lvts_ctrl->sensors[i].tz, 420 THERMAL_TRIP_VIOLATED); 421 iret = IRQ_HANDLED; 422 } 423 424 /* 425 * Write back to clear the interrupt status (W1C) 426 */ 427 writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); 428 429 return iret; 430 } 431 432 /* 433 * Temperature interrupt handler. Even if the driver supports more 434 * interrupt modes, we use the interrupt when the temperature crosses 435 * the hot threshold the way up and the way down (modulo the 436 * hysteresis). 437 * 438 * Each thermal domain has a couple of interrupts, one for hardware 439 * reset and another one for all the thermal events happening on the 440 * different sensors. 441 * 442 * The interrupt is configured for thermal events when crossing the 443 * hot temperature limit. At each interrupt, we check in every 444 * controller if there is an interrupt pending. 445 */ 446 static irqreturn_t lvts_irq_handler(int irq, void *data) 447 { 448 struct lvts_domain *lvts_td = data; 449 irqreturn_t aux, iret = IRQ_NONE; 450 int i; 451 452 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 453 454 aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl); 455 if (aux != IRQ_HANDLED) 456 continue; 457 458 iret = IRQ_HANDLED; 459 } 460 461 return iret; 462 } 463 464 static struct thermal_zone_device_ops lvts_ops = { 465 .get_temp = lvts_get_temp, 466 .set_trips = lvts_set_trips, 467 }; 468 469 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 470 const struct lvts_ctrl_data *lvts_ctrl_data) 471 { 472 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; 473 void __iomem *msr_regs[] = { 474 LVTS_MSR0(lvts_ctrl->base), 475 LVTS_MSR1(lvts_ctrl->base), 476 LVTS_MSR2(lvts_ctrl->base), 477 LVTS_MSR3(lvts_ctrl->base) 478 }; 479 480 void __iomem *imm_regs[] = { 481 LVTS_IMMD0(lvts_ctrl->base), 482 LVTS_IMMD1(lvts_ctrl->base), 483 LVTS_IMMD2(lvts_ctrl->base), 484 LVTS_IMMD3(lvts_ctrl->base) 485 }; 486 487 int i; 488 489 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { 490 491 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; 492 493 /* 494 * At this point, we don't know which id matches which 495 * sensor. Let's set arbitrally the id from the index. 496 */ 497 lvts_sensor[i].id = i; 498 499 /* 500 * The thermal zone registration will set the trip 501 * point interrupt in the thermal controller 502 * register. But this one will be reset in the 503 * initialization after. So we need to post pone the 504 * thermal zone creation after the controller is 505 * setup. For this reason, we store the device tree 506 * node id from the data in the sensor structure 507 */ 508 lvts_sensor[i].dt_id = dt_id; 509 510 /* 511 * We assign the base address of the thermal 512 * controller as a back pointer. So it will be 513 * accessible from the different thermal framework ops 514 * as we pass the lvts_sensor pointer as thermal zone 515 * private data. 516 */ 517 lvts_sensor[i].base = lvts_ctrl->base; 518 519 /* 520 * Each sensor has its own register address to read from. 521 */ 522 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? 523 imm_regs[i] : msr_regs[i]; 524 }; 525 526 lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; 527 528 return 0; 529 } 530 531 /* 532 * The efuse blob values follows the sensor enumeration per thermal 533 * controller. The decoding of the stream is as follow: 534 * 535 * stream index map for MCU Domain : 536 * 537 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 538 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 539 * 540 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 541 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 542 * 543 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 544 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 545 * 546 * stream index map for AP Domain : 547 * 548 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 549 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A 550 * 551 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 552 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 553 * 554 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> 555 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F 556 * 557 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> 558 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 559 * 560 * The data description gives the offset of the calibration data in 561 * this bytes stream for each sensor. 562 */ 563 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 564 const struct lvts_ctrl_data *lvts_ctrl_data, 565 u8 *efuse_calibration) 566 { 567 int i; 568 569 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) 570 memcpy(&lvts_ctrl->calibration[i], 571 efuse_calibration + lvts_ctrl_data->cal_offset[i], 2); 572 573 return 0; 574 } 575 576 /* 577 * The efuse bytes stream can be split into different chunk of 578 * nvmems. This function reads and concatenate those into a single 579 * buffer so it can be read sequentially when initializing the 580 * calibration data. 581 */ 582 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, 583 const struct lvts_data *lvts_data) 584 { 585 struct device_node *np = dev_of_node(dev); 586 struct nvmem_cell *cell; 587 struct property *prop; 588 const char *cell_name; 589 590 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { 591 size_t len; 592 u8 *efuse; 593 594 cell = of_nvmem_cell_get(np, cell_name); 595 if (IS_ERR(cell)) { 596 dev_err(dev, "Failed to get cell '%s'\n", cell_name); 597 return PTR_ERR(cell); 598 } 599 600 efuse = nvmem_cell_read(cell, &len); 601 602 nvmem_cell_put(cell); 603 604 if (IS_ERR(efuse)) { 605 dev_err(dev, "Failed to read cell '%s'\n", cell_name); 606 return PTR_ERR(efuse); 607 } 608 609 lvts_td->calib = devm_krealloc(dev, lvts_td->calib, 610 lvts_td->calib_len + len, GFP_KERNEL); 611 if (!lvts_td->calib) 612 return -ENOMEM; 613 614 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); 615 616 lvts_td->calib_len += len; 617 618 kfree(efuse); 619 } 620 621 return 0; 622 } 623 624 static int lvts_golden_temp_init(struct device *dev, u32 *value) 625 { 626 u32 gt; 627 628 gt = (*value) >> 24; 629 630 if (gt && gt < LVTS_GOLDEN_TEMP_MAX) 631 golden_temp = gt; 632 633 coeff_b = golden_temp * 500 + LVTS_COEFF_B; 634 635 return 0; 636 } 637 638 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, 639 const struct lvts_data *lvts_data) 640 { 641 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; 642 struct lvts_ctrl *lvts_ctrl; 643 int i, ret; 644 645 /* 646 * Create the calibration bytes stream from efuse data 647 */ 648 ret = lvts_calibration_read(dev, lvts_td, lvts_data); 649 if (ret) 650 return ret; 651 652 /* 653 * The golden temp information is contained in the first chunk 654 * of efuse data. 655 */ 656 ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib); 657 if (ret) 658 return ret; 659 660 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); 661 if (!lvts_ctrl) 662 return -ENOMEM; 663 664 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { 665 666 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; 667 668 ret = lvts_sensor_init(dev, &lvts_ctrl[i], 669 &lvts_data->lvts_ctrl[i]); 670 if (ret) 671 return ret; 672 673 ret = lvts_calibration_init(dev, &lvts_ctrl[i], 674 &lvts_data->lvts_ctrl[i], 675 lvts_td->calib); 676 if (ret) 677 return ret; 678 679 /* 680 * The mode the ctrl will use to read the temperature 681 * (filtered or immediate) 682 */ 683 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; 684 685 /* 686 * The temperature to raw temperature must be done 687 * after initializing the calibration. 688 */ 689 lvts_ctrl[i].hw_tshut_raw_temp = 690 lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp); 691 } 692 693 /* 694 * We no longer need the efuse bytes stream, let's free it 695 */ 696 devm_kfree(dev, lvts_td->calib); 697 698 lvts_td->lvts_ctrl = lvts_ctrl; 699 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; 700 701 return 0; 702 } 703 704 /* 705 * At this point the configuration register is the only place in the 706 * driver where we write multiple values. Per hardware constraint, 707 * each write in the configuration register must be separated by a 708 * delay of 2 us. 709 */ 710 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) 711 { 712 int i; 713 714 /* 715 * Configuration register 716 */ 717 for (i = 0; i < nr_cmds; i++) { 718 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); 719 usleep_range(2, 4); 720 } 721 } 722 723 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) 724 { 725 /* 726 * LVTS_PROTCTL : Thermal Protection Sensor Selection 727 * 728 * Bits: 729 * 730 * 19-18 : Sensor to base the protection on 731 * 17-16 : Strategy: 732 * 00 : Average of 4 sensors 733 * 01 : Max of 4 sensors 734 * 10 : Selected sensor with bits 19-18 735 * 11 : Reserved 736 */ 737 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); 738 739 /* 740 * LVTS_PROTTA : Stage 1 temperature threshold 741 * LVTS_PROTTB : Stage 2 temperature threshold 742 * LVTS_PROTTC : Stage 3 temperature threshold 743 * 744 * Bits: 745 * 746 * 14-0: Raw temperature threshold 747 * 748 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); 749 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); 750 */ 751 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); 752 753 /* 754 * LVTS_MONINT : Interrupt configuration register 755 * 756 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS 757 * register, except we set the bits to enable the interrupt. 758 */ 759 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); 760 761 return 0; 762 } 763 764 static int lvts_domain_reset(struct device *dev, struct reset_control *reset) 765 { 766 int ret; 767 768 ret = reset_control_assert(reset); 769 if (ret) 770 return ret; 771 772 return reset_control_deassert(reset); 773 } 774 775 /* 776 * Enable or disable the clocks of a specified thermal controller 777 */ 778 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) 779 { 780 /* 781 * LVTS_CLKEN : Internal LVTS clock 782 * 783 * Bits: 784 * 785 * 0 : enable / disable clock 786 */ 787 writel(enable, LVTS_CLKEN(lvts_ctrl->base)); 788 789 return 0; 790 } 791 792 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) 793 { 794 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; 795 796 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 797 798 /* 799 * LVTS_ID : Get ID and status of the thermal controller 800 * 801 * Bits: 802 * 803 * 0-5 : thermal controller id 804 * 7 : thermal controller connection is valid 805 */ 806 id = readl(LVTS_ID(lvts_ctrl->base)); 807 if (!(id & BIT(7))) 808 return -EIO; 809 810 return 0; 811 } 812 813 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) 814 { 815 /* 816 * Write device mask: 0xC1030000 817 */ 818 u32 cmds[] = { 819 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 820 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, 821 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, 822 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 823 }; 824 825 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 826 827 return 0; 828 } 829 830 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) 831 { 832 int i; 833 void __iomem *lvts_edata[] = { 834 LVTS_EDATA00(lvts_ctrl->base), 835 LVTS_EDATA01(lvts_ctrl->base), 836 LVTS_EDATA02(lvts_ctrl->base), 837 LVTS_EDATA03(lvts_ctrl->base) 838 }; 839 840 /* 841 * LVTS_EDATA0X : Efuse calibration reference value for sensor X 842 * 843 * Bits: 844 * 845 * 20-0 : Efuse value for normalization data 846 */ 847 for (i = 0; i < LVTS_SENSOR_MAX; i++) 848 writel(lvts_ctrl->calibration[i], lvts_edata[i]); 849 850 return 0; 851 } 852 853 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) 854 { 855 u32 value; 856 857 /* 858 * LVTS_TSSEL : Sensing point index numbering 859 * 860 * Bits: 861 * 862 * 31-24: ADC Sense 3 863 * 23-16: ADC Sense 2 864 * 15-8 : ADC Sense 1 865 * 7-0 : ADC Sense 0 866 */ 867 value = LVTS_TSSEL_CONF; 868 writel(value, LVTS_TSSEL(lvts_ctrl->base)); 869 870 /* 871 * LVTS_CALSCALE : ADC voltage round 872 */ 873 value = 0x300; 874 value = LVTS_CALSCALE_CONF; 875 876 /* 877 * LVTS_MSRCTL0 : Sensor filtering strategy 878 * 879 * Filters: 880 * 881 * 000 : One sample 882 * 001 : Avg 2 samples 883 * 010 : 4 samples, drop min and max, avg 2 samples 884 * 011 : 6 samples, drop min and max, avg 4 samples 885 * 100 : 10 samples, drop min and max, avg 8 samples 886 * 101 : 18 samples, drop min and max, avg 16 samples 887 * 888 * Bits: 889 * 890 * 0-2 : Sensor0 filter 891 * 3-5 : Sensor1 filter 892 * 6-8 : Sensor2 filter 893 * 9-11 : Sensor3 filter 894 */ 895 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | 896 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; 897 writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); 898 899 /* 900 * LVTS_MSRCTL1 : Measurement control 901 * 902 * Bits: 903 * 904 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 905 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 906 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 907 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 908 * 909 * That configuration will ignore the filtering and the delays 910 * introduced below in MONCTL1 and MONCTL2 911 */ 912 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { 913 value = BIT(9) | BIT(6) | BIT(5) | BIT(4); 914 writel(value, LVTS_MSRCTL1(lvts_ctrl->base)); 915 } 916 917 /* 918 * LVTS_MONCTL1 : Period unit and group interval configuration 919 * 920 * The clock source of LVTS thermal controller is 26MHz. 921 * 922 * The period unit is a time base for all the interval delays 923 * specified in the registers. By default we use 12. The time 924 * conversion is done by multiplying by 256 and 1/26.10^6 925 * 926 * An interval delay multiplied by the period unit gives the 927 * duration in seconds. 928 * 929 * - Filter interval delay is a delay between two samples of 930 * the same sensor. 931 * 932 * - Sensor interval delay is a delay between two samples of 933 * different sensors. 934 * 935 * - Group interval delay is a delay between different rounds. 936 * 937 * For example: 938 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, 939 * and two sensors, TS1 and TS2, are in a LVTS thermal controller 940 * and then 941 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us 942 * Filter interval delay = 1 * Period unit = 118.149us 943 * Sensor interval delay = 2 * Period unit = 236.298us 944 * Group interval delay = 1 * Period unit = 118.149us 945 * 946 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... 947 * <--> Filter interval delay 948 * <--> Sensor interval delay 949 * <--> Group interval delay 950 * Bits: 951 * 29 - 20 : Group interval 952 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) 953 * or an interrupt everytime the hot threshold is crossed (0) 954 * 9 - 0 : Period unit 955 * 956 */ 957 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; 958 writel(value, LVTS_MONCTL1(lvts_ctrl->base)); 959 960 /* 961 * LVTS_MONCTL2 : Filtering and sensor interval 962 * 963 * Bits: 964 * 965 * 25-16 : Interval unit in PERIOD_UNIT between sample on 966 * the same sensor, filter interval 967 * 9-0 : Interval unit in PERIOD_UNIT between each sensor 968 * 969 */ 970 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; 971 writel(value, LVTS_MONCTL2(lvts_ctrl->base)); 972 973 return lvts_irq_init(lvts_ctrl); 974 } 975 976 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) 977 { 978 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; 979 struct thermal_zone_device *tz; 980 u32 sensor_map = 0; 981 int i; 982 983 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { 984 985 int dt_id = lvts_sensors[i].dt_id; 986 987 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], 988 &lvts_ops); 989 if (IS_ERR(tz)) { 990 /* 991 * This thermal zone is not described in the 992 * device tree. It is not an error from the 993 * thermal OF code POV, we just continue. 994 */ 995 if (PTR_ERR(tz) == -ENODEV) 996 continue; 997 998 return PTR_ERR(tz); 999 } 1000 1001 devm_thermal_add_hwmon_sysfs(dev, tz); 1002 1003 /* 1004 * The thermal zone pointer will be needed in the 1005 * interrupt handler, we store it in the sensor 1006 * structure. The thermal domain structure will be 1007 * passed to the interrupt handler private data as the 1008 * interrupt is shared for all the controller 1009 * belonging to the thermal domain. 1010 */ 1011 lvts_sensors[i].tz = tz; 1012 1013 /* 1014 * This sensor was correctly associated with a thermal 1015 * zone, let's set the corresponding bit in the sensor 1016 * map, so we can enable the temperature monitoring in 1017 * the hardware thermal controller. 1018 */ 1019 sensor_map |= BIT(i); 1020 } 1021 1022 /* 1023 * Bits: 1024 * 9: Single point access flow 1025 * 0-3: Enable sensing point 0-3 1026 * 1027 * The initialization of the thermal zones give us 1028 * which sensor point to enable. If any thermal zone 1029 * was not described in the device tree, it won't be 1030 * enabled here in the sensor map. 1031 */ 1032 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 1033 1034 return 0; 1035 } 1036 1037 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, 1038 const struct lvts_data *lvts_data) 1039 { 1040 struct lvts_ctrl *lvts_ctrl; 1041 int i, ret; 1042 1043 ret = lvts_ctrl_init(dev, lvts_td, lvts_data); 1044 if (ret) 1045 return ret; 1046 1047 ret = lvts_domain_reset(dev, lvts_td->reset); 1048 if (ret) { 1049 dev_dbg(dev, "Failed to reset domain"); 1050 return ret; 1051 } 1052 1053 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1054 1055 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 1056 1057 /* 1058 * Initialization steps: 1059 * 1060 * - Enable the clock 1061 * - Connect to the LVTS 1062 * - Initialize the LVTS 1063 * - Prepare the calibration data 1064 * - Select monitored sensors 1065 * [ Configure sampling ] 1066 * [ Configure the interrupt ] 1067 * - Start measurement 1068 */ 1069 ret = lvts_ctrl_set_enable(lvts_ctrl, true); 1070 if (ret) { 1071 dev_dbg(dev, "Failed to enable LVTS clock"); 1072 return ret; 1073 } 1074 1075 ret = lvts_ctrl_connect(dev, lvts_ctrl); 1076 if (ret) { 1077 dev_dbg(dev, "Failed to connect to LVTS controller"); 1078 return ret; 1079 } 1080 1081 ret = lvts_ctrl_initialize(dev, lvts_ctrl); 1082 if (ret) { 1083 dev_dbg(dev, "Failed to initialize controller"); 1084 return ret; 1085 } 1086 1087 ret = lvts_ctrl_calibrate(dev, lvts_ctrl); 1088 if (ret) { 1089 dev_dbg(dev, "Failed to calibrate controller"); 1090 return ret; 1091 } 1092 1093 ret = lvts_ctrl_configure(dev, lvts_ctrl); 1094 if (ret) { 1095 dev_dbg(dev, "Failed to configure controller"); 1096 return ret; 1097 } 1098 1099 ret = lvts_ctrl_start(dev, lvts_ctrl); 1100 if (ret) { 1101 dev_dbg(dev, "Failed to start controller"); 1102 return ret; 1103 } 1104 } 1105 1106 return lvts_debugfs_init(dev, lvts_td); 1107 } 1108 1109 static int lvts_probe(struct platform_device *pdev) 1110 { 1111 const struct lvts_data *lvts_data; 1112 struct lvts_domain *lvts_td; 1113 struct device *dev = &pdev->dev; 1114 struct resource *res; 1115 int irq, ret; 1116 1117 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); 1118 if (!lvts_td) 1119 return -ENOMEM; 1120 1121 lvts_data = of_device_get_match_data(dev); 1122 1123 lvts_td->clk = devm_clk_get_enabled(dev, NULL); 1124 if (IS_ERR(lvts_td->clk)) 1125 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); 1126 1127 res = platform_get_mem_or_io(pdev, 0); 1128 if (!res) 1129 return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); 1130 1131 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1132 if (IS_ERR(lvts_td->base)) 1133 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); 1134 1135 lvts_td->reset = devm_reset_control_get_by_index(dev, 0); 1136 if (IS_ERR(lvts_td->reset)) 1137 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); 1138 1139 irq = platform_get_irq(pdev, 0); 1140 if (irq < 0) 1141 return dev_err_probe(dev, irq, "No irq resource\n"); 1142 1143 ret = lvts_domain_init(dev, lvts_td, lvts_data); 1144 if (ret) 1145 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); 1146 1147 /* 1148 * At this point the LVTS is initialized and enabled. We can 1149 * safely enable the interrupt. 1150 */ 1151 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, 1152 IRQF_ONESHOT, dev_name(dev), lvts_td); 1153 if (ret) 1154 return dev_err_probe(dev, ret, "Failed to request interrupt\n"); 1155 1156 platform_set_drvdata(pdev, lvts_td); 1157 1158 return 0; 1159 } 1160 1161 static int lvts_remove(struct platform_device *pdev) 1162 { 1163 struct lvts_domain *lvts_td; 1164 int i; 1165 1166 lvts_td = platform_get_drvdata(pdev); 1167 1168 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1169 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1170 1171 lvts_debugfs_exit(lvts_td); 1172 1173 return 0; 1174 } 1175 1176 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { 1177 { 1178 .cal_offset = { 0x04, 0x07 }, 1179 .lvts_sensor = { 1180 { .dt_id = MT8195_MCU_BIG_CPU0 }, 1181 { .dt_id = MT8195_MCU_BIG_CPU1 } 1182 }, 1183 .num_lvts_sensor = 2, 1184 .offset = 0x0, 1185 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1186 }, 1187 { 1188 .cal_offset = { 0x0d, 0x10 }, 1189 .lvts_sensor = { 1190 { .dt_id = MT8195_MCU_BIG_CPU2 }, 1191 { .dt_id = MT8195_MCU_BIG_CPU3 } 1192 }, 1193 .num_lvts_sensor = 2, 1194 .offset = 0x100, 1195 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1196 }, 1197 { 1198 .cal_offset = { 0x16, 0x19, 0x1c, 0x1f }, 1199 .lvts_sensor = { 1200 { .dt_id = MT8195_MCU_LITTLE_CPU0 }, 1201 { .dt_id = MT8195_MCU_LITTLE_CPU1 }, 1202 { .dt_id = MT8195_MCU_LITTLE_CPU2 }, 1203 { .dt_id = MT8195_MCU_LITTLE_CPU3 } 1204 }, 1205 .num_lvts_sensor = 4, 1206 .offset = 0x200, 1207 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1208 } 1209 }; 1210 1211 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { 1212 { 1213 .cal_offset = { 0x25, 0x28 }, 1214 .lvts_sensor = { 1215 { .dt_id = MT8195_AP_VPU0 }, 1216 { .dt_id = MT8195_AP_VPU1 } 1217 }, 1218 .num_lvts_sensor = 2, 1219 .offset = 0x0, 1220 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1221 }, 1222 { 1223 .cal_offset = { 0x2e, 0x31 }, 1224 .lvts_sensor = { 1225 { .dt_id = MT8195_AP_GPU0 }, 1226 { .dt_id = MT8195_AP_GPU1 } 1227 }, 1228 .num_lvts_sensor = 2, 1229 .offset = 0x100, 1230 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1231 }, 1232 { 1233 .cal_offset = { 0x37, 0x3a, 0x3d }, 1234 .lvts_sensor = { 1235 { .dt_id = MT8195_AP_VDEC }, 1236 { .dt_id = MT8195_AP_IMG }, 1237 { .dt_id = MT8195_AP_INFRA }, 1238 }, 1239 .num_lvts_sensor = 3, 1240 .offset = 0x200, 1241 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1242 }, 1243 { 1244 .cal_offset = { 0x43, 0x46 }, 1245 .lvts_sensor = { 1246 { .dt_id = MT8195_AP_CAM0 }, 1247 { .dt_id = MT8195_AP_CAM1 } 1248 }, 1249 .num_lvts_sensor = 2, 1250 .offset = 0x300, 1251 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1252 } 1253 }; 1254 1255 static const struct lvts_data mt8195_lvts_mcu_data = { 1256 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, 1257 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), 1258 }; 1259 1260 static const struct lvts_data mt8195_lvts_ap_data = { 1261 .lvts_ctrl = mt8195_lvts_ap_data_ctrl, 1262 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), 1263 }; 1264 1265 static const struct of_device_id lvts_of_match[] = { 1266 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, 1267 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, 1268 {}, 1269 }; 1270 MODULE_DEVICE_TABLE(of, lvts_of_match); 1271 1272 static struct platform_driver lvts_driver = { 1273 .probe = lvts_probe, 1274 .remove = lvts_remove, 1275 .driver = { 1276 .name = "mtk-lvts-thermal", 1277 .of_match_table = lvts_of_match, 1278 }, 1279 }; 1280 module_platform_driver(lvts_driver); 1281 1282 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>"); 1283 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); 1284 MODULE_LICENSE("GPL"); 1285