1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015 MediaTek Inc.
4  * Author: Hanyi Wu <hanyi.wu@mediatek.com>
5  *         Sascha Hauer <s.hauer@pengutronix.de>
6  *         Dawei Chien <dawei.chien@mediatek.com>
7  *         Louis Yu <louis.yu@mediatek.com>
8  */
9 
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/interrupt.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/nvmem-consumer.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_device.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
21 #include <linux/io.h>
22 #include <linux/thermal.h>
23 #include <linux/reset.h>
24 #include <linux/types.h>
25 
26 #include "../thermal_hwmon.h"
27 
28 /* AUXADC Registers */
29 #define AUXADC_CON1_SET_V	0x008
30 #define AUXADC_CON1_CLR_V	0x00c
31 #define AUXADC_CON2_V		0x010
32 #define AUXADC_DATA(channel)	(0x14 + (channel) * 4)
33 
34 #define APMIXED_SYS_TS_CON0	0x600
35 #define APMIXED_SYS_TS_CON1	0x604
36 
37 /* Thermal Controller Registers */
38 #define TEMP_MONCTL0		0x000
39 #define TEMP_MONCTL1		0x004
40 #define TEMP_MONCTL2		0x008
41 #define TEMP_MONIDET0		0x014
42 #define TEMP_MONIDET1		0x018
43 #define TEMP_MSRCTL0		0x038
44 #define TEMP_MSRCTL1		0x03c
45 #define TEMP_AHBPOLL		0x040
46 #define TEMP_AHBTO		0x044
47 #define TEMP_ADCPNP0		0x048
48 #define TEMP_ADCPNP1		0x04c
49 #define TEMP_ADCPNP2		0x050
50 #define TEMP_ADCPNP3		0x0b4
51 
52 #define TEMP_ADCMUX		0x054
53 #define TEMP_ADCEN		0x060
54 #define TEMP_PNPMUXADDR		0x064
55 #define TEMP_ADCMUXADDR		0x068
56 #define TEMP_ADCENADDR		0x074
57 #define TEMP_ADCVALIDADDR	0x078
58 #define TEMP_ADCVOLTADDR	0x07c
59 #define TEMP_RDCTRL		0x080
60 #define TEMP_ADCVALIDMASK	0x084
61 #define TEMP_ADCVOLTAGESHIFT	0x088
62 #define TEMP_ADCWRITECTRL	0x08c
63 #define TEMP_MSR0		0x090
64 #define TEMP_MSR1		0x094
65 #define TEMP_MSR2		0x098
66 #define TEMP_MSR3		0x0B8
67 
68 #define TEMP_SPARE0		0x0f0
69 
70 #define TEMP_ADCPNP0_1          0x148
71 #define TEMP_ADCPNP1_1          0x14c
72 #define TEMP_ADCPNP2_1          0x150
73 #define TEMP_MSR0_1             0x190
74 #define TEMP_MSR1_1             0x194
75 #define TEMP_MSR2_1             0x198
76 #define TEMP_ADCPNP3_1          0x1b4
77 #define TEMP_MSR3_1             0x1B8
78 
79 #define PTPCORESEL		0x400
80 
81 #define TEMP_MONCTL1_PERIOD_UNIT(x)	((x) & 0x3ff)
82 
83 #define TEMP_MONCTL2_FILTER_INTERVAL(x)	(((x) & 0x3ff) << 16)
84 #define TEMP_MONCTL2_SENSOR_INTERVAL(x)	((x) & 0x3ff)
85 
86 #define TEMP_AHBPOLL_ADC_POLL_INTERVAL(x)	(x)
87 
88 #define TEMP_ADCWRITECTRL_ADC_PNP_WRITE		BIT(0)
89 #define TEMP_ADCWRITECTRL_ADC_MUX_WRITE		BIT(1)
90 
91 #define TEMP_ADCVALIDMASK_VALID_HIGH		BIT(5)
92 #define TEMP_ADCVALIDMASK_VALID_POS(bit)	(bit)
93 
94 /* MT8173 thermal sensors */
95 #define MT8173_TS1	0
96 #define MT8173_TS2	1
97 #define MT8173_TS3	2
98 #define MT8173_TS4	3
99 #define MT8173_TSABB	4
100 
101 /* AUXADC channel 11 is used for the temperature sensors */
102 #define MT8173_TEMP_AUXADC_CHANNEL	11
103 
104 /* The total number of temperature sensors in the MT8173 */
105 #define MT8173_NUM_SENSORS		5
106 
107 /* The number of banks in the MT8173 */
108 #define MT8173_NUM_ZONES		4
109 
110 /* The number of sensing points per bank */
111 #define MT8173_NUM_SENSORS_PER_ZONE	4
112 
113 /* The number of controller in the MT8173 */
114 #define MT8173_NUM_CONTROLLER		1
115 
116 /* The calibration coefficient of sensor  */
117 #define MT8173_CALIBRATION	165
118 
119 /* Valid temperatures range */
120 #define MT8173_TEMP_MIN		-20000
121 #define MT8173_TEMP_MAX		150000
122 
123 /*
124  * Layout of the fuses providing the calibration data
125  * These macros could be used for MT8183, MT8173, MT2701, and MT2712.
126  * MT8183 has 6 sensors and needs 6 VTS calibration data.
127  * MT8173 has 5 sensors and needs 5 VTS calibration data.
128  * MT2701 has 3 sensors and needs 3 VTS calibration data.
129  * MT2712 has 4 sensors and needs 4 VTS calibration data.
130  */
131 #define CALIB_BUF0_VALID_V1		BIT(0)
132 #define CALIB_BUF1_ADC_GE_V1(x)		(((x) >> 22) & 0x3ff)
133 #define CALIB_BUF0_VTS_TS1_V1(x)	(((x) >> 17) & 0x1ff)
134 #define CALIB_BUF0_VTS_TS2_V1(x)	(((x) >> 8) & 0x1ff)
135 #define CALIB_BUF1_VTS_TS3_V1(x)	(((x) >> 0) & 0x1ff)
136 #define CALIB_BUF2_VTS_TS4_V1(x)	(((x) >> 23) & 0x1ff)
137 #define CALIB_BUF2_VTS_TS5_V1(x)	(((x) >> 5) & 0x1ff)
138 #define CALIB_BUF2_VTS_TSABB_V1(x)	(((x) >> 14) & 0x1ff)
139 #define CALIB_BUF0_DEGC_CALI_V1(x)	(((x) >> 1) & 0x3f)
140 #define CALIB_BUF0_O_SLOPE_V1(x)	(((x) >> 26) & 0x3f)
141 #define CALIB_BUF0_O_SLOPE_SIGN_V1(x)	(((x) >> 7) & 0x1)
142 #define CALIB_BUF1_ID_V1(x)		(((x) >> 9) & 0x1)
143 
144 /*
145  * Layout of the fuses providing the calibration data
146  * These macros could be used for MT7622.
147  */
148 #define CALIB_BUF0_ADC_OE_V2(x)		(((x) >> 22) & 0x3ff)
149 #define CALIB_BUF0_ADC_GE_V2(x)		(((x) >> 12) & 0x3ff)
150 #define CALIB_BUF0_DEGC_CALI_V2(x)	(((x) >> 6) & 0x3f)
151 #define CALIB_BUF0_O_SLOPE_V2(x)	(((x) >> 0) & 0x3f)
152 #define CALIB_BUF1_VTS_TS1_V2(x)	(((x) >> 23) & 0x1ff)
153 #define CALIB_BUF1_VTS_TS2_V2(x)	(((x) >> 14) & 0x1ff)
154 #define CALIB_BUF1_VTS_TSABB_V2(x)	(((x) >> 5) & 0x1ff)
155 #define CALIB_BUF1_VALID_V2(x)		(((x) >> 4) & 0x1)
156 #define CALIB_BUF1_O_SLOPE_SIGN_V2(x)	(((x) >> 3) & 0x1)
157 
158 /*
159  * Layout of the fuses providing the calibration data
160  * These macros can be used for MT7981 and MT7986.
161  */
162 #define CALIB_BUF0_ADC_GE_V3(x)		(((x) >> 0) & 0x3ff)
163 #define CALIB_BUF0_DEGC_CALI_V3(x)	(((x) >> 20) & 0x3f)
164 #define CALIB_BUF0_O_SLOPE_V3(x)	(((x) >> 26) & 0x3f)
165 #define CALIB_BUF1_VTS_TS1_V3(x)	(((x) >> 0) & 0x1ff)
166 #define CALIB_BUF1_VTS_TS2_V3(x)	(((x) >> 21) & 0x1ff)
167 #define CALIB_BUF1_VTS_TSABB_V3(x)	(((x) >> 9) & 0x1ff)
168 #define CALIB_BUF1_VALID_V3(x)		(((x) >> 18) & 0x1)
169 #define CALIB_BUF1_O_SLOPE_SIGN_V3(x)	(((x) >> 19) & 0x1)
170 #define CALIB_BUF1_ID_V3(x)		(((x) >> 20) & 0x1)
171 
172 enum {
173 	VTS1,
174 	VTS2,
175 	VTS3,
176 	VTS4,
177 	VTS5,
178 	VTSABB,
179 	MAX_NUM_VTS,
180 };
181 
182 enum mtk_thermal_version {
183 	MTK_THERMAL_V1 = 1,
184 	MTK_THERMAL_V2,
185 	MTK_THERMAL_V3,
186 };
187 
188 /* MT2701 thermal sensors */
189 #define MT2701_TS1	0
190 #define MT2701_TS2	1
191 #define MT2701_TSABB	2
192 
193 /* AUXADC channel 11 is used for the temperature sensors */
194 #define MT2701_TEMP_AUXADC_CHANNEL	11
195 
196 /* The total number of temperature sensors in the MT2701 */
197 #define MT2701_NUM_SENSORS	3
198 
199 /* The number of sensing points per bank */
200 #define MT2701_NUM_SENSORS_PER_ZONE	3
201 
202 /* The number of controller in the MT2701 */
203 #define MT2701_NUM_CONTROLLER		1
204 
205 /* The calibration coefficient of sensor  */
206 #define MT2701_CALIBRATION	165
207 
208 /* MT2712 thermal sensors */
209 #define MT2712_TS1	0
210 #define MT2712_TS2	1
211 #define MT2712_TS3	2
212 #define MT2712_TS4	3
213 
214 /* AUXADC channel 11 is used for the temperature sensors */
215 #define MT2712_TEMP_AUXADC_CHANNEL	11
216 
217 /* The total number of temperature sensors in the MT2712 */
218 #define MT2712_NUM_SENSORS	4
219 
220 /* The number of sensing points per bank */
221 #define MT2712_NUM_SENSORS_PER_ZONE	4
222 
223 /* The number of controller in the MT2712 */
224 #define MT2712_NUM_CONTROLLER		1
225 
226 /* The calibration coefficient of sensor  */
227 #define MT2712_CALIBRATION	165
228 
229 #define MT7622_TEMP_AUXADC_CHANNEL	11
230 #define MT7622_NUM_SENSORS		1
231 #define MT7622_NUM_ZONES		1
232 #define MT7622_NUM_SENSORS_PER_ZONE	1
233 #define MT7622_TS1	0
234 #define MT7622_NUM_CONTROLLER		1
235 
236 /* The maximum number of banks */
237 #define MAX_NUM_ZONES		8
238 
239 /* The calibration coefficient of sensor  */
240 #define MT7622_CALIBRATION	165
241 
242 /* MT8183 thermal sensors */
243 #define MT8183_TS1	0
244 #define MT8183_TS2	1
245 #define MT8183_TS3	2
246 #define MT8183_TS4	3
247 #define MT8183_TS5	4
248 #define MT8183_TSABB	5
249 
250 /* AUXADC channel  is used for the temperature sensors */
251 #define MT8183_TEMP_AUXADC_CHANNEL	11
252 
253 /* The total number of temperature sensors in the MT8183 */
254 #define MT8183_NUM_SENSORS	6
255 
256 /* The number of banks in the MT8183 */
257 #define MT8183_NUM_ZONES               1
258 
259 /* The number of sensing points per bank */
260 #define MT8183_NUM_SENSORS_PER_ZONE	 6
261 
262 /* The number of controller in the MT8183 */
263 #define MT8183_NUM_CONTROLLER		2
264 
265 /* The calibration coefficient of sensor  */
266 #define MT8183_CALIBRATION	153
267 
268 /* AUXADC channel 11 is used for the temperature sensors */
269 #define MT7986_TEMP_AUXADC_CHANNEL	11
270 
271 /* The total number of temperature sensors in the MT7986 */
272 #define MT7986_NUM_SENSORS		1
273 
274 /* The number of banks in the MT7986 */
275 #define MT7986_NUM_ZONES		1
276 
277 /* The number of sensing points per bank */
278 #define MT7986_NUM_SENSORS_PER_ZONE	1
279 
280 /* MT7986 thermal sensors */
281 #define MT7986_TS1			0
282 
283 /* The number of controller in the MT7986 */
284 #define MT7986_NUM_CONTROLLER		1
285 
286 /* The calibration coefficient of sensor  */
287 #define MT7986_CALIBRATION		165
288 
289 /* MT8365 */
290 #define MT8365_TEMP_AUXADC_CHANNEL 11
291 #define MT8365_CALIBRATION 164
292 #define MT8365_NUM_CONTROLLER 1
293 #define MT8365_NUM_BANKS 1
294 #define MT8365_NUM_SENSORS 3
295 #define MT8365_NUM_SENSORS_PER_ZONE 3
296 #define MT8365_TS1 0
297 #define MT8365_TS2 1
298 #define MT8365_TS3 2
299 
300 struct mtk_thermal;
301 
302 struct thermal_bank_cfg {
303 	unsigned int num_sensors;
304 	const int *sensors;
305 };
306 
307 struct mtk_thermal_bank {
308 	struct mtk_thermal *mt;
309 	int id;
310 };
311 
312 struct mtk_thermal_data {
313 	s32 num_banks;
314 	s32 num_sensors;
315 	s32 auxadc_channel;
316 	const int *vts_index;
317 	const int *sensor_mux_values;
318 	const int *msr;
319 	const int *adcpnp;
320 	const int cali_val;
321 	const int num_controller;
322 	const int *controller_offset;
323 	bool need_switch_bank;
324 	struct thermal_bank_cfg bank_data[MAX_NUM_ZONES];
325 	enum mtk_thermal_version version;
326 	u32 apmixed_buffer_ctl_reg;
327 	u32 apmixed_buffer_ctl_mask;
328 	u32 apmixed_buffer_ctl_set;
329 };
330 
331 struct mtk_thermal {
332 	struct device *dev;
333 	void __iomem *thermal_base;
334 
335 	struct clk *clk_peri_therm;
336 	struct clk *clk_auxadc;
337 	/* lock: for getting and putting banks */
338 	struct mutex lock;
339 
340 	/* Calibration values */
341 	s32 adc_ge;
342 	s32 adc_oe;
343 	s32 degc_cali;
344 	s32 o_slope;
345 	s32 o_slope_sign;
346 	s32 vts[MAX_NUM_VTS];
347 
348 	const struct mtk_thermal_data *conf;
349 	struct mtk_thermal_bank banks[MAX_NUM_ZONES];
350 
351 	int (*raw_to_mcelsius)(struct mtk_thermal *mt, int sensno, s32 raw);
352 };
353 
354 /* MT8183 thermal sensor data */
355 static const int mt8183_bank_data[MT8183_NUM_SENSORS] = {
356 	MT8183_TS1, MT8183_TS2, MT8183_TS3, MT8183_TS4, MT8183_TS5, MT8183_TSABB
357 };
358 
359 static const int mt8183_msr[MT8183_NUM_SENSORS_PER_ZONE] = {
360 	TEMP_MSR0_1, TEMP_MSR1_1, TEMP_MSR2_1, TEMP_MSR1, TEMP_MSR0, TEMP_MSR3_1
361 };
362 
363 static const int mt8183_adcpnp[MT8183_NUM_SENSORS_PER_ZONE] = {
364 	TEMP_ADCPNP0_1, TEMP_ADCPNP1_1, TEMP_ADCPNP2_1,
365 	TEMP_ADCPNP1, TEMP_ADCPNP0, TEMP_ADCPNP3_1
366 };
367 
368 static const int mt8183_mux_values[MT8183_NUM_SENSORS] = { 0, 1, 2, 3, 4, 0 };
369 static const int mt8183_tc_offset[MT8183_NUM_CONTROLLER] = {0x0, 0x100};
370 
371 static const int mt8183_vts_index[MT8183_NUM_SENSORS] = {
372 	VTS1, VTS2, VTS3, VTS4, VTS5, VTSABB
373 };
374 
375 /* MT8173 thermal sensor data */
376 static const int mt8173_bank_data[MT8173_NUM_ZONES][3] = {
377 	{ MT8173_TS2, MT8173_TS3 },
378 	{ MT8173_TS2, MT8173_TS4 },
379 	{ MT8173_TS1, MT8173_TS2, MT8173_TSABB },
380 	{ MT8173_TS2 },
381 };
382 
383 static const int mt8173_msr[MT8173_NUM_SENSORS_PER_ZONE] = {
384 	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
385 };
386 
387 static const int mt8173_adcpnp[MT8173_NUM_SENSORS_PER_ZONE] = {
388 	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
389 };
390 
391 static const int mt8173_mux_values[MT8173_NUM_SENSORS] = { 0, 1, 2, 3, 16 };
392 static const int mt8173_tc_offset[MT8173_NUM_CONTROLLER] = { 0x0, };
393 
394 static const int mt8173_vts_index[MT8173_NUM_SENSORS] = {
395 	VTS1, VTS2, VTS3, VTS4, VTSABB
396 };
397 
398 /* MT2701 thermal sensor data */
399 static const int mt2701_bank_data[MT2701_NUM_SENSORS] = {
400 	MT2701_TS1, MT2701_TS2, MT2701_TSABB
401 };
402 
403 static const int mt2701_msr[MT2701_NUM_SENSORS_PER_ZONE] = {
404 	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
405 };
406 
407 static const int mt2701_adcpnp[MT2701_NUM_SENSORS_PER_ZONE] = {
408 	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
409 };
410 
411 static const int mt2701_mux_values[MT2701_NUM_SENSORS] = { 0, 1, 16 };
412 static const int mt2701_tc_offset[MT2701_NUM_CONTROLLER] = { 0x0, };
413 
414 static const int mt2701_vts_index[MT2701_NUM_SENSORS] = {
415 	VTS1, VTS2, VTS3
416 };
417 
418 /* MT2712 thermal sensor data */
419 static const int mt2712_bank_data[MT2712_NUM_SENSORS] = {
420 	MT2712_TS1, MT2712_TS2, MT2712_TS3, MT2712_TS4
421 };
422 
423 static const int mt2712_msr[MT2712_NUM_SENSORS_PER_ZONE] = {
424 	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2, TEMP_MSR3
425 };
426 
427 static const int mt2712_adcpnp[MT2712_NUM_SENSORS_PER_ZONE] = {
428 	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2, TEMP_ADCPNP3
429 };
430 
431 static const int mt2712_mux_values[MT2712_NUM_SENSORS] = { 0, 1, 2, 3 };
432 static const int mt2712_tc_offset[MT2712_NUM_CONTROLLER] = { 0x0, };
433 
434 static const int mt2712_vts_index[MT2712_NUM_SENSORS] = {
435 	VTS1, VTS2, VTS3, VTS4
436 };
437 
438 /* MT7622 thermal sensor data */
439 static const int mt7622_bank_data[MT7622_NUM_SENSORS] = { MT7622_TS1, };
440 static const int mt7622_msr[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
441 static const int mt7622_adcpnp[MT7622_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
442 static const int mt7622_mux_values[MT7622_NUM_SENSORS] = { 0, };
443 static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
444 static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
445 
446 /* MT7986 thermal sensor data */
447 static const int mt7986_bank_data[MT7986_NUM_SENSORS] = { MT7986_TS1, };
448 static const int mt7986_msr[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_MSR0, };
449 static const int mt7986_adcpnp[MT7986_NUM_SENSORS_PER_ZONE] = { TEMP_ADCPNP0, };
450 static const int mt7986_mux_values[MT7986_NUM_SENSORS] = { 0, };
451 static const int mt7986_vts_index[MT7986_NUM_SENSORS] = { VTS1 };
452 static const int mt7986_tc_offset[MT7986_NUM_CONTROLLER] = { 0x0, };
453 
454 /* MT8365 thermal sensor data */
455 static const int mt8365_bank_data[MT8365_NUM_SENSORS] = {
456 	MT8365_TS1, MT8365_TS2, MT8365_TS3
457 };
458 
459 static const int mt8365_msr[MT8365_NUM_SENSORS_PER_ZONE] = {
460 	TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
461 };
462 
463 static const int mt8365_adcpnp[MT8365_NUM_SENSORS_PER_ZONE] = {
464 	TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
465 };
466 
467 static const int mt8365_mux_values[MT8365_NUM_SENSORS] = { 0, 1, 2 };
468 static const int mt8365_tc_offset[MT8365_NUM_CONTROLLER] = { 0 };
469 
470 static const int mt8365_vts_index[MT8365_NUM_SENSORS] = { VTS1, VTS2, VTS3 };
471 
472 /*
473  * The MT8173 thermal controller has four banks. Each bank can read up to
474  * four temperature sensors simultaneously. The MT8173 has a total of 5
475  * temperature sensors. We use each bank to measure a certain area of the
476  * SoC. Since TS2 is located centrally in the SoC it is influenced by multiple
477  * areas, hence is used in different banks.
478  *
479  * The thermal core only gets the maximum temperature of all banks, so
480  * the bank concept wouldn't be necessary here. However, the SVS (Smart
481  * Voltage Scaling) unit makes its decisions based on the same bank
482  * data, and this indeed needs the temperatures of the individual banks
483  * for making better decisions.
484  */
485 static const struct mtk_thermal_data mt8173_thermal_data = {
486 	.auxadc_channel = MT8173_TEMP_AUXADC_CHANNEL,
487 	.num_banks = MT8173_NUM_ZONES,
488 	.num_sensors = MT8173_NUM_SENSORS,
489 	.vts_index = mt8173_vts_index,
490 	.cali_val = MT8173_CALIBRATION,
491 	.num_controller = MT8173_NUM_CONTROLLER,
492 	.controller_offset = mt8173_tc_offset,
493 	.need_switch_bank = true,
494 	.bank_data = {
495 		{
496 			.num_sensors = 2,
497 			.sensors = mt8173_bank_data[0],
498 		}, {
499 			.num_sensors = 2,
500 			.sensors = mt8173_bank_data[1],
501 		}, {
502 			.num_sensors = 3,
503 			.sensors = mt8173_bank_data[2],
504 		}, {
505 			.num_sensors = 1,
506 			.sensors = mt8173_bank_data[3],
507 		},
508 	},
509 	.msr = mt8173_msr,
510 	.adcpnp = mt8173_adcpnp,
511 	.sensor_mux_values = mt8173_mux_values,
512 	.version = MTK_THERMAL_V1,
513 };
514 
515 /*
516  * The MT2701 thermal controller has one bank, which can read up to
517  * three temperature sensors simultaneously. The MT2701 has a total of 3
518  * temperature sensors.
519  *
520  * The thermal core only gets the maximum temperature of this one bank,
521  * so the bank concept wouldn't be necessary here. However, the SVS (Smart
522  * Voltage Scaling) unit makes its decisions based on the same bank
523  * data.
524  */
525 static const struct mtk_thermal_data mt2701_thermal_data = {
526 	.auxadc_channel = MT2701_TEMP_AUXADC_CHANNEL,
527 	.num_banks = 1,
528 	.num_sensors = MT2701_NUM_SENSORS,
529 	.vts_index = mt2701_vts_index,
530 	.cali_val = MT2701_CALIBRATION,
531 	.num_controller = MT2701_NUM_CONTROLLER,
532 	.controller_offset = mt2701_tc_offset,
533 	.need_switch_bank = true,
534 	.bank_data = {
535 		{
536 			.num_sensors = 3,
537 			.sensors = mt2701_bank_data,
538 		},
539 	},
540 	.msr = mt2701_msr,
541 	.adcpnp = mt2701_adcpnp,
542 	.sensor_mux_values = mt2701_mux_values,
543 	.version = MTK_THERMAL_V1,
544 };
545 
546 /*
547  * The MT8365 thermal controller has one bank, which can read up to
548  * four temperature sensors simultaneously. The MT8365 has a total of 3
549  * temperature sensors.
550  *
551  * The thermal core only gets the maximum temperature of this one bank,
552  * so the bank concept wouldn't be necessary here. However, the SVS (Smart
553  * Voltage Scaling) unit makes its decisions based on the same bank
554  * data.
555  */
556 static const struct mtk_thermal_data mt8365_thermal_data = {
557 	.auxadc_channel = MT8365_TEMP_AUXADC_CHANNEL,
558 	.num_banks = MT8365_NUM_BANKS,
559 	.num_sensors = MT8365_NUM_SENSORS,
560 	.vts_index = mt8365_vts_index,
561 	.cali_val = MT8365_CALIBRATION,
562 	.num_controller = MT8365_NUM_CONTROLLER,
563 	.controller_offset = mt8365_tc_offset,
564 	.need_switch_bank = false,
565 	.bank_data = {
566 		{
567 			.num_sensors = MT8365_NUM_SENSORS,
568 			.sensors = mt8365_bank_data
569 		},
570 	},
571 	.msr = mt8365_msr,
572 	.adcpnp = mt8365_adcpnp,
573 	.sensor_mux_values = mt8365_mux_values,
574 	.version = MTK_THERMAL_V1,
575 	.apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON0,
576 	.apmixed_buffer_ctl_mask = (u32) ~GENMASK(29, 28),
577 	.apmixed_buffer_ctl_set = 0,
578 };
579 
580 /*
581  * The MT2712 thermal controller has one bank, which can read up to
582  * four temperature sensors simultaneously. The MT2712 has a total of 4
583  * temperature sensors.
584  *
585  * The thermal core only gets the maximum temperature of this one bank,
586  * so the bank concept wouldn't be necessary here. However, the SVS (Smart
587  * Voltage Scaling) unit makes its decisions based on the same bank
588  * data.
589  */
590 static const struct mtk_thermal_data mt2712_thermal_data = {
591 	.auxadc_channel = MT2712_TEMP_AUXADC_CHANNEL,
592 	.num_banks = 1,
593 	.num_sensors = MT2712_NUM_SENSORS,
594 	.vts_index = mt2712_vts_index,
595 	.cali_val = MT2712_CALIBRATION,
596 	.num_controller = MT2712_NUM_CONTROLLER,
597 	.controller_offset = mt2712_tc_offset,
598 	.need_switch_bank = true,
599 	.bank_data = {
600 		{
601 			.num_sensors = 4,
602 			.sensors = mt2712_bank_data,
603 		},
604 	},
605 	.msr = mt2712_msr,
606 	.adcpnp = mt2712_adcpnp,
607 	.sensor_mux_values = mt2712_mux_values,
608 	.version = MTK_THERMAL_V1,
609 };
610 
611 /*
612  * MT7622 have only one sensing point which uses AUXADC Channel 11 for raw data
613  * access.
614  */
615 static const struct mtk_thermal_data mt7622_thermal_data = {
616 	.auxadc_channel = MT7622_TEMP_AUXADC_CHANNEL,
617 	.num_banks = MT7622_NUM_ZONES,
618 	.num_sensors = MT7622_NUM_SENSORS,
619 	.vts_index = mt7622_vts_index,
620 	.cali_val = MT7622_CALIBRATION,
621 	.num_controller = MT7622_NUM_CONTROLLER,
622 	.controller_offset = mt7622_tc_offset,
623 	.need_switch_bank = true,
624 	.bank_data = {
625 		{
626 			.num_sensors = 1,
627 			.sensors = mt7622_bank_data,
628 		},
629 	},
630 	.msr = mt7622_msr,
631 	.adcpnp = mt7622_adcpnp,
632 	.sensor_mux_values = mt7622_mux_values,
633 	.version = MTK_THERMAL_V2,
634 	.apmixed_buffer_ctl_reg = APMIXED_SYS_TS_CON1,
635 	.apmixed_buffer_ctl_mask = GENMASK(31, 6) | BIT(3),
636 	.apmixed_buffer_ctl_set = BIT(0),
637 };
638 
639 /*
640  * The MT8183 thermal controller has one bank for the current SW framework.
641  * The MT8183 has a total of 6 temperature sensors.
642  * There are two thermal controller to control the six sensor.
643  * The first one bind 2 sensor, and the other bind 4 sensors.
644  * The thermal core only gets the maximum temperature of all sensor, so
645  * the bank concept wouldn't be necessary here. However, the SVS (Smart
646  * Voltage Scaling) unit makes its decisions based on the same bank
647  * data, and this indeed needs the temperatures of the individual banks
648  * for making better decisions.
649  */
650 static const struct mtk_thermal_data mt8183_thermal_data = {
651 	.auxadc_channel = MT8183_TEMP_AUXADC_CHANNEL,
652 	.num_banks = MT8183_NUM_ZONES,
653 	.num_sensors = MT8183_NUM_SENSORS,
654 	.vts_index = mt8183_vts_index,
655 	.cali_val = MT8183_CALIBRATION,
656 	.num_controller = MT8183_NUM_CONTROLLER,
657 	.controller_offset = mt8183_tc_offset,
658 	.need_switch_bank = false,
659 	.bank_data = {
660 		{
661 			.num_sensors = 6,
662 			.sensors = mt8183_bank_data,
663 		},
664 	},
665 
666 	.msr = mt8183_msr,
667 	.adcpnp = mt8183_adcpnp,
668 	.sensor_mux_values = mt8183_mux_values,
669 	.version = MTK_THERMAL_V1,
670 };
671 
672 /*
673  * MT7986 uses AUXADC Channel 11 for raw data access.
674  */
675 static const struct mtk_thermal_data mt7986_thermal_data = {
676 	.auxadc_channel = MT7986_TEMP_AUXADC_CHANNEL,
677 	.num_banks = MT7986_NUM_ZONES,
678 	.num_sensors = MT7986_NUM_SENSORS,
679 	.vts_index = mt7986_vts_index,
680 	.cali_val = MT7986_CALIBRATION,
681 	.num_controller = MT7986_NUM_CONTROLLER,
682 	.controller_offset = mt7986_tc_offset,
683 	.need_switch_bank = true,
684 	.bank_data = {
685 		{
686 			.num_sensors = 1,
687 			.sensors = mt7986_bank_data,
688 		},
689 	},
690 	.msr = mt7986_msr,
691 	.adcpnp = mt7986_adcpnp,
692 	.sensor_mux_values = mt7986_mux_values,
693 	.version = MTK_THERMAL_V3,
694 };
695 
696 static bool mtk_thermal_temp_is_valid(int temp)
697 {
698 	return (temp >= MT8173_TEMP_MIN) && (temp <= MT8173_TEMP_MAX);
699 }
700 
701 /**
702  * raw_to_mcelsius_v1 - convert a raw ADC value to mcelsius
703  * @mt:	The thermal controller
704  * @sensno:	sensor number
705  * @raw:	raw ADC value
706  *
707  * This converts the raw ADC value to mcelsius using the SoC specific
708  * calibration constants
709  */
710 static int raw_to_mcelsius_v1(struct mtk_thermal *mt, int sensno, s32 raw)
711 {
712 	s32 tmp;
713 
714 	raw &= 0xfff;
715 
716 	tmp = 203450520 << 3;
717 	tmp /= mt->conf->cali_val + mt->o_slope;
718 	tmp /= 10000 + mt->adc_ge;
719 	tmp *= raw - mt->vts[sensno] - 3350;
720 	tmp >>= 3;
721 
722 	return mt->degc_cali * 500 - tmp;
723 }
724 
725 static int raw_to_mcelsius_v2(struct mtk_thermal *mt, int sensno, s32 raw)
726 {
727 	s32 format_1;
728 	s32 format_2;
729 	s32 g_oe;
730 	s32 g_gain;
731 	s32 g_x_roomt;
732 	s32 tmp;
733 
734 	if (raw == 0)
735 		return 0;
736 
737 	raw &= 0xfff;
738 	g_gain = 10000 + (((mt->adc_ge - 512) * 10000) >> 12);
739 	g_oe = mt->adc_oe - 512;
740 	format_1 = mt->vts[VTS2] + 3105 - g_oe;
741 	format_2 = (mt->degc_cali * 10) >> 1;
742 	g_x_roomt = (((format_1 * 10000) >> 12) * 10000) / g_gain;
743 
744 	tmp = (((((raw - g_oe) * 10000) >> 12) * 10000) / g_gain) - g_x_roomt;
745 	tmp = tmp * 10 * 100 / 11;
746 
747 	if (mt->o_slope_sign == 0)
748 		tmp = tmp / (165 - mt->o_slope);
749 	else
750 		tmp = tmp / (165 + mt->o_slope);
751 
752 	return (format_2 - tmp) * 100;
753 }
754 
755 static int raw_to_mcelsius_v3(struct mtk_thermal *mt, int sensno, s32 raw)
756 {
757 	s32 tmp;
758 
759 	if (raw == 0)
760 		return 0;
761 
762 	raw &= 0xfff;
763 	tmp = 100000 * 15 / 16 * 10000;
764 	tmp /= 4096 - 512 + mt->adc_ge;
765 	tmp /= 1490;
766 	tmp *= raw - mt->vts[sensno] - 2900;
767 
768 	return mt->degc_cali * 500 - tmp;
769 }
770 
771 /**
772  * mtk_thermal_get_bank - get bank
773  * @bank:	The bank
774  *
775  * The bank registers are banked, we have to select a bank in the
776  * PTPCORESEL register to access it.
777  */
778 static void mtk_thermal_get_bank(struct mtk_thermal_bank *bank)
779 {
780 	struct mtk_thermal *mt = bank->mt;
781 	u32 val;
782 
783 	if (mt->conf->need_switch_bank) {
784 		mutex_lock(&mt->lock);
785 
786 		val = readl(mt->thermal_base + PTPCORESEL);
787 		val &= ~0xf;
788 		val |= bank->id;
789 		writel(val, mt->thermal_base + PTPCORESEL);
790 	}
791 }
792 
793 /**
794  * mtk_thermal_put_bank - release bank
795  * @bank:	The bank
796  *
797  * release a bank previously taken with mtk_thermal_get_bank,
798  */
799 static void mtk_thermal_put_bank(struct mtk_thermal_bank *bank)
800 {
801 	struct mtk_thermal *mt = bank->mt;
802 
803 	if (mt->conf->need_switch_bank)
804 		mutex_unlock(&mt->lock);
805 }
806 
807 /**
808  * mtk_thermal_bank_temperature - get the temperature of a bank
809  * @bank:	The bank
810  *
811  * The temperature of a bank is considered the maximum temperature of
812  * the sensors associated to the bank.
813  */
814 static int mtk_thermal_bank_temperature(struct mtk_thermal_bank *bank)
815 {
816 	struct mtk_thermal *mt = bank->mt;
817 	const struct mtk_thermal_data *conf = mt->conf;
818 	int i, temp = INT_MIN, max = INT_MIN;
819 	u32 raw;
820 
821 	for (i = 0; i < conf->bank_data[bank->id].num_sensors; i++) {
822 		raw = readl(mt->thermal_base + conf->msr[i]);
823 
824 		temp = mt->raw_to_mcelsius(
825 			mt, conf->bank_data[bank->id].sensors[i], raw);
826 
827 		/*
828 		 * Depending on the filt/sen intervals and ADC polling time,
829 		 * we may need up to 60 milliseconds after initialization: this
830 		 * will result in the first reading containing an out of range
831 		 * temperature value.
832 		 * Validate the reading to both address the aforementioned issue
833 		 * and to eventually avoid bogus readings during runtime in the
834 		 * event that the AUXADC gets unstable due to high EMI, etc.
835 		 */
836 		if (!mtk_thermal_temp_is_valid(temp))
837 			temp = THERMAL_TEMP_INVALID;
838 
839 		if (temp > max)
840 			max = temp;
841 	}
842 
843 	return max;
844 }
845 
846 static int mtk_read_temp(struct thermal_zone_device *tz, int *temperature)
847 {
848 	struct mtk_thermal *mt = thermal_zone_device_priv(tz);
849 	int i;
850 	int tempmax = INT_MIN;
851 
852 	for (i = 0; i < mt->conf->num_banks; i++) {
853 		struct mtk_thermal_bank *bank = &mt->banks[i];
854 
855 		mtk_thermal_get_bank(bank);
856 
857 		tempmax = max(tempmax, mtk_thermal_bank_temperature(bank));
858 
859 		mtk_thermal_put_bank(bank);
860 	}
861 
862 	*temperature = tempmax;
863 
864 	return 0;
865 }
866 
867 static const struct thermal_zone_device_ops mtk_thermal_ops = {
868 	.get_temp = mtk_read_temp,
869 };
870 
871 static void mtk_thermal_init_bank(struct mtk_thermal *mt, int num,
872 				  u32 apmixed_phys_base, u32 auxadc_phys_base,
873 				  int ctrl_id)
874 {
875 	struct mtk_thermal_bank *bank = &mt->banks[num];
876 	const struct mtk_thermal_data *conf = mt->conf;
877 	int i;
878 
879 	int offset = mt->conf->controller_offset[ctrl_id];
880 	void __iomem *controller_base = mt->thermal_base + offset;
881 
882 	bank->id = num;
883 	bank->mt = mt;
884 
885 	mtk_thermal_get_bank(bank);
886 
887 	/* bus clock 66M counting unit is 12 * 15.15ns * 256 = 46.540us */
888 	writel(TEMP_MONCTL1_PERIOD_UNIT(12), controller_base + TEMP_MONCTL1);
889 
890 	/*
891 	 * filt interval is 1 * 46.540us = 46.54us,
892 	 * sen interval is 429 * 46.540us = 19.96ms
893 	 */
894 	writel(TEMP_MONCTL2_FILTER_INTERVAL(1) |
895 			TEMP_MONCTL2_SENSOR_INTERVAL(429),
896 			controller_base + TEMP_MONCTL2);
897 
898 	/* poll is set to 10u */
899 	writel(TEMP_AHBPOLL_ADC_POLL_INTERVAL(768),
900 	       controller_base + TEMP_AHBPOLL);
901 
902 	/* temperature sampling control, 1 sample */
903 	writel(0x0, controller_base + TEMP_MSRCTL0);
904 
905 	/* exceed this polling time, IRQ would be inserted */
906 	writel(0xffffffff, controller_base + TEMP_AHBTO);
907 
908 	/* number of interrupts per event, 1 is enough */
909 	writel(0x0, controller_base + TEMP_MONIDET0);
910 	writel(0x0, controller_base + TEMP_MONIDET1);
911 
912 	/*
913 	 * The MT8173 thermal controller does not have its own ADC. Instead it
914 	 * uses AHB bus accesses to control the AUXADC. To do this the thermal
915 	 * controller has to be programmed with the physical addresses of the
916 	 * AUXADC registers and with the various bit positions in the AUXADC.
917 	 * Also the thermal controller controls a mux in the APMIXEDSYS register
918 	 * space.
919 	 */
920 
921 	/*
922 	 * this value will be stored to TEMP_PNPMUXADDR (TEMP_SPARE0)
923 	 * automatically by hw
924 	 */
925 	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCMUX);
926 
927 	/* AHB address for auxadc mux selection */
928 	writel(auxadc_phys_base + AUXADC_CON1_CLR_V,
929 	       controller_base + TEMP_ADCMUXADDR);
930 
931 	if (mt->conf->version == MTK_THERMAL_V1) {
932 		/* AHB address for pnp sensor mux selection */
933 		writel(apmixed_phys_base + APMIXED_SYS_TS_CON1,
934 		       controller_base + TEMP_PNPMUXADDR);
935 	}
936 
937 	/* AHB value for auxadc enable */
938 	writel(BIT(conf->auxadc_channel), controller_base + TEMP_ADCEN);
939 
940 	/* AHB address for auxadc enable (channel 0 immediate mode selected) */
941 	writel(auxadc_phys_base + AUXADC_CON1_SET_V,
942 	       controller_base + TEMP_ADCENADDR);
943 
944 	/* AHB address for auxadc valid bit */
945 	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
946 	       controller_base + TEMP_ADCVALIDADDR);
947 
948 	/* AHB address for auxadc voltage output */
949 	writel(auxadc_phys_base + AUXADC_DATA(conf->auxadc_channel),
950 	       controller_base + TEMP_ADCVOLTADDR);
951 
952 	/* read valid & voltage are at the same register */
953 	writel(0x0, controller_base + TEMP_RDCTRL);
954 
955 	/* indicate where the valid bit is */
956 	writel(TEMP_ADCVALIDMASK_VALID_HIGH | TEMP_ADCVALIDMASK_VALID_POS(12),
957 	       controller_base + TEMP_ADCVALIDMASK);
958 
959 	/* no shift */
960 	writel(0x0, controller_base + TEMP_ADCVOLTAGESHIFT);
961 
962 	/* enable auxadc mux write transaction */
963 	writel(TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
964 		controller_base + TEMP_ADCWRITECTRL);
965 
966 	for (i = 0; i < conf->bank_data[num].num_sensors; i++)
967 		writel(conf->sensor_mux_values[conf->bank_data[num].sensors[i]],
968 		       mt->thermal_base + conf->adcpnp[i]);
969 
970 	writel((1 << conf->bank_data[num].num_sensors) - 1,
971 	       controller_base + TEMP_MONCTL0);
972 
973 	writel(TEMP_ADCWRITECTRL_ADC_PNP_WRITE |
974 	       TEMP_ADCWRITECTRL_ADC_MUX_WRITE,
975 	       controller_base + TEMP_ADCWRITECTRL);
976 
977 	mtk_thermal_put_bank(bank);
978 }
979 
980 static u64 of_get_phys_base(struct device_node *np)
981 {
982 	struct resource res;
983 
984 	if (of_address_to_resource(np, 0, &res))
985 		return OF_BAD_ADDR;
986 
987 	return res.start;
988 }
989 
990 static int mtk_thermal_extract_efuse_v1(struct mtk_thermal *mt, u32 *buf)
991 {
992 	int i;
993 
994 	if (!(buf[0] & CALIB_BUF0_VALID_V1))
995 		return -EINVAL;
996 
997 	mt->adc_ge = CALIB_BUF1_ADC_GE_V1(buf[1]);
998 
999 	for (i = 0; i < mt->conf->num_sensors; i++) {
1000 		switch (mt->conf->vts_index[i]) {
1001 		case VTS1:
1002 			mt->vts[VTS1] = CALIB_BUF0_VTS_TS1_V1(buf[0]);
1003 			break;
1004 		case VTS2:
1005 			mt->vts[VTS2] = CALIB_BUF0_VTS_TS2_V1(buf[0]);
1006 			break;
1007 		case VTS3:
1008 			mt->vts[VTS3] = CALIB_BUF1_VTS_TS3_V1(buf[1]);
1009 			break;
1010 		case VTS4:
1011 			mt->vts[VTS4] = CALIB_BUF2_VTS_TS4_V1(buf[2]);
1012 			break;
1013 		case VTS5:
1014 			mt->vts[VTS5] = CALIB_BUF2_VTS_TS5_V1(buf[2]);
1015 			break;
1016 		case VTSABB:
1017 			mt->vts[VTSABB] =
1018 				CALIB_BUF2_VTS_TSABB_V1(buf[2]);
1019 			break;
1020 		default:
1021 			break;
1022 		}
1023 	}
1024 
1025 	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V1(buf[0]);
1026 	if (CALIB_BUF1_ID_V1(buf[1]) &
1027 	    CALIB_BUF0_O_SLOPE_SIGN_V1(buf[0]))
1028 		mt->o_slope = -CALIB_BUF0_O_SLOPE_V1(buf[0]);
1029 	else
1030 		mt->o_slope = CALIB_BUF0_O_SLOPE_V1(buf[0]);
1031 
1032 	return 0;
1033 }
1034 
1035 static int mtk_thermal_extract_efuse_v2(struct mtk_thermal *mt, u32 *buf)
1036 {
1037 	if (!CALIB_BUF1_VALID_V2(buf[1]))
1038 		return -EINVAL;
1039 
1040 	mt->adc_oe = CALIB_BUF0_ADC_OE_V2(buf[0]);
1041 	mt->adc_ge = CALIB_BUF0_ADC_GE_V2(buf[0]);
1042 	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V2(buf[0]);
1043 	mt->o_slope = CALIB_BUF0_O_SLOPE_V2(buf[0]);
1044 	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V2(buf[1]);
1045 	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V2(buf[1]);
1046 	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V2(buf[1]);
1047 	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V2(buf[1]);
1048 
1049 	return 0;
1050 }
1051 
1052 static int mtk_thermal_extract_efuse_v3(struct mtk_thermal *mt, u32 *buf)
1053 {
1054 	if (!CALIB_BUF1_VALID_V3(buf[1]))
1055 		return -EINVAL;
1056 
1057 	mt->adc_ge = CALIB_BUF0_ADC_GE_V3(buf[0]);
1058 	mt->degc_cali = CALIB_BUF0_DEGC_CALI_V3(buf[0]);
1059 	mt->o_slope = CALIB_BUF0_O_SLOPE_V3(buf[0]);
1060 	mt->vts[VTS1] = CALIB_BUF1_VTS_TS1_V3(buf[1]);
1061 	mt->vts[VTS2] = CALIB_BUF1_VTS_TS2_V3(buf[1]);
1062 	mt->vts[VTSABB] = CALIB_BUF1_VTS_TSABB_V3(buf[1]);
1063 	mt->o_slope_sign = CALIB_BUF1_O_SLOPE_SIGN_V3(buf[1]);
1064 
1065 	if (CALIB_BUF1_ID_V3(buf[1]) == 0)
1066 		mt->o_slope = 0;
1067 
1068 	return 0;
1069 }
1070 
1071 static int mtk_thermal_get_calibration_data(struct device *dev,
1072 					    struct mtk_thermal *mt)
1073 {
1074 	struct nvmem_cell *cell;
1075 	u32 *buf;
1076 	size_t len;
1077 	int i, ret = 0;
1078 
1079 	/* Start with default values */
1080 	mt->adc_ge = 512;
1081 	mt->adc_oe = 512;
1082 	for (i = 0; i < mt->conf->num_sensors; i++)
1083 		mt->vts[i] = 260;
1084 	mt->degc_cali = 40;
1085 	mt->o_slope = 0;
1086 
1087 	cell = nvmem_cell_get(dev, "calibration-data");
1088 	if (IS_ERR(cell)) {
1089 		if (PTR_ERR(cell) == -EPROBE_DEFER)
1090 			return PTR_ERR(cell);
1091 		return 0;
1092 	}
1093 
1094 	buf = (u32 *)nvmem_cell_read(cell, &len);
1095 
1096 	nvmem_cell_put(cell);
1097 
1098 	if (IS_ERR(buf))
1099 		return PTR_ERR(buf);
1100 
1101 	if (len < 3 * sizeof(u32)) {
1102 		dev_warn(dev, "invalid calibration data\n");
1103 		ret = -EINVAL;
1104 		goto out;
1105 	}
1106 
1107 	switch (mt->conf->version) {
1108 	case MTK_THERMAL_V1:
1109 		ret = mtk_thermal_extract_efuse_v1(mt, buf);
1110 		break;
1111 	case MTK_THERMAL_V2:
1112 		ret = mtk_thermal_extract_efuse_v2(mt, buf);
1113 		break;
1114 	case MTK_THERMAL_V3:
1115 		ret = mtk_thermal_extract_efuse_v3(mt, buf);
1116 		break;
1117 	default:
1118 		ret = -EINVAL;
1119 		break;
1120 	}
1121 
1122 	if (ret) {
1123 		dev_info(dev, "Device not calibrated, using default calibration values\n");
1124 		ret = 0;
1125 	}
1126 
1127 out:
1128 	kfree(buf);
1129 
1130 	return ret;
1131 }
1132 
1133 static const struct of_device_id mtk_thermal_of_match[] = {
1134 	{
1135 		.compatible = "mediatek,mt8173-thermal",
1136 		.data = (void *)&mt8173_thermal_data,
1137 	},
1138 	{
1139 		.compatible = "mediatek,mt2701-thermal",
1140 		.data = (void *)&mt2701_thermal_data,
1141 	},
1142 	{
1143 		.compatible = "mediatek,mt2712-thermal",
1144 		.data = (void *)&mt2712_thermal_data,
1145 	},
1146 	{
1147 		.compatible = "mediatek,mt7622-thermal",
1148 		.data = (void *)&mt7622_thermal_data,
1149 	},
1150 	{
1151 		.compatible = "mediatek,mt7986-thermal",
1152 		.data = (void *)&mt7986_thermal_data,
1153 	},
1154 	{
1155 		.compatible = "mediatek,mt8183-thermal",
1156 		.data = (void *)&mt8183_thermal_data,
1157 	},
1158 	{
1159 		.compatible = "mediatek,mt8365-thermal",
1160 		.data = (void *)&mt8365_thermal_data,
1161 	}, {
1162 	},
1163 };
1164 MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
1165 
1166 static void mtk_thermal_turn_on_buffer(struct mtk_thermal *mt,
1167 				       void __iomem *apmixed_base)
1168 {
1169 	u32 tmp;
1170 
1171 	if (!mt->conf->apmixed_buffer_ctl_reg)
1172 		return;
1173 
1174 	tmp = readl(apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
1175 	tmp &= mt->conf->apmixed_buffer_ctl_mask;
1176 	tmp |= mt->conf->apmixed_buffer_ctl_set;
1177 	writel(tmp, apmixed_base + mt->conf->apmixed_buffer_ctl_reg);
1178 	udelay(200);
1179 }
1180 
1181 static void mtk_thermal_release_periodic_ts(struct mtk_thermal *mt,
1182 					    void __iomem *auxadc_base)
1183 {
1184 	int tmp;
1185 
1186 	writel(0x800, auxadc_base + AUXADC_CON1_SET_V);
1187 	writel(0x1, mt->thermal_base + TEMP_MONCTL0);
1188 	tmp = readl(mt->thermal_base + TEMP_MSRCTL1);
1189 	writel((tmp & (~0x10e)), mt->thermal_base + TEMP_MSRCTL1);
1190 }
1191 
1192 static int mtk_thermal_probe(struct platform_device *pdev)
1193 {
1194 	int ret, i, ctrl_id;
1195 	struct device_node *auxadc, *apmixedsys, *np = pdev->dev.of_node;
1196 	struct mtk_thermal *mt;
1197 	u64 auxadc_phys_base, apmixed_phys_base;
1198 	struct thermal_zone_device *tzdev;
1199 	void __iomem *apmixed_base, *auxadc_base;
1200 
1201 	mt = devm_kzalloc(&pdev->dev, sizeof(*mt), GFP_KERNEL);
1202 	if (!mt)
1203 		return -ENOMEM;
1204 
1205 	mt->conf = of_device_get_match_data(&pdev->dev);
1206 
1207 	mt->thermal_base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
1208 	if (IS_ERR(mt->thermal_base))
1209 		return PTR_ERR(mt->thermal_base);
1210 
1211 	ret = mtk_thermal_get_calibration_data(&pdev->dev, mt);
1212 	if (ret)
1213 		return ret;
1214 
1215 	mutex_init(&mt->lock);
1216 
1217 	mt->dev = &pdev->dev;
1218 
1219 	auxadc = of_parse_phandle(np, "mediatek,auxadc", 0);
1220 	if (!auxadc) {
1221 		dev_err(&pdev->dev, "missing auxadc node\n");
1222 		return -ENODEV;
1223 	}
1224 
1225 	auxadc_base = of_iomap(auxadc, 0);
1226 	auxadc_phys_base = of_get_phys_base(auxadc);
1227 
1228 	of_node_put(auxadc);
1229 
1230 	if (auxadc_phys_base == OF_BAD_ADDR) {
1231 		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
1232 		return -EINVAL;
1233 	}
1234 
1235 	apmixedsys = of_parse_phandle(np, "mediatek,apmixedsys", 0);
1236 	if (!apmixedsys) {
1237 		dev_err(&pdev->dev, "missing apmixedsys node\n");
1238 		return -ENODEV;
1239 	}
1240 
1241 	apmixed_base = of_iomap(apmixedsys, 0);
1242 	apmixed_phys_base = of_get_phys_base(apmixedsys);
1243 
1244 	of_node_put(apmixedsys);
1245 
1246 	if (apmixed_phys_base == OF_BAD_ADDR) {
1247 		dev_err(&pdev->dev, "Can't get auxadc phys address\n");
1248 		return -EINVAL;
1249 	}
1250 
1251 	ret = device_reset_optional(&pdev->dev);
1252 	if (ret)
1253 		return ret;
1254 
1255 	mt->clk_auxadc = devm_clk_get_enabled(&pdev->dev, "auxadc");
1256 	if (IS_ERR(mt->clk_auxadc)) {
1257 		ret = PTR_ERR(mt->clk_auxadc);
1258 		dev_err(&pdev->dev, "Can't enable auxadc clk: %d\n", ret);
1259 		return ret;
1260 	}
1261 
1262 	mt->clk_peri_therm = devm_clk_get_enabled(&pdev->dev, "therm");
1263 	if (IS_ERR(mt->clk_peri_therm)) {
1264 		ret = PTR_ERR(mt->clk_peri_therm);
1265 		dev_err(&pdev->dev, "Can't enable peri clk: %d\n", ret);
1266 		return ret;
1267 	}
1268 
1269 	mtk_thermal_turn_on_buffer(mt, apmixed_base);
1270 
1271 	if (mt->conf->version != MTK_THERMAL_V2)
1272 		mtk_thermal_release_periodic_ts(mt, auxadc_base);
1273 
1274 	if (mt->conf->version == MTK_THERMAL_V1)
1275 		mt->raw_to_mcelsius = raw_to_mcelsius_v1;
1276 	else if (mt->conf->version == MTK_THERMAL_V2)
1277 		mt->raw_to_mcelsius = raw_to_mcelsius_v2;
1278 	else
1279 		mt->raw_to_mcelsius = raw_to_mcelsius_v3;
1280 
1281 	for (ctrl_id = 0; ctrl_id < mt->conf->num_controller ; ctrl_id++)
1282 		for (i = 0; i < mt->conf->num_banks; i++)
1283 			mtk_thermal_init_bank(mt, i, apmixed_phys_base,
1284 					      auxadc_phys_base, ctrl_id);
1285 
1286 	platform_set_drvdata(pdev, mt);
1287 
1288 	tzdev = devm_thermal_of_zone_register(&pdev->dev, 0, mt,
1289 					      &mtk_thermal_ops);
1290 	if (IS_ERR(tzdev))
1291 		return PTR_ERR(tzdev);
1292 
1293 	ret = devm_thermal_add_hwmon_sysfs(&pdev->dev, tzdev);
1294 	if (ret)
1295 		dev_warn(&pdev->dev, "error in thermal_add_hwmon_sysfs");
1296 
1297 	return 0;
1298 }
1299 
1300 static struct platform_driver mtk_thermal_driver = {
1301 	.probe = mtk_thermal_probe,
1302 	.driver = {
1303 		.name = "mtk-thermal",
1304 		.of_match_table = mtk_thermal_of_match,
1305 	},
1306 };
1307 
1308 module_platform_driver(mtk_thermal_driver);
1309 
1310 MODULE_AUTHOR("Michael Kao <michael.kao@mediatek.com>");
1311 MODULE_AUTHOR("Louis Yu <louis.yu@mediatek.com>");
1312 MODULE_AUTHOR("Dawei Chien <dawei.chien@mediatek.com>");
1313 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1314 MODULE_AUTHOR("Hanyi Wu <hanyi.wu@mediatek.com>");
1315 MODULE_DESCRIPTION("Mediatek thermal driver");
1316 MODULE_LICENSE("GPL v2");
1317