1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Thermal throttle event support code (such as syslog messaging and rate 4 * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c). 5 * 6 * This allows consistent reporting of CPU thermal throttle events. 7 * 8 * Maintains a counter in /sys that keeps track of the number of thermal 9 * events, such that the user knows how bad the thermal problem might be 10 * (since the logging to syslog is rate limited). 11 * 12 * Author: Dmitriy Zavin (dmitriyz@google.com) 13 * 14 * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c. 15 * Inspired by Ross Biro's and Al Borchers' counter code. 16 */ 17 #include <linux/interrupt.h> 18 #include <linux/notifier.h> 19 #include <linux/jiffies.h> 20 #include <linux/kernel.h> 21 #include <linux/percpu.h> 22 #include <linux/export.h> 23 #include <linux/types.h> 24 #include <linux/init.h> 25 #include <linux/smp.h> 26 #include <linux/cpu.h> 27 28 #include <asm/processor.h> 29 #include <asm/thermal.h> 30 #include <asm/traps.h> 31 #include <asm/apic.h> 32 #include <asm/irq.h> 33 #include <asm/msr.h> 34 35 #include "intel_hfi.h" 36 #include "thermal_interrupt.h" 37 38 /* How long to wait between reporting thermal events */ 39 #define CHECK_INTERVAL (300 * HZ) 40 41 #define THERMAL_THROTTLING_EVENT 0 42 #define POWER_LIMIT_EVENT 1 43 44 /** 45 * struct _thermal_state - Represent the current thermal event state 46 * @next_check: Stores the next timestamp, when it is allowed 47 * to log the next warning message. 48 * @last_interrupt_time: Stores the timestamp for the last threshold 49 * high event. 50 * @therm_work: Delayed workqueue structure 51 * @count: Stores the current running count for thermal 52 * or power threshold interrupts. 53 * @last_count: Stores the previous running count for thermal 54 * or power threshold interrupts. 55 * @max_time_ms: This shows the maximum amount of time CPU was 56 * in throttled state for a single thermal 57 * threshold high to low state. 58 * @total_time_ms: This is a cumulative time during which CPU was 59 * in the throttled state. 60 * @rate_control_active: Set when a throttling message is logged. 61 * This is used for the purpose of rate-control. 62 * @new_event: Stores the last high/low status of the 63 * THERM_STATUS_PROCHOT or 64 * THERM_STATUS_POWER_LIMIT. 65 * @level: Stores whether this _thermal_state instance is 66 * for a CORE level or for PACKAGE level. 67 * @sample_index: Index for storing the next sample in the buffer 68 * temp_samples[]. 69 * @sample_count: Total number of samples collected in the buffer 70 * temp_samples[]. 71 * @average: The last moving average of temperature samples 72 * @baseline_temp: Temperature at which thermal threshold high 73 * interrupt was generated. 74 * @temp_samples: Storage for temperature samples to calculate 75 * moving average. 76 * 77 * This structure is used to represent data related to thermal state for a CPU. 78 * There is a separate storage for core and package level for each CPU. 79 */ 80 struct _thermal_state { 81 u64 next_check; 82 u64 last_interrupt_time; 83 struct delayed_work therm_work; 84 unsigned long count; 85 unsigned long last_count; 86 unsigned long max_time_ms; 87 unsigned long total_time_ms; 88 bool rate_control_active; 89 bool new_event; 90 u8 level; 91 u8 sample_index; 92 u8 sample_count; 93 u8 average; 94 u8 baseline_temp; 95 u8 temp_samples[3]; 96 }; 97 98 struct thermal_state { 99 struct _thermal_state core_throttle; 100 struct _thermal_state core_power_limit; 101 struct _thermal_state package_throttle; 102 struct _thermal_state package_power_limit; 103 struct _thermal_state core_thresh0; 104 struct _thermal_state core_thresh1; 105 struct _thermal_state pkg_thresh0; 106 struct _thermal_state pkg_thresh1; 107 }; 108 109 /* Callback to handle core threshold interrupts */ 110 int (*platform_thermal_notify)(__u64 msr_val); 111 EXPORT_SYMBOL(platform_thermal_notify); 112 113 /* Callback to handle core package threshold_interrupts */ 114 int (*platform_thermal_package_notify)(__u64 msr_val); 115 EXPORT_SYMBOL_GPL(platform_thermal_package_notify); 116 117 /* Callback support of rate control, return true, if 118 * callback has rate control */ 119 bool (*platform_thermal_package_rate_control)(void); 120 EXPORT_SYMBOL_GPL(platform_thermal_package_rate_control); 121 122 123 static DEFINE_PER_CPU(struct thermal_state, thermal_state); 124 125 static atomic_t therm_throt_en = ATOMIC_INIT(0); 126 127 static u32 lvtthmr_init __read_mostly; 128 129 #ifdef CONFIG_SYSFS 130 #define define_therm_throt_device_one_ro(_name) \ 131 static DEVICE_ATTR(_name, 0444, \ 132 therm_throt_device_show_##_name, \ 133 NULL) \ 134 135 #define define_therm_throt_device_show_func(event, name) \ 136 \ 137 static ssize_t therm_throt_device_show_##event##_##name( \ 138 struct device *dev, \ 139 struct device_attribute *attr, \ 140 char *buf) \ 141 { \ 142 unsigned int cpu = dev->id; \ 143 ssize_t ret; \ 144 \ 145 preempt_disable(); /* CPU hotplug */ \ 146 if (cpu_online(cpu)) { \ 147 ret = sprintf(buf, "%lu\n", \ 148 per_cpu(thermal_state, cpu).event.name); \ 149 } else \ 150 ret = 0; \ 151 preempt_enable(); \ 152 \ 153 return ret; \ 154 } 155 156 define_therm_throt_device_show_func(core_throttle, count); 157 define_therm_throt_device_one_ro(core_throttle_count); 158 159 define_therm_throt_device_show_func(core_power_limit, count); 160 define_therm_throt_device_one_ro(core_power_limit_count); 161 162 define_therm_throt_device_show_func(package_throttle, count); 163 define_therm_throt_device_one_ro(package_throttle_count); 164 165 define_therm_throt_device_show_func(package_power_limit, count); 166 define_therm_throt_device_one_ro(package_power_limit_count); 167 168 define_therm_throt_device_show_func(core_throttle, max_time_ms); 169 define_therm_throt_device_one_ro(core_throttle_max_time_ms); 170 171 define_therm_throt_device_show_func(package_throttle, max_time_ms); 172 define_therm_throt_device_one_ro(package_throttle_max_time_ms); 173 174 define_therm_throt_device_show_func(core_throttle, total_time_ms); 175 define_therm_throt_device_one_ro(core_throttle_total_time_ms); 176 177 define_therm_throt_device_show_func(package_throttle, total_time_ms); 178 define_therm_throt_device_one_ro(package_throttle_total_time_ms); 179 180 static struct attribute *thermal_throttle_attrs[] = { 181 &dev_attr_core_throttle_count.attr, 182 &dev_attr_core_throttle_max_time_ms.attr, 183 &dev_attr_core_throttle_total_time_ms.attr, 184 NULL 185 }; 186 187 static const struct attribute_group thermal_attr_group = { 188 .attrs = thermal_throttle_attrs, 189 .name = "thermal_throttle" 190 }; 191 #endif /* CONFIG_SYSFS */ 192 193 #define THERM_THROT_POLL_INTERVAL HZ 194 #define THERM_STATUS_PROCHOT_LOG BIT(1) 195 196 #define THERM_STATUS_CLEAR_CORE_MASK (BIT(1) | BIT(3) | BIT(5) | BIT(7) | BIT(9) | BIT(11) | BIT(13) | BIT(15)) 197 #define THERM_STATUS_CLEAR_PKG_MASK (BIT(1) | BIT(3) | BIT(5) | BIT(7) | BIT(9) | BIT(11)) 198 199 /* 200 * Clear the bits in package thermal status register for bit = 1 201 * in bitmask 202 */ 203 void thermal_clear_package_intr_status(int level, u64 bit_mask) 204 { 205 u64 msr_val; 206 int msr; 207 208 if (level == CORE_LEVEL) { 209 msr = MSR_IA32_THERM_STATUS; 210 msr_val = THERM_STATUS_CLEAR_CORE_MASK; 211 } else { 212 msr = MSR_IA32_PACKAGE_THERM_STATUS; 213 msr_val = THERM_STATUS_CLEAR_PKG_MASK; 214 if (boot_cpu_has(X86_FEATURE_HFI)) 215 msr_val |= BIT(26); 216 217 } 218 219 msr_val &= ~bit_mask; 220 wrmsrl(msr, msr_val); 221 } 222 EXPORT_SYMBOL_GPL(thermal_clear_package_intr_status); 223 224 static void get_therm_status(int level, bool *proc_hot, u8 *temp) 225 { 226 int msr; 227 u64 msr_val; 228 229 if (level == CORE_LEVEL) 230 msr = MSR_IA32_THERM_STATUS; 231 else 232 msr = MSR_IA32_PACKAGE_THERM_STATUS; 233 234 rdmsrl(msr, msr_val); 235 if (msr_val & THERM_STATUS_PROCHOT_LOG) 236 *proc_hot = true; 237 else 238 *proc_hot = false; 239 240 *temp = (msr_val >> 16) & 0x7F; 241 } 242 243 static void __maybe_unused throttle_active_work(struct work_struct *work) 244 { 245 struct _thermal_state *state = container_of(to_delayed_work(work), 246 struct _thermal_state, therm_work); 247 unsigned int i, avg, this_cpu = smp_processor_id(); 248 u64 now = get_jiffies_64(); 249 bool hot; 250 u8 temp; 251 252 get_therm_status(state->level, &hot, &temp); 253 /* temperature value is offset from the max so lesser means hotter */ 254 if (!hot && temp > state->baseline_temp) { 255 if (state->rate_control_active) 256 pr_info("CPU%d: %s temperature/speed normal (total events = %lu)\n", 257 this_cpu, 258 state->level == CORE_LEVEL ? "Core" : "Package", 259 state->count); 260 261 state->rate_control_active = false; 262 return; 263 } 264 265 if (time_before64(now, state->next_check) && 266 state->rate_control_active) 267 goto re_arm; 268 269 state->next_check = now + CHECK_INTERVAL; 270 271 if (state->count != state->last_count) { 272 /* There was one new thermal interrupt */ 273 state->last_count = state->count; 274 state->average = 0; 275 state->sample_count = 0; 276 state->sample_index = 0; 277 } 278 279 state->temp_samples[state->sample_index] = temp; 280 state->sample_count++; 281 state->sample_index = (state->sample_index + 1) % ARRAY_SIZE(state->temp_samples); 282 if (state->sample_count < ARRAY_SIZE(state->temp_samples)) 283 goto re_arm; 284 285 avg = 0; 286 for (i = 0; i < ARRAY_SIZE(state->temp_samples); ++i) 287 avg += state->temp_samples[i]; 288 289 avg /= ARRAY_SIZE(state->temp_samples); 290 291 if (state->average > avg) { 292 pr_warn("CPU%d: %s temperature is above threshold, cpu clock is throttled (total events = %lu)\n", 293 this_cpu, 294 state->level == CORE_LEVEL ? "Core" : "Package", 295 state->count); 296 state->rate_control_active = true; 297 } 298 299 state->average = avg; 300 301 re_arm: 302 thermal_clear_package_intr_status(state->level, THERM_STATUS_PROCHOT_LOG); 303 schedule_delayed_work_on(this_cpu, &state->therm_work, THERM_THROT_POLL_INTERVAL); 304 } 305 306 /*** 307 * therm_throt_process - Process thermal throttling event from interrupt 308 * @curr: Whether the condition is current or not (boolean), since the 309 * thermal interrupt normally gets called both when the thermal 310 * event begins and once the event has ended. 311 * 312 * This function is called by the thermal interrupt after the 313 * IRQ has been acknowledged. 314 * 315 * It will take care of rate limiting and printing messages to the syslog. 316 */ 317 static void therm_throt_process(bool new_event, int event, int level) 318 { 319 struct _thermal_state *state; 320 unsigned int this_cpu = smp_processor_id(); 321 bool old_event; 322 u64 now; 323 struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); 324 325 now = get_jiffies_64(); 326 if (level == CORE_LEVEL) { 327 if (event == THERMAL_THROTTLING_EVENT) 328 state = &pstate->core_throttle; 329 else if (event == POWER_LIMIT_EVENT) 330 state = &pstate->core_power_limit; 331 else 332 return; 333 } else if (level == PACKAGE_LEVEL) { 334 if (event == THERMAL_THROTTLING_EVENT) 335 state = &pstate->package_throttle; 336 else if (event == POWER_LIMIT_EVENT) 337 state = &pstate->package_power_limit; 338 else 339 return; 340 } else 341 return; 342 343 old_event = state->new_event; 344 state->new_event = new_event; 345 346 if (new_event) 347 state->count++; 348 349 if (event != THERMAL_THROTTLING_EVENT) 350 return; 351 352 if (new_event && !state->last_interrupt_time) { 353 bool hot; 354 u8 temp; 355 356 get_therm_status(state->level, &hot, &temp); 357 /* 358 * Ignore short temperature spike as the system is not close 359 * to PROCHOT. 10C offset is large enough to ignore. It is 360 * already dropped from the high threshold temperature. 361 */ 362 if (temp > 10) 363 return; 364 365 state->baseline_temp = temp; 366 state->last_interrupt_time = now; 367 schedule_delayed_work_on(this_cpu, &state->therm_work, THERM_THROT_POLL_INTERVAL); 368 } else if (old_event && state->last_interrupt_time) { 369 unsigned long throttle_time; 370 371 throttle_time = jiffies_delta_to_msecs(now - state->last_interrupt_time); 372 if (throttle_time > state->max_time_ms) 373 state->max_time_ms = throttle_time; 374 state->total_time_ms += throttle_time; 375 state->last_interrupt_time = 0; 376 } 377 } 378 379 static int thresh_event_valid(int level, int event) 380 { 381 struct _thermal_state *state; 382 unsigned int this_cpu = smp_processor_id(); 383 struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); 384 u64 now = get_jiffies_64(); 385 386 if (level == PACKAGE_LEVEL) 387 state = (event == 0) ? &pstate->pkg_thresh0 : 388 &pstate->pkg_thresh1; 389 else 390 state = (event == 0) ? &pstate->core_thresh0 : 391 &pstate->core_thresh1; 392 393 if (time_before64(now, state->next_check)) 394 return 0; 395 396 state->next_check = now + CHECK_INTERVAL; 397 398 return 1; 399 } 400 401 static bool int_pln_enable; 402 static int __init int_pln_enable_setup(char *s) 403 { 404 int_pln_enable = true; 405 406 return 1; 407 } 408 __setup("int_pln_enable", int_pln_enable_setup); 409 410 #ifdef CONFIG_SYSFS 411 /* Add/Remove thermal_throttle interface for CPU device: */ 412 static int thermal_throttle_add_dev(struct device *dev, unsigned int cpu) 413 { 414 int err; 415 struct cpuinfo_x86 *c = &cpu_data(cpu); 416 417 err = sysfs_create_group(&dev->kobj, &thermal_attr_group); 418 if (err) 419 return err; 420 421 if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) { 422 err = sysfs_add_file_to_group(&dev->kobj, 423 &dev_attr_core_power_limit_count.attr, 424 thermal_attr_group.name); 425 if (err) 426 goto del_group; 427 } 428 429 if (cpu_has(c, X86_FEATURE_PTS)) { 430 err = sysfs_add_file_to_group(&dev->kobj, 431 &dev_attr_package_throttle_count.attr, 432 thermal_attr_group.name); 433 if (err) 434 goto del_group; 435 436 err = sysfs_add_file_to_group(&dev->kobj, 437 &dev_attr_package_throttle_max_time_ms.attr, 438 thermal_attr_group.name); 439 if (err) 440 goto del_group; 441 442 err = sysfs_add_file_to_group(&dev->kobj, 443 &dev_attr_package_throttle_total_time_ms.attr, 444 thermal_attr_group.name); 445 if (err) 446 goto del_group; 447 448 if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) { 449 err = sysfs_add_file_to_group(&dev->kobj, 450 &dev_attr_package_power_limit_count.attr, 451 thermal_attr_group.name); 452 if (err) 453 goto del_group; 454 } 455 } 456 457 return 0; 458 459 del_group: 460 sysfs_remove_group(&dev->kobj, &thermal_attr_group); 461 462 return err; 463 } 464 465 static void thermal_throttle_remove_dev(struct device *dev) 466 { 467 sysfs_remove_group(&dev->kobj, &thermal_attr_group); 468 } 469 470 /* Get notified when a cpu comes on/off. Be hotplug friendly. */ 471 static int thermal_throttle_online(unsigned int cpu) 472 { 473 struct thermal_state *state = &per_cpu(thermal_state, cpu); 474 struct device *dev = get_cpu_device(cpu); 475 u32 l; 476 477 state->package_throttle.level = PACKAGE_LEVEL; 478 state->core_throttle.level = CORE_LEVEL; 479 480 INIT_DELAYED_WORK(&state->package_throttle.therm_work, throttle_active_work); 481 INIT_DELAYED_WORK(&state->core_throttle.therm_work, throttle_active_work); 482 483 /* 484 * The first CPU coming online will enable the HFI. Usually this causes 485 * hardware to issue an HFI thermal interrupt. Such interrupt will reach 486 * the CPU once we enable the thermal vector in the local APIC. 487 */ 488 intel_hfi_online(cpu); 489 490 /* Unmask the thermal vector after the above workqueues are initialized. */ 491 l = apic_read(APIC_LVTTHMR); 492 apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED); 493 494 return thermal_throttle_add_dev(dev, cpu); 495 } 496 497 static int thermal_throttle_offline(unsigned int cpu) 498 { 499 struct thermal_state *state = &per_cpu(thermal_state, cpu); 500 struct device *dev = get_cpu_device(cpu); 501 u32 l; 502 503 /* Mask the thermal vector before draining evtl. pending work */ 504 l = apic_read(APIC_LVTTHMR); 505 apic_write(APIC_LVTTHMR, l | APIC_LVT_MASKED); 506 507 intel_hfi_offline(cpu); 508 509 cancel_delayed_work_sync(&state->package_throttle.therm_work); 510 cancel_delayed_work_sync(&state->core_throttle.therm_work); 511 512 state->package_throttle.rate_control_active = false; 513 state->core_throttle.rate_control_active = false; 514 515 thermal_throttle_remove_dev(dev); 516 return 0; 517 } 518 519 static __init int thermal_throttle_init_device(void) 520 { 521 int ret; 522 523 if (!atomic_read(&therm_throt_en)) 524 return 0; 525 526 intel_hfi_init(); 527 528 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/therm:online", 529 thermal_throttle_online, 530 thermal_throttle_offline); 531 return ret < 0 ? ret : 0; 532 } 533 device_initcall(thermal_throttle_init_device); 534 535 #endif /* CONFIG_SYSFS */ 536 537 static void notify_package_thresholds(__u64 msr_val) 538 { 539 bool notify_thres_0 = false; 540 bool notify_thres_1 = false; 541 542 if (!platform_thermal_package_notify) 543 return; 544 545 /* lower threshold check */ 546 if (msr_val & THERM_LOG_THRESHOLD0) 547 notify_thres_0 = true; 548 /* higher threshold check */ 549 if (msr_val & THERM_LOG_THRESHOLD1) 550 notify_thres_1 = true; 551 552 if (!notify_thres_0 && !notify_thres_1) 553 return; 554 555 if (platform_thermal_package_rate_control && 556 platform_thermal_package_rate_control()) { 557 /* Rate control is implemented in callback */ 558 platform_thermal_package_notify(msr_val); 559 return; 560 } 561 562 /* lower threshold reached */ 563 if (notify_thres_0 && thresh_event_valid(PACKAGE_LEVEL, 0)) 564 platform_thermal_package_notify(msr_val); 565 /* higher threshold reached */ 566 if (notify_thres_1 && thresh_event_valid(PACKAGE_LEVEL, 1)) 567 platform_thermal_package_notify(msr_val); 568 } 569 570 static void notify_thresholds(__u64 msr_val) 571 { 572 /* check whether the interrupt handler is defined; 573 * otherwise simply return 574 */ 575 if (!platform_thermal_notify) 576 return; 577 578 /* lower threshold reached */ 579 if ((msr_val & THERM_LOG_THRESHOLD0) && 580 thresh_event_valid(CORE_LEVEL, 0)) 581 platform_thermal_notify(msr_val); 582 /* higher threshold reached */ 583 if ((msr_val & THERM_LOG_THRESHOLD1) && 584 thresh_event_valid(CORE_LEVEL, 1)) 585 platform_thermal_notify(msr_val); 586 } 587 588 void __weak notify_hwp_interrupt(void) 589 { 590 wrmsrl_safe(MSR_HWP_STATUS, 0); 591 } 592 593 /* Thermal transition interrupt handler */ 594 void intel_thermal_interrupt(void) 595 { 596 __u64 msr_val; 597 598 if (static_cpu_has(X86_FEATURE_HWP)) 599 notify_hwp_interrupt(); 600 601 rdmsrl(MSR_IA32_THERM_STATUS, msr_val); 602 603 /* Check for violation of core thermal thresholds*/ 604 notify_thresholds(msr_val); 605 606 therm_throt_process(msr_val & THERM_STATUS_PROCHOT, 607 THERMAL_THROTTLING_EVENT, 608 CORE_LEVEL); 609 610 if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable) 611 therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT, 612 POWER_LIMIT_EVENT, 613 CORE_LEVEL); 614 615 if (this_cpu_has(X86_FEATURE_PTS)) { 616 rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val); 617 /* check violations of package thermal thresholds */ 618 notify_package_thresholds(msr_val); 619 therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT, 620 THERMAL_THROTTLING_EVENT, 621 PACKAGE_LEVEL); 622 if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable) 623 therm_throt_process(msr_val & 624 PACKAGE_THERM_STATUS_POWER_LIMIT, 625 POWER_LIMIT_EVENT, 626 PACKAGE_LEVEL); 627 628 if (this_cpu_has(X86_FEATURE_HFI)) 629 intel_hfi_process_event(msr_val & 630 PACKAGE_THERM_STATUS_HFI_UPDATED); 631 } 632 } 633 634 /* Thermal monitoring depends on APIC, ACPI and clock modulation */ 635 static int intel_thermal_supported(struct cpuinfo_x86 *c) 636 { 637 if (!boot_cpu_has(X86_FEATURE_APIC)) 638 return 0; 639 if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC)) 640 return 0; 641 return 1; 642 } 643 644 bool x86_thermal_enabled(void) 645 { 646 return atomic_read(&therm_throt_en); 647 } 648 649 void __init therm_lvt_init(void) 650 { 651 /* 652 * This function is only called on boot CPU. Save the init thermal 653 * LVT value on BSP and use that value to restore APs' thermal LVT 654 * entry BIOS programmed later 655 */ 656 if (intel_thermal_supported(&boot_cpu_data)) 657 lvtthmr_init = apic_read(APIC_LVTTHMR); 658 } 659 660 void intel_init_thermal(struct cpuinfo_x86 *c) 661 { 662 unsigned int cpu = smp_processor_id(); 663 int tm2 = 0; 664 u32 l, h; 665 666 if (!intel_thermal_supported(c)) 667 return; 668 669 /* 670 * First check if its enabled already, in which case there might 671 * be some SMM goo which handles it, so we can't even put a handler 672 * since it might be delivered via SMI already: 673 */ 674 rdmsr(MSR_IA32_MISC_ENABLE, l, h); 675 676 h = lvtthmr_init; 677 /* 678 * The initial value of thermal LVT entries on all APs always reads 679 * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI 680 * sequence to them and LVT registers are reset to 0s except for 681 * the mask bits which are set to 1s when APs receive INIT IPI. 682 * If BIOS takes over the thermal interrupt and sets its interrupt 683 * delivery mode to SMI (not fixed), it restores the value that the 684 * BIOS has programmed on AP based on BSP's info we saved since BIOS 685 * is always setting the same value for all threads/cores. 686 */ 687 if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED) 688 apic_write(APIC_LVTTHMR, lvtthmr_init); 689 690 691 if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) { 692 if (system_state == SYSTEM_BOOTING) 693 pr_debug("CPU%d: Thermal monitoring handled by SMI\n", cpu); 694 return; 695 } 696 697 /* early Pentium M models use different method for enabling TM2 */ 698 if (cpu_has(c, X86_FEATURE_TM2)) { 699 if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) { 700 rdmsr(MSR_THERM2_CTL, l, h); 701 if (l & MSR_THERM2_CTL_TM_SELECT) 702 tm2 = 1; 703 } else if (l & MSR_IA32_MISC_ENABLE_TM2) 704 tm2 = 1; 705 } 706 707 /* We'll mask the thermal vector in the lapic till we're ready: */ 708 h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED; 709 apic_write(APIC_LVTTHMR, h); 710 711 rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); 712 if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable) 713 wrmsr(MSR_IA32_THERM_INTERRUPT, 714 (l | (THERM_INT_LOW_ENABLE 715 | THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h); 716 else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) 717 wrmsr(MSR_IA32_THERM_INTERRUPT, 718 l | (THERM_INT_LOW_ENABLE 719 | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h); 720 else 721 wrmsr(MSR_IA32_THERM_INTERRUPT, 722 l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h); 723 724 if (cpu_has(c, X86_FEATURE_PTS)) { 725 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); 726 if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable) 727 wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, 728 (l | (PACKAGE_THERM_INT_LOW_ENABLE 729 | PACKAGE_THERM_INT_HIGH_ENABLE)) 730 & ~PACKAGE_THERM_INT_PLN_ENABLE, h); 731 else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) 732 wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, 733 l | (PACKAGE_THERM_INT_LOW_ENABLE 734 | PACKAGE_THERM_INT_HIGH_ENABLE 735 | PACKAGE_THERM_INT_PLN_ENABLE), h); 736 else 737 wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, 738 l | (PACKAGE_THERM_INT_LOW_ENABLE 739 | PACKAGE_THERM_INT_HIGH_ENABLE), h); 740 741 if (cpu_has(c, X86_FEATURE_HFI)) { 742 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); 743 wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, 744 l | PACKAGE_THERM_INT_HFI_ENABLE, h); 745 } 746 } 747 748 rdmsr(MSR_IA32_MISC_ENABLE, l, h); 749 wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h); 750 751 pr_info_once("CPU0: Thermal monitoring enabled (%s)\n", 752 tm2 ? "TM2" : "TM1"); 753 754 /* enable thermal throttle processing */ 755 atomic_set(&therm_throt_en, 1); 756 } 757