1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Thermal throttle event support code (such as syslog messaging and rate 4 * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c). 5 * 6 * This allows consistent reporting of CPU thermal throttle events. 7 * 8 * Maintains a counter in /sys that keeps track of the number of thermal 9 * events, such that the user knows how bad the thermal problem might be 10 * (since the logging to syslog is rate limited). 11 * 12 * Author: Dmitriy Zavin (dmitriyz@google.com) 13 * 14 * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c. 15 * Inspired by Ross Biro's and Al Borchers' counter code. 16 */ 17 #include <linux/interrupt.h> 18 #include <linux/notifier.h> 19 #include <linux/jiffies.h> 20 #include <linux/kernel.h> 21 #include <linux/percpu.h> 22 #include <linux/export.h> 23 #include <linux/types.h> 24 #include <linux/init.h> 25 #include <linux/smp.h> 26 #include <linux/cpu.h> 27 28 #include <asm/processor.h> 29 #include <asm/thermal.h> 30 #include <asm/traps.h> 31 #include <asm/apic.h> 32 #include <asm/irq.h> 33 #include <asm/msr.h> 34 35 #include "intel_hfi.h" 36 #include "thermal_interrupt.h" 37 38 /* How long to wait between reporting thermal events */ 39 #define CHECK_INTERVAL (300 * HZ) 40 41 #define THERMAL_THROTTLING_EVENT 0 42 #define POWER_LIMIT_EVENT 1 43 44 /** 45 * struct _thermal_state - Represent the current thermal event state 46 * @next_check: Stores the next timestamp, when it is allowed 47 * to log the next warning message. 48 * @last_interrupt_time: Stores the timestamp for the last threshold 49 * high event. 50 * @therm_work: Delayed workqueue structure 51 * @count: Stores the current running count for thermal 52 * or power threshold interrupts. 53 * @last_count: Stores the previous running count for thermal 54 * or power threshold interrupts. 55 * @max_time_ms: This shows the maximum amount of time CPU was 56 * in throttled state for a single thermal 57 * threshold high to low state. 58 * @total_time_ms: This is a cumulative time during which CPU was 59 * in the throttled state. 60 * @rate_control_active: Set when a throttling message is logged. 61 * This is used for the purpose of rate-control. 62 * @new_event: Stores the last high/low status of the 63 * THERM_STATUS_PROCHOT or 64 * THERM_STATUS_POWER_LIMIT. 65 * @level: Stores whether this _thermal_state instance is 66 * for a CORE level or for PACKAGE level. 67 * @sample_index: Index for storing the next sample in the buffer 68 * temp_samples[]. 69 * @sample_count: Total number of samples collected in the buffer 70 * temp_samples[]. 71 * @average: The last moving average of temperature samples 72 * @baseline_temp: Temperature at which thermal threshold high 73 * interrupt was generated. 74 * @temp_samples: Storage for temperature samples to calculate 75 * moving average. 76 * 77 * This structure is used to represent data related to thermal state for a CPU. 78 * There is a separate storage for core and package level for each CPU. 79 */ 80 struct _thermal_state { 81 u64 next_check; 82 u64 last_interrupt_time; 83 struct delayed_work therm_work; 84 unsigned long count; 85 unsigned long last_count; 86 unsigned long max_time_ms; 87 unsigned long total_time_ms; 88 bool rate_control_active; 89 bool new_event; 90 u8 level; 91 u8 sample_index; 92 u8 sample_count; 93 u8 average; 94 u8 baseline_temp; 95 u8 temp_samples[3]; 96 }; 97 98 struct thermal_state { 99 struct _thermal_state core_throttle; 100 struct _thermal_state core_power_limit; 101 struct _thermal_state package_throttle; 102 struct _thermal_state package_power_limit; 103 struct _thermal_state core_thresh0; 104 struct _thermal_state core_thresh1; 105 struct _thermal_state pkg_thresh0; 106 struct _thermal_state pkg_thresh1; 107 }; 108 109 /* Callback to handle core threshold interrupts */ 110 int (*platform_thermal_notify)(__u64 msr_val); 111 EXPORT_SYMBOL(platform_thermal_notify); 112 113 /* Callback to handle core package threshold_interrupts */ 114 int (*platform_thermal_package_notify)(__u64 msr_val); 115 EXPORT_SYMBOL_GPL(platform_thermal_package_notify); 116 117 /* Callback support of rate control, return true, if 118 * callback has rate control */ 119 bool (*platform_thermal_package_rate_control)(void); 120 EXPORT_SYMBOL_GPL(platform_thermal_package_rate_control); 121 122 123 static DEFINE_PER_CPU(struct thermal_state, thermal_state); 124 125 static atomic_t therm_throt_en = ATOMIC_INIT(0); 126 127 static u32 lvtthmr_init __read_mostly; 128 129 #ifdef CONFIG_SYSFS 130 #define define_therm_throt_device_one_ro(_name) \ 131 static DEVICE_ATTR(_name, 0444, \ 132 therm_throt_device_show_##_name, \ 133 NULL) \ 134 135 #define define_therm_throt_device_show_func(event, name) \ 136 \ 137 static ssize_t therm_throt_device_show_##event##_##name( \ 138 struct device *dev, \ 139 struct device_attribute *attr, \ 140 char *buf) \ 141 { \ 142 unsigned int cpu = dev->id; \ 143 ssize_t ret; \ 144 \ 145 preempt_disable(); /* CPU hotplug */ \ 146 if (cpu_online(cpu)) { \ 147 ret = sprintf(buf, "%lu\n", \ 148 per_cpu(thermal_state, cpu).event.name); \ 149 } else \ 150 ret = 0; \ 151 preempt_enable(); \ 152 \ 153 return ret; \ 154 } 155 156 define_therm_throt_device_show_func(core_throttle, count); 157 define_therm_throt_device_one_ro(core_throttle_count); 158 159 define_therm_throt_device_show_func(core_power_limit, count); 160 define_therm_throt_device_one_ro(core_power_limit_count); 161 162 define_therm_throt_device_show_func(package_throttle, count); 163 define_therm_throt_device_one_ro(package_throttle_count); 164 165 define_therm_throt_device_show_func(package_power_limit, count); 166 define_therm_throt_device_one_ro(package_power_limit_count); 167 168 define_therm_throt_device_show_func(core_throttle, max_time_ms); 169 define_therm_throt_device_one_ro(core_throttle_max_time_ms); 170 171 define_therm_throt_device_show_func(package_throttle, max_time_ms); 172 define_therm_throt_device_one_ro(package_throttle_max_time_ms); 173 174 define_therm_throt_device_show_func(core_throttle, total_time_ms); 175 define_therm_throt_device_one_ro(core_throttle_total_time_ms); 176 177 define_therm_throt_device_show_func(package_throttle, total_time_ms); 178 define_therm_throt_device_one_ro(package_throttle_total_time_ms); 179 180 static struct attribute *thermal_throttle_attrs[] = { 181 &dev_attr_core_throttle_count.attr, 182 &dev_attr_core_throttle_max_time_ms.attr, 183 &dev_attr_core_throttle_total_time_ms.attr, 184 NULL 185 }; 186 187 static const struct attribute_group thermal_attr_group = { 188 .attrs = thermal_throttle_attrs, 189 .name = "thermal_throttle" 190 }; 191 #endif /* CONFIG_SYSFS */ 192 193 #define THERM_THROT_POLL_INTERVAL HZ 194 #define THERM_STATUS_PROCHOT_LOG BIT(1) 195 196 #define THERM_STATUS_CLEAR_CORE_MASK (BIT(1) | BIT(3) | BIT(5) | BIT(7) | BIT(9) | BIT(11) | BIT(13) | BIT(15)) 197 #define THERM_STATUS_CLEAR_PKG_MASK (BIT(1) | BIT(3) | BIT(5) | BIT(7) | BIT(9) | BIT(11) | BIT(26)) 198 199 /* 200 * Clear the bits in package thermal status register for bit = 1 201 * in bitmask 202 */ 203 void thermal_clear_package_intr_status(int level, u64 bit_mask) 204 { 205 u64 msr_val; 206 int msr; 207 208 if (level == CORE_LEVEL) { 209 msr = MSR_IA32_THERM_STATUS; 210 msr_val = THERM_STATUS_CLEAR_CORE_MASK; 211 } else { 212 msr = MSR_IA32_PACKAGE_THERM_STATUS; 213 msr_val = THERM_STATUS_CLEAR_PKG_MASK; 214 } 215 216 msr_val &= ~bit_mask; 217 wrmsrl(msr, msr_val); 218 } 219 EXPORT_SYMBOL_GPL(thermal_clear_package_intr_status); 220 221 static void get_therm_status(int level, bool *proc_hot, u8 *temp) 222 { 223 int msr; 224 u64 msr_val; 225 226 if (level == CORE_LEVEL) 227 msr = MSR_IA32_THERM_STATUS; 228 else 229 msr = MSR_IA32_PACKAGE_THERM_STATUS; 230 231 rdmsrl(msr, msr_val); 232 if (msr_val & THERM_STATUS_PROCHOT_LOG) 233 *proc_hot = true; 234 else 235 *proc_hot = false; 236 237 *temp = (msr_val >> 16) & 0x7F; 238 } 239 240 static void __maybe_unused throttle_active_work(struct work_struct *work) 241 { 242 struct _thermal_state *state = container_of(to_delayed_work(work), 243 struct _thermal_state, therm_work); 244 unsigned int i, avg, this_cpu = smp_processor_id(); 245 u64 now = get_jiffies_64(); 246 bool hot; 247 u8 temp; 248 249 get_therm_status(state->level, &hot, &temp); 250 /* temperature value is offset from the max so lesser means hotter */ 251 if (!hot && temp > state->baseline_temp) { 252 if (state->rate_control_active) 253 pr_info("CPU%d: %s temperature/speed normal (total events = %lu)\n", 254 this_cpu, 255 state->level == CORE_LEVEL ? "Core" : "Package", 256 state->count); 257 258 state->rate_control_active = false; 259 return; 260 } 261 262 if (time_before64(now, state->next_check) && 263 state->rate_control_active) 264 goto re_arm; 265 266 state->next_check = now + CHECK_INTERVAL; 267 268 if (state->count != state->last_count) { 269 /* There was one new thermal interrupt */ 270 state->last_count = state->count; 271 state->average = 0; 272 state->sample_count = 0; 273 state->sample_index = 0; 274 } 275 276 state->temp_samples[state->sample_index] = temp; 277 state->sample_count++; 278 state->sample_index = (state->sample_index + 1) % ARRAY_SIZE(state->temp_samples); 279 if (state->sample_count < ARRAY_SIZE(state->temp_samples)) 280 goto re_arm; 281 282 avg = 0; 283 for (i = 0; i < ARRAY_SIZE(state->temp_samples); ++i) 284 avg += state->temp_samples[i]; 285 286 avg /= ARRAY_SIZE(state->temp_samples); 287 288 if (state->average > avg) { 289 pr_warn("CPU%d: %s temperature is above threshold, cpu clock is throttled (total events = %lu)\n", 290 this_cpu, 291 state->level == CORE_LEVEL ? "Core" : "Package", 292 state->count); 293 state->rate_control_active = true; 294 } 295 296 state->average = avg; 297 298 re_arm: 299 thermal_clear_package_intr_status(state->level, THERM_STATUS_PROCHOT_LOG); 300 schedule_delayed_work_on(this_cpu, &state->therm_work, THERM_THROT_POLL_INTERVAL); 301 } 302 303 /*** 304 * therm_throt_process - Process thermal throttling event from interrupt 305 * @curr: Whether the condition is current or not (boolean), since the 306 * thermal interrupt normally gets called both when the thermal 307 * event begins and once the event has ended. 308 * 309 * This function is called by the thermal interrupt after the 310 * IRQ has been acknowledged. 311 * 312 * It will take care of rate limiting and printing messages to the syslog. 313 */ 314 static void therm_throt_process(bool new_event, int event, int level) 315 { 316 struct _thermal_state *state; 317 unsigned int this_cpu = smp_processor_id(); 318 bool old_event; 319 u64 now; 320 struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); 321 322 now = get_jiffies_64(); 323 if (level == CORE_LEVEL) { 324 if (event == THERMAL_THROTTLING_EVENT) 325 state = &pstate->core_throttle; 326 else if (event == POWER_LIMIT_EVENT) 327 state = &pstate->core_power_limit; 328 else 329 return; 330 } else if (level == PACKAGE_LEVEL) { 331 if (event == THERMAL_THROTTLING_EVENT) 332 state = &pstate->package_throttle; 333 else if (event == POWER_LIMIT_EVENT) 334 state = &pstate->package_power_limit; 335 else 336 return; 337 } else 338 return; 339 340 old_event = state->new_event; 341 state->new_event = new_event; 342 343 if (new_event) 344 state->count++; 345 346 if (event != THERMAL_THROTTLING_EVENT) 347 return; 348 349 if (new_event && !state->last_interrupt_time) { 350 bool hot; 351 u8 temp; 352 353 get_therm_status(state->level, &hot, &temp); 354 /* 355 * Ignore short temperature spike as the system is not close 356 * to PROCHOT. 10C offset is large enough to ignore. It is 357 * already dropped from the high threshold temperature. 358 */ 359 if (temp > 10) 360 return; 361 362 state->baseline_temp = temp; 363 state->last_interrupt_time = now; 364 schedule_delayed_work_on(this_cpu, &state->therm_work, THERM_THROT_POLL_INTERVAL); 365 } else if (old_event && state->last_interrupt_time) { 366 unsigned long throttle_time; 367 368 throttle_time = jiffies_delta_to_msecs(now - state->last_interrupt_time); 369 if (throttle_time > state->max_time_ms) 370 state->max_time_ms = throttle_time; 371 state->total_time_ms += throttle_time; 372 state->last_interrupt_time = 0; 373 } 374 } 375 376 static int thresh_event_valid(int level, int event) 377 { 378 struct _thermal_state *state; 379 unsigned int this_cpu = smp_processor_id(); 380 struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu); 381 u64 now = get_jiffies_64(); 382 383 if (level == PACKAGE_LEVEL) 384 state = (event == 0) ? &pstate->pkg_thresh0 : 385 &pstate->pkg_thresh1; 386 else 387 state = (event == 0) ? &pstate->core_thresh0 : 388 &pstate->core_thresh1; 389 390 if (time_before64(now, state->next_check)) 391 return 0; 392 393 state->next_check = now + CHECK_INTERVAL; 394 395 return 1; 396 } 397 398 static bool int_pln_enable; 399 static int __init int_pln_enable_setup(char *s) 400 { 401 int_pln_enable = true; 402 403 return 1; 404 } 405 __setup("int_pln_enable", int_pln_enable_setup); 406 407 #ifdef CONFIG_SYSFS 408 /* Add/Remove thermal_throttle interface for CPU device: */ 409 static int thermal_throttle_add_dev(struct device *dev, unsigned int cpu) 410 { 411 int err; 412 struct cpuinfo_x86 *c = &cpu_data(cpu); 413 414 err = sysfs_create_group(&dev->kobj, &thermal_attr_group); 415 if (err) 416 return err; 417 418 if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) { 419 err = sysfs_add_file_to_group(&dev->kobj, 420 &dev_attr_core_power_limit_count.attr, 421 thermal_attr_group.name); 422 if (err) 423 goto del_group; 424 } 425 426 if (cpu_has(c, X86_FEATURE_PTS)) { 427 err = sysfs_add_file_to_group(&dev->kobj, 428 &dev_attr_package_throttle_count.attr, 429 thermal_attr_group.name); 430 if (err) 431 goto del_group; 432 433 err = sysfs_add_file_to_group(&dev->kobj, 434 &dev_attr_package_throttle_max_time_ms.attr, 435 thermal_attr_group.name); 436 if (err) 437 goto del_group; 438 439 err = sysfs_add_file_to_group(&dev->kobj, 440 &dev_attr_package_throttle_total_time_ms.attr, 441 thermal_attr_group.name); 442 if (err) 443 goto del_group; 444 445 if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) { 446 err = sysfs_add_file_to_group(&dev->kobj, 447 &dev_attr_package_power_limit_count.attr, 448 thermal_attr_group.name); 449 if (err) 450 goto del_group; 451 } 452 } 453 454 return 0; 455 456 del_group: 457 sysfs_remove_group(&dev->kobj, &thermal_attr_group); 458 459 return err; 460 } 461 462 static void thermal_throttle_remove_dev(struct device *dev) 463 { 464 sysfs_remove_group(&dev->kobj, &thermal_attr_group); 465 } 466 467 /* Get notified when a cpu comes on/off. Be hotplug friendly. */ 468 static int thermal_throttle_online(unsigned int cpu) 469 { 470 struct thermal_state *state = &per_cpu(thermal_state, cpu); 471 struct device *dev = get_cpu_device(cpu); 472 u32 l; 473 474 state->package_throttle.level = PACKAGE_LEVEL; 475 state->core_throttle.level = CORE_LEVEL; 476 477 INIT_DELAYED_WORK(&state->package_throttle.therm_work, throttle_active_work); 478 INIT_DELAYED_WORK(&state->core_throttle.therm_work, throttle_active_work); 479 480 /* 481 * The first CPU coming online will enable the HFI. Usually this causes 482 * hardware to issue an HFI thermal interrupt. Such interrupt will reach 483 * the CPU once we enable the thermal vector in the local APIC. 484 */ 485 intel_hfi_online(cpu); 486 487 /* Unmask the thermal vector after the above workqueues are initialized. */ 488 l = apic_read(APIC_LVTTHMR); 489 apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED); 490 491 return thermal_throttle_add_dev(dev, cpu); 492 } 493 494 static int thermal_throttle_offline(unsigned int cpu) 495 { 496 struct thermal_state *state = &per_cpu(thermal_state, cpu); 497 struct device *dev = get_cpu_device(cpu); 498 u32 l; 499 500 /* Mask the thermal vector before draining evtl. pending work */ 501 l = apic_read(APIC_LVTTHMR); 502 apic_write(APIC_LVTTHMR, l | APIC_LVT_MASKED); 503 504 intel_hfi_offline(cpu); 505 506 cancel_delayed_work_sync(&state->package_throttle.therm_work); 507 cancel_delayed_work_sync(&state->core_throttle.therm_work); 508 509 state->package_throttle.rate_control_active = false; 510 state->core_throttle.rate_control_active = false; 511 512 thermal_throttle_remove_dev(dev); 513 return 0; 514 } 515 516 static __init int thermal_throttle_init_device(void) 517 { 518 int ret; 519 520 if (!atomic_read(&therm_throt_en)) 521 return 0; 522 523 intel_hfi_init(); 524 525 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/therm:online", 526 thermal_throttle_online, 527 thermal_throttle_offline); 528 return ret < 0 ? ret : 0; 529 } 530 device_initcall(thermal_throttle_init_device); 531 532 #endif /* CONFIG_SYSFS */ 533 534 static void notify_package_thresholds(__u64 msr_val) 535 { 536 bool notify_thres_0 = false; 537 bool notify_thres_1 = false; 538 539 if (!platform_thermal_package_notify) 540 return; 541 542 /* lower threshold check */ 543 if (msr_val & THERM_LOG_THRESHOLD0) 544 notify_thres_0 = true; 545 /* higher threshold check */ 546 if (msr_val & THERM_LOG_THRESHOLD1) 547 notify_thres_1 = true; 548 549 if (!notify_thres_0 && !notify_thres_1) 550 return; 551 552 if (platform_thermal_package_rate_control && 553 platform_thermal_package_rate_control()) { 554 /* Rate control is implemented in callback */ 555 platform_thermal_package_notify(msr_val); 556 return; 557 } 558 559 /* lower threshold reached */ 560 if (notify_thres_0 && thresh_event_valid(PACKAGE_LEVEL, 0)) 561 platform_thermal_package_notify(msr_val); 562 /* higher threshold reached */ 563 if (notify_thres_1 && thresh_event_valid(PACKAGE_LEVEL, 1)) 564 platform_thermal_package_notify(msr_val); 565 } 566 567 static void notify_thresholds(__u64 msr_val) 568 { 569 /* check whether the interrupt handler is defined; 570 * otherwise simply return 571 */ 572 if (!platform_thermal_notify) 573 return; 574 575 /* lower threshold reached */ 576 if ((msr_val & THERM_LOG_THRESHOLD0) && 577 thresh_event_valid(CORE_LEVEL, 0)) 578 platform_thermal_notify(msr_val); 579 /* higher threshold reached */ 580 if ((msr_val & THERM_LOG_THRESHOLD1) && 581 thresh_event_valid(CORE_LEVEL, 1)) 582 platform_thermal_notify(msr_val); 583 } 584 585 void __weak notify_hwp_interrupt(void) 586 { 587 wrmsrl_safe(MSR_HWP_STATUS, 0); 588 } 589 590 /* Thermal transition interrupt handler */ 591 void intel_thermal_interrupt(void) 592 { 593 __u64 msr_val; 594 595 if (static_cpu_has(X86_FEATURE_HWP)) 596 notify_hwp_interrupt(); 597 598 rdmsrl(MSR_IA32_THERM_STATUS, msr_val); 599 600 /* Check for violation of core thermal thresholds*/ 601 notify_thresholds(msr_val); 602 603 therm_throt_process(msr_val & THERM_STATUS_PROCHOT, 604 THERMAL_THROTTLING_EVENT, 605 CORE_LEVEL); 606 607 if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable) 608 therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT, 609 POWER_LIMIT_EVENT, 610 CORE_LEVEL); 611 612 if (this_cpu_has(X86_FEATURE_PTS)) { 613 rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val); 614 /* check violations of package thermal thresholds */ 615 notify_package_thresholds(msr_val); 616 therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT, 617 THERMAL_THROTTLING_EVENT, 618 PACKAGE_LEVEL); 619 if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable) 620 therm_throt_process(msr_val & 621 PACKAGE_THERM_STATUS_POWER_LIMIT, 622 POWER_LIMIT_EVENT, 623 PACKAGE_LEVEL); 624 625 if (this_cpu_has(X86_FEATURE_HFI)) 626 intel_hfi_process_event(msr_val & 627 PACKAGE_THERM_STATUS_HFI_UPDATED); 628 } 629 } 630 631 /* Thermal monitoring depends on APIC, ACPI and clock modulation */ 632 static int intel_thermal_supported(struct cpuinfo_x86 *c) 633 { 634 if (!boot_cpu_has(X86_FEATURE_APIC)) 635 return 0; 636 if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC)) 637 return 0; 638 return 1; 639 } 640 641 bool x86_thermal_enabled(void) 642 { 643 return atomic_read(&therm_throt_en); 644 } 645 646 void __init therm_lvt_init(void) 647 { 648 /* 649 * This function is only called on boot CPU. Save the init thermal 650 * LVT value on BSP and use that value to restore APs' thermal LVT 651 * entry BIOS programmed later 652 */ 653 if (intel_thermal_supported(&boot_cpu_data)) 654 lvtthmr_init = apic_read(APIC_LVTTHMR); 655 } 656 657 void intel_init_thermal(struct cpuinfo_x86 *c) 658 { 659 unsigned int cpu = smp_processor_id(); 660 int tm2 = 0; 661 u32 l, h; 662 663 if (!intel_thermal_supported(c)) 664 return; 665 666 /* 667 * First check if its enabled already, in which case there might 668 * be some SMM goo which handles it, so we can't even put a handler 669 * since it might be delivered via SMI already: 670 */ 671 rdmsr(MSR_IA32_MISC_ENABLE, l, h); 672 673 h = lvtthmr_init; 674 /* 675 * The initial value of thermal LVT entries on all APs always reads 676 * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI 677 * sequence to them and LVT registers are reset to 0s except for 678 * the mask bits which are set to 1s when APs receive INIT IPI. 679 * If BIOS takes over the thermal interrupt and sets its interrupt 680 * delivery mode to SMI (not fixed), it restores the value that the 681 * BIOS has programmed on AP based on BSP's info we saved since BIOS 682 * is always setting the same value for all threads/cores. 683 */ 684 if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED) 685 apic_write(APIC_LVTTHMR, lvtthmr_init); 686 687 688 if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) { 689 if (system_state == SYSTEM_BOOTING) 690 pr_debug("CPU%d: Thermal monitoring handled by SMI\n", cpu); 691 return; 692 } 693 694 /* early Pentium M models use different method for enabling TM2 */ 695 if (cpu_has(c, X86_FEATURE_TM2)) { 696 if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) { 697 rdmsr(MSR_THERM2_CTL, l, h); 698 if (l & MSR_THERM2_CTL_TM_SELECT) 699 tm2 = 1; 700 } else if (l & MSR_IA32_MISC_ENABLE_TM2) 701 tm2 = 1; 702 } 703 704 /* We'll mask the thermal vector in the lapic till we're ready: */ 705 h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED; 706 apic_write(APIC_LVTTHMR, h); 707 708 rdmsr(MSR_IA32_THERM_INTERRUPT, l, h); 709 if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable) 710 wrmsr(MSR_IA32_THERM_INTERRUPT, 711 (l | (THERM_INT_LOW_ENABLE 712 | THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h); 713 else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) 714 wrmsr(MSR_IA32_THERM_INTERRUPT, 715 l | (THERM_INT_LOW_ENABLE 716 | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h); 717 else 718 wrmsr(MSR_IA32_THERM_INTERRUPT, 719 l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h); 720 721 if (cpu_has(c, X86_FEATURE_PTS)) { 722 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); 723 if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable) 724 wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, 725 (l | (PACKAGE_THERM_INT_LOW_ENABLE 726 | PACKAGE_THERM_INT_HIGH_ENABLE)) 727 & ~PACKAGE_THERM_INT_PLN_ENABLE, h); 728 else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable) 729 wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, 730 l | (PACKAGE_THERM_INT_LOW_ENABLE 731 | PACKAGE_THERM_INT_HIGH_ENABLE 732 | PACKAGE_THERM_INT_PLN_ENABLE), h); 733 else 734 wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, 735 l | (PACKAGE_THERM_INT_LOW_ENABLE 736 | PACKAGE_THERM_INT_HIGH_ENABLE), h); 737 738 if (cpu_has(c, X86_FEATURE_HFI)) { 739 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); 740 wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, 741 l | PACKAGE_THERM_INT_HFI_ENABLE, h); 742 } 743 } 744 745 rdmsr(MSR_IA32_MISC_ENABLE, l, h); 746 wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h); 747 748 pr_info_once("CPU0: Thermal monitoring enabled (%s)\n", 749 tm2 ? "TM2" : "TM1"); 750 751 /* enable thermal throttle processing */ 752 atomic_set(&therm_throt_en, 1); 753 } 754