1 // SPDX-License-Identifier: GPL-2.0-only 2 /* intel_pch_thermal.c - Intel PCH Thermal driver 3 * 4 * Copyright (c) 2015, Intel Corporation. 5 * 6 * Authors: 7 * Tushar Dave <tushar.n.dave@intel.com> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/delay.h> 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/pci.h> 15 #include <linux/pm.h> 16 #include <linux/suspend.h> 17 #include <linux/thermal.h> 18 #include <linux/types.h> 19 #include <linux/units.h> 20 21 /* Intel PCH thermal Device IDs */ 22 #define PCH_THERMAL_DID_HSW_1 0x9C24 /* Haswell PCH */ 23 #define PCH_THERMAL_DID_HSW_2 0x8C24 /* Haswell PCH */ 24 #define PCH_THERMAL_DID_WPT 0x9CA4 /* Wildcat Point */ 25 #define PCH_THERMAL_DID_SKL 0x9D31 /* Skylake PCH */ 26 #define PCH_THERMAL_DID_SKL_H 0xA131 /* Skylake PCH 100 series */ 27 #define PCH_THERMAL_DID_CNL 0x9Df9 /* CNL PCH */ 28 #define PCH_THERMAL_DID_CNL_H 0xA379 /* CNL-H PCH */ 29 #define PCH_THERMAL_DID_CNL_LP 0x02F9 /* CNL-LP PCH */ 30 #define PCH_THERMAL_DID_CML_H 0X06F9 /* CML-H PCH */ 31 #define PCH_THERMAL_DID_LWB 0xA1B1 /* Lewisburg PCH */ 32 #define PCH_THERMAL_DID_WBG 0x8D24 /* Wellsburg PCH */ 33 34 /* Wildcat Point-LP PCH Thermal registers */ 35 #define WPT_TEMP 0x0000 /* Temperature */ 36 #define WPT_TSC 0x04 /* Thermal Sensor Control */ 37 #define WPT_TSS 0x06 /* Thermal Sensor Status */ 38 #define WPT_TSEL 0x08 /* Thermal Sensor Enable and Lock */ 39 #define WPT_TSREL 0x0A /* Thermal Sensor Report Enable and Lock */ 40 #define WPT_TSMIC 0x0C /* Thermal Sensor SMI Control */ 41 #define WPT_CTT 0x0010 /* Catastrophic Trip Point */ 42 #define WPT_TSPM 0x001C /* Thermal Sensor Power Management */ 43 #define WPT_TAHV 0x0014 /* Thermal Alert High Value */ 44 #define WPT_TALV 0x0018 /* Thermal Alert Low Value */ 45 #define WPT_TL 0x00000040 /* Throttle Value */ 46 #define WPT_PHL 0x0060 /* PCH Hot Level */ 47 #define WPT_PHLC 0x62 /* PHL Control */ 48 #define WPT_TAS 0x80 /* Thermal Alert Status */ 49 #define WPT_TSPIEN 0x82 /* PCI Interrupt Event Enables */ 50 #define WPT_TSGPEN 0x84 /* General Purpose Event Enables */ 51 52 /* Wildcat Point-LP PCH Thermal Register bit definitions */ 53 #define WPT_TEMP_TSR 0x01ff /* Temp TS Reading */ 54 #define WPT_TSC_CPDE 0x01 /* Catastrophic Power-Down Enable */ 55 #define WPT_TSS_TSDSS 0x10 /* Thermal Sensor Dynamic Shutdown Status */ 56 #define WPT_TSS_GPES 0x08 /* GPE status */ 57 #define WPT_TSEL_ETS 0x01 /* Enable TS */ 58 #define WPT_TSEL_PLDB 0x80 /* TSEL Policy Lock-Down Bit */ 59 #define WPT_TL_TOL 0x000001FF /* T0 Level */ 60 #define WPT_TL_T1L 0x1ff00000 /* T1 Level */ 61 #define WPT_TL_TTEN 0x20000000 /* TT Enable */ 62 63 /* Resolution of 1/2 degree C and an offset of -50C */ 64 #define PCH_TEMP_OFFSET (-50) 65 #define GET_WPT_TEMP(x) ((x) * MILLIDEGREE_PER_DEGREE / 2 + WPT_TEMP_OFFSET) 66 #define WPT_TEMP_OFFSET (PCH_TEMP_OFFSET * MILLIDEGREE_PER_DEGREE) 67 #define GET_PCH_TEMP(x) (((x) / 2) + PCH_TEMP_OFFSET) 68 69 #define PCH_MAX_TRIPS 3 /* critical, hot, passive */ 70 71 /* Amount of time for each cooling delay, 100ms by default for now */ 72 static unsigned int delay_timeout = 100; 73 module_param(delay_timeout, int, 0644); 74 MODULE_PARM_DESC(delay_timeout, "amount of time delay for each iteration."); 75 76 /* Number of iterations for cooling delay, 600 counts by default for now */ 77 static unsigned int delay_cnt = 600; 78 module_param(delay_cnt, int, 0644); 79 MODULE_PARM_DESC(delay_cnt, "total number of iterations for time delay."); 80 81 static char driver_name[] = "Intel PCH thermal driver"; 82 83 struct pch_thermal_device { 84 void __iomem *hw_base; 85 struct pci_dev *pdev; 86 struct thermal_zone_device *tzd; 87 struct thermal_trip trips[PCH_MAX_TRIPS]; 88 bool bios_enabled; 89 }; 90 91 #ifdef CONFIG_ACPI 92 /* 93 * On some platforms, there is a companion ACPI device, which adds 94 * passive trip temperature using _PSV method. There is no specific 95 * passive temperature setting in MMIO interface of this PCI device. 96 */ 97 static int pch_wpt_add_acpi_psv_trip(struct pch_thermal_device *ptd, int trip) 98 { 99 struct acpi_device *adev; 100 int temp; 101 102 adev = ACPI_COMPANION(&ptd->pdev->dev); 103 if (!adev) 104 return 0; 105 106 if (thermal_acpi_passive_trip_temp(adev, &temp) || temp <= 0) 107 return 0; 108 109 ptd->trips[trip].type = THERMAL_TRIP_PASSIVE; 110 ptd->trips[trip].temperature = temp; 111 return 1; 112 } 113 #else 114 static int pch_wpt_add_acpi_psv_trip(struct pch_thermal_device *ptd, int trip) 115 { 116 return 0; 117 } 118 #endif 119 120 static int pch_hw_init(struct pch_thermal_device *ptd) 121 { 122 int nr_trips = 0; 123 u16 trip_temp; 124 u8 tsel; 125 126 /* Check if BIOS has already enabled thermal sensor */ 127 if (WPT_TSEL_ETS & readb(ptd->hw_base + WPT_TSEL)) { 128 ptd->bios_enabled = true; 129 goto read_trips; 130 } 131 132 tsel = readb(ptd->hw_base + WPT_TSEL); 133 /* 134 * When TSEL's Policy Lock-Down bit is 1, TSEL become RO. 135 * If so, thermal sensor cannot enable. Bail out. 136 */ 137 if (tsel & WPT_TSEL_PLDB) { 138 dev_err(&ptd->pdev->dev, "Sensor can't be enabled\n"); 139 return -ENODEV; 140 } 141 142 writeb(tsel|WPT_TSEL_ETS, ptd->hw_base + WPT_TSEL); 143 if (!(WPT_TSEL_ETS & readb(ptd->hw_base + WPT_TSEL))) { 144 dev_err(&ptd->pdev->dev, "Sensor can't be enabled\n"); 145 return -ENODEV; 146 } 147 148 read_trips: 149 trip_temp = readw(ptd->hw_base + WPT_CTT); 150 trip_temp &= 0x1FF; 151 if (trip_temp) { 152 ptd->trips[nr_trips].temperature = GET_WPT_TEMP(trip_temp); 153 ptd->trips[nr_trips++].type = THERMAL_TRIP_CRITICAL; 154 } 155 156 trip_temp = readw(ptd->hw_base + WPT_PHL); 157 trip_temp &= 0x1FF; 158 if (trip_temp) { 159 ptd->trips[nr_trips].temperature = GET_WPT_TEMP(trip_temp); 160 ptd->trips[nr_trips++].type = THERMAL_TRIP_HOT; 161 } 162 163 return nr_trips + pch_wpt_add_acpi_psv_trip(ptd, nr_trips); 164 } 165 166 static int pch_get_temp(struct pch_thermal_device *ptd) 167 { 168 return GET_WPT_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TEMP)); 169 } 170 171 /* Cool the PCH when it's overheat in .suspend_noirq phase */ 172 static int pch_suspend(struct pch_thermal_device *ptd) 173 { 174 u8 tsel; 175 int pch_delay_cnt = 0; 176 u16 pch_thr_temp, pch_cur_temp; 177 178 /* Shutdown the thermal sensor if it is not enabled by BIOS */ 179 if (!ptd->bios_enabled) { 180 tsel = readb(ptd->hw_base + WPT_TSEL); 181 writeb(tsel & 0xFE, ptd->hw_base + WPT_TSEL); 182 return 0; 183 } 184 185 /* Do not check temperature if it is not s2idle */ 186 if (pm_suspend_via_firmware()) 187 return 0; 188 189 /* Get the PCH temperature threshold value */ 190 pch_thr_temp = GET_PCH_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TSPM)); 191 192 /* Get the PCH current temperature value */ 193 pch_cur_temp = GET_PCH_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TEMP)); 194 195 /* 196 * If current PCH temperature is higher than configured PCH threshold 197 * value, run some delay loop with sleep to let the current temperature 198 * go down below the threshold value which helps to allow system enter 199 * lower power S0ix suspend state. Even after delay loop if PCH current 200 * temperature stays above threshold, notify the warning message 201 * which helps to indentify the reason why S0ix entry was rejected. 202 */ 203 while (pch_delay_cnt < delay_cnt) { 204 if (pch_cur_temp < pch_thr_temp) 205 break; 206 207 if (pm_wakeup_pending()) { 208 dev_warn(&ptd->pdev->dev, "Wakeup event detected, abort cooling\n"); 209 return 0; 210 } 211 212 pch_delay_cnt++; 213 dev_dbg(&ptd->pdev->dev, 214 "CPU-PCH current temp [%dC] higher than the threshold temp [%dC], sleep %d times for %d ms duration\n", 215 pch_cur_temp, pch_thr_temp, pch_delay_cnt, delay_timeout); 216 msleep(delay_timeout); 217 /* Read the PCH current temperature for next cycle. */ 218 pch_cur_temp = GET_PCH_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TEMP)); 219 } 220 221 if (pch_cur_temp >= pch_thr_temp) 222 dev_warn(&ptd->pdev->dev, 223 "CPU-PCH is hot [%dC] after %d ms delay. S0ix might fail\n", 224 pch_cur_temp, pch_delay_cnt * delay_timeout); 225 else { 226 if (pch_delay_cnt) 227 dev_info(&ptd->pdev->dev, 228 "CPU-PCH is cool [%dC] after %d ms delay\n", 229 pch_cur_temp, pch_delay_cnt * delay_timeout); 230 else 231 dev_info(&ptd->pdev->dev, 232 "CPU-PCH is cool [%dC]\n", 233 pch_cur_temp); 234 } 235 236 return 0; 237 } 238 239 static int pch_resume(struct pch_thermal_device *ptd) 240 { 241 u8 tsel; 242 243 if (ptd->bios_enabled) 244 return 0; 245 246 tsel = readb(ptd->hw_base + WPT_TSEL); 247 248 writeb(tsel | WPT_TSEL_ETS, ptd->hw_base + WPT_TSEL); 249 250 return 0; 251 } 252 253 static int pch_thermal_get_temp(struct thermal_zone_device *tzd, int *temp) 254 { 255 struct pch_thermal_device *ptd = tzd->devdata; 256 257 *temp = pch_get_temp(ptd); 258 return 0; 259 } 260 261 static void pch_critical(struct thermal_zone_device *tzd) 262 { 263 dev_dbg(&tzd->device, "%s: critical temperature reached\n", tzd->type); 264 } 265 266 static struct thermal_zone_device_ops tzd_ops = { 267 .get_temp = pch_thermal_get_temp, 268 .critical = pch_critical, 269 }; 270 271 enum board_ids { 272 board_hsw, 273 board_wpt, 274 board_skl, 275 board_cnl, 276 board_cml, 277 board_lwb, 278 board_wbg, 279 }; 280 281 static const struct board_info { 282 const char *name; 283 } board_info[] = { 284 [board_hsw] = { 285 .name = "pch_haswell", 286 }, 287 [board_wpt] = { 288 .name = "pch_wildcat_point", 289 }, 290 [board_skl] = { 291 .name = "pch_skylake", 292 }, 293 [board_cnl] = { 294 .name = "pch_cannonlake", 295 }, 296 [board_cml] = { 297 .name = "pch_cometlake", 298 }, 299 [board_lwb] = { 300 .name = "pch_lewisburg", 301 }, 302 [board_wbg] = { 303 .name = "pch_wellsburg", 304 }, 305 }; 306 307 static int intel_pch_thermal_probe(struct pci_dev *pdev, 308 const struct pci_device_id *id) 309 { 310 enum board_ids board_id = id->driver_data; 311 const struct board_info *bi = &board_info[board_id]; 312 struct pch_thermal_device *ptd; 313 int err; 314 int nr_trips; 315 316 ptd = devm_kzalloc(&pdev->dev, sizeof(*ptd), GFP_KERNEL); 317 if (!ptd) 318 return -ENOMEM; 319 320 pci_set_drvdata(pdev, ptd); 321 ptd->pdev = pdev; 322 323 err = pci_enable_device(pdev); 324 if (err) { 325 dev_err(&pdev->dev, "failed to enable pci device\n"); 326 return err; 327 } 328 329 err = pci_request_regions(pdev, driver_name); 330 if (err) { 331 dev_err(&pdev->dev, "failed to request pci region\n"); 332 goto error_disable; 333 } 334 335 ptd->hw_base = pci_ioremap_bar(pdev, 0); 336 if (!ptd->hw_base) { 337 err = -ENOMEM; 338 dev_err(&pdev->dev, "failed to map mem base\n"); 339 goto error_release; 340 } 341 342 nr_trips = pch_hw_init(ptd); 343 if (nr_trips < 0) { 344 err = nr_trips; 345 goto error_cleanup; 346 } 347 348 ptd->tzd = thermal_zone_device_register_with_trips(bi->name, ptd->trips, 349 nr_trips, 0, ptd, 350 &tzd_ops, NULL, 0, 0); 351 if (IS_ERR(ptd->tzd)) { 352 dev_err(&pdev->dev, "Failed to register thermal zone %s\n", 353 bi->name); 354 err = PTR_ERR(ptd->tzd); 355 goto error_cleanup; 356 } 357 err = thermal_zone_device_enable(ptd->tzd); 358 if (err) 359 goto err_unregister; 360 361 return 0; 362 363 err_unregister: 364 thermal_zone_device_unregister(ptd->tzd); 365 error_cleanup: 366 iounmap(ptd->hw_base); 367 error_release: 368 pci_release_regions(pdev); 369 error_disable: 370 pci_disable_device(pdev); 371 dev_err(&pdev->dev, "pci device failed to probe\n"); 372 return err; 373 } 374 375 static void intel_pch_thermal_remove(struct pci_dev *pdev) 376 { 377 struct pch_thermal_device *ptd = pci_get_drvdata(pdev); 378 379 thermal_zone_device_unregister(ptd->tzd); 380 iounmap(ptd->hw_base); 381 pci_set_drvdata(pdev, NULL); 382 pci_release_regions(pdev); 383 pci_disable_device(pdev); 384 } 385 386 static int intel_pch_thermal_suspend_noirq(struct device *device) 387 { 388 struct pch_thermal_device *ptd = dev_get_drvdata(device); 389 390 return pch_suspend(ptd); 391 } 392 393 static int intel_pch_thermal_resume(struct device *device) 394 { 395 struct pch_thermal_device *ptd = dev_get_drvdata(device); 396 397 return pch_resume(ptd); 398 } 399 400 static const struct pci_device_id intel_pch_thermal_id[] = { 401 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_HSW_1), 402 .driver_data = board_hsw, }, 403 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_HSW_2), 404 .driver_data = board_hsw, }, 405 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_WPT), 406 .driver_data = board_wpt, }, 407 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_SKL), 408 .driver_data = board_skl, }, 409 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_SKL_H), 410 .driver_data = board_skl, }, 411 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_CNL), 412 .driver_data = board_cnl, }, 413 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_CNL_H), 414 .driver_data = board_cnl, }, 415 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_CNL_LP), 416 .driver_data = board_cnl, }, 417 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_CML_H), 418 .driver_data = board_cml, }, 419 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_LWB), 420 .driver_data = board_lwb, }, 421 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_WBG), 422 .driver_data = board_wbg, }, 423 { 0, }, 424 }; 425 MODULE_DEVICE_TABLE(pci, intel_pch_thermal_id); 426 427 static const struct dev_pm_ops intel_pch_pm_ops = { 428 .suspend_noirq = intel_pch_thermal_suspend_noirq, 429 .resume = intel_pch_thermal_resume, 430 }; 431 432 static struct pci_driver intel_pch_thermal_driver = { 433 .name = "intel_pch_thermal", 434 .id_table = intel_pch_thermal_id, 435 .probe = intel_pch_thermal_probe, 436 .remove = intel_pch_thermal_remove, 437 .driver.pm = &intel_pch_pm_ops, 438 }; 439 440 module_pci_driver(intel_pch_thermal_driver); 441 442 MODULE_LICENSE("GPL v2"); 443 MODULE_DESCRIPTION("Intel PCH Thermal driver"); 444