1 // SPDX-License-Identifier: GPL-2.0-only
2 /* intel_pch_thermal.c - Intel PCH Thermal driver
3  *
4  * Copyright (c) 2015, Intel Corporation.
5  *
6  * Authors:
7  *     Tushar Dave <tushar.n.dave@intel.com>
8  */
9 
10 #include <linux/acpi.h>
11 #include <linux/delay.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/pci.h>
15 #include <linux/pm.h>
16 #include <linux/suspend.h>
17 #include <linux/thermal.h>
18 #include <linux/types.h>
19 #include <linux/units.h>
20 
21 /* Intel PCH thermal Device IDs */
22 #define PCH_THERMAL_DID_HSW_1	0x9C24 /* Haswell PCH */
23 #define PCH_THERMAL_DID_HSW_2	0x8C24 /* Haswell PCH */
24 #define PCH_THERMAL_DID_WPT	0x9CA4 /* Wildcat Point */
25 #define PCH_THERMAL_DID_SKL	0x9D31 /* Skylake PCH */
26 #define PCH_THERMAL_DID_SKL_H	0xA131 /* Skylake PCH 100 series */
27 #define PCH_THERMAL_DID_CNL	0x9Df9 /* CNL PCH */
28 #define PCH_THERMAL_DID_CNL_H	0xA379 /* CNL-H PCH */
29 #define PCH_THERMAL_DID_CNL_LP	0x02F9 /* CNL-LP PCH */
30 #define PCH_THERMAL_DID_CML_H	0X06F9 /* CML-H PCH */
31 #define PCH_THERMAL_DID_LWB	0xA1B1 /* Lewisburg PCH */
32 #define PCH_THERMAL_DID_WBG	0x8D24 /* Wellsburg PCH */
33 
34 /* Wildcat Point-LP  PCH Thermal registers */
35 #define WPT_TEMP	0x0000	/* Temperature */
36 #define WPT_TSC	0x04	/* Thermal Sensor Control */
37 #define WPT_TSS	0x06	/* Thermal Sensor Status */
38 #define WPT_TSEL	0x08	/* Thermal Sensor Enable and Lock */
39 #define WPT_TSREL	0x0A	/* Thermal Sensor Report Enable and Lock */
40 #define WPT_TSMIC	0x0C	/* Thermal Sensor SMI Control */
41 #define WPT_CTT	0x0010	/* Catastrophic Trip Point */
42 #define WPT_TSPM	0x001C	/* Thermal Sensor Power Management */
43 #define WPT_TAHV	0x0014	/* Thermal Alert High Value */
44 #define WPT_TALV	0x0018	/* Thermal Alert Low Value */
45 #define WPT_TL		0x00000040	/* Throttle Value */
46 #define WPT_PHL	0x0060	/* PCH Hot Level */
47 #define WPT_PHLC	0x62	/* PHL Control */
48 #define WPT_TAS	0x80	/* Thermal Alert Status */
49 #define WPT_TSPIEN	0x82	/* PCI Interrupt Event Enables */
50 #define WPT_TSGPEN	0x84	/* General Purpose Event Enables */
51 
52 /*  Wildcat Point-LP  PCH Thermal Register bit definitions */
53 #define WPT_TEMP_TSR	0x01ff	/* Temp TS Reading */
54 #define WPT_TSC_CPDE	0x01	/* Catastrophic Power-Down Enable */
55 #define WPT_TSS_TSDSS	0x10	/* Thermal Sensor Dynamic Shutdown Status */
56 #define WPT_TSS_GPES	0x08	/* GPE status */
57 #define WPT_TSEL_ETS	0x01    /* Enable TS */
58 #define WPT_TSEL_PLDB	0x80	/* TSEL Policy Lock-Down Bit */
59 #define WPT_TL_TOL	0x000001FF	/* T0 Level */
60 #define WPT_TL_T1L	0x1ff00000	/* T1 Level */
61 #define WPT_TL_TTEN	0x20000000	/* TT Enable */
62 
63 /* Resolution of 1/2 degree C and an offset of -50C */
64 #define PCH_TEMP_OFFSET	(-50)
65 #define GET_WPT_TEMP(x)	((x) * MILLIDEGREE_PER_DEGREE / 2 + WPT_TEMP_OFFSET)
66 #define WPT_TEMP_OFFSET	(PCH_TEMP_OFFSET * MILLIDEGREE_PER_DEGREE)
67 #define GET_PCH_TEMP(x)	(((x) / 2) + PCH_TEMP_OFFSET)
68 
69 #define PCH_MAX_TRIPS 3 /* critical, hot, passive */
70 
71 /* Amount of time for each cooling delay, 100ms by default for now */
72 static unsigned int delay_timeout = 100;
73 module_param(delay_timeout, int, 0644);
74 MODULE_PARM_DESC(delay_timeout, "amount of time delay for each iteration.");
75 
76 /* Number of iterations for cooling delay, 600 counts by default for now */
77 static unsigned int delay_cnt = 600;
78 module_param(delay_cnt, int, 0644);
79 MODULE_PARM_DESC(delay_cnt, "total number of iterations for time delay.");
80 
81 static char driver_name[] = "Intel PCH thermal driver";
82 
83 struct pch_thermal_device {
84 	void __iomem *hw_base;
85 	const struct pch_dev_ops *ops;
86 	struct pci_dev *pdev;
87 	struct thermal_zone_device *tzd;
88 	struct thermal_trip trips[PCH_MAX_TRIPS];
89 	bool bios_enabled;
90 };
91 
92 #ifdef CONFIG_ACPI
93 /*
94  * On some platforms, there is a companion ACPI device, which adds
95  * passive trip temperature using _PSV method. There is no specific
96  * passive temperature setting in MMIO interface of this PCI device.
97  */
98 static int pch_wpt_add_acpi_psv_trip(struct pch_thermal_device *ptd, int trip)
99 {
100 	struct acpi_device *adev;
101 	int temp;
102 
103 	adev = ACPI_COMPANION(&ptd->pdev->dev);
104 	if (!adev)
105 		return 0;
106 
107 	if (thermal_acpi_passive_trip_temp(adev, &temp) || temp <= 0)
108 		return 0;
109 
110 	ptd->trips[trip].type = THERMAL_TRIP_PASSIVE;
111 	ptd->trips[trip].temperature = temp;
112 	return 1;
113 }
114 #else
115 static int pch_wpt_add_acpi_psv_trip(struct pch_thermal_device *ptd, int trip)
116 {
117 	return 0;
118 }
119 #endif
120 
121 static int pch_wpt_init(struct pch_thermal_device *ptd, int *nr_trips)
122 {
123 	u8 tsel;
124 	u16 trip_temp;
125 
126 	*nr_trips = 0;
127 
128 	/* Check if BIOS has already enabled thermal sensor */
129 	if (WPT_TSEL_ETS & readb(ptd->hw_base + WPT_TSEL)) {
130 		ptd->bios_enabled = true;
131 		goto read_trips;
132 	}
133 
134 	tsel = readb(ptd->hw_base + WPT_TSEL);
135 	/*
136 	 * When TSEL's Policy Lock-Down bit is 1, TSEL become RO.
137 	 * If so, thermal sensor cannot enable. Bail out.
138 	 */
139 	if (tsel & WPT_TSEL_PLDB) {
140 		dev_err(&ptd->pdev->dev, "Sensor can't be enabled\n");
141 		return -ENODEV;
142 	}
143 
144 	writeb(tsel|WPT_TSEL_ETS, ptd->hw_base + WPT_TSEL);
145 	if (!(WPT_TSEL_ETS & readb(ptd->hw_base + WPT_TSEL))) {
146 		dev_err(&ptd->pdev->dev, "Sensor can't be enabled\n");
147 		return -ENODEV;
148 	}
149 
150 read_trips:
151 	trip_temp = readw(ptd->hw_base + WPT_CTT);
152 	trip_temp &= 0x1FF;
153 	if (trip_temp) {
154 		ptd->trips[*nr_trips].temperature = GET_WPT_TEMP(trip_temp);
155 		ptd->trips[*nr_trips].type = THERMAL_TRIP_CRITICAL;
156 		++(*nr_trips);
157 	}
158 
159 	trip_temp = readw(ptd->hw_base + WPT_PHL);
160 	trip_temp &= 0x1FF;
161 	if (trip_temp) {
162 		ptd->trips[*nr_trips].temperature = GET_WPT_TEMP(trip_temp);
163 		ptd->trips[*nr_trips].type = THERMAL_TRIP_HOT;
164 		++(*nr_trips);
165 	}
166 
167 	*nr_trips += pch_wpt_add_acpi_psv_trip(ptd, *nr_trips);
168 
169 	return 0;
170 }
171 
172 static int pch_wpt_get_temp(struct pch_thermal_device *ptd, int *temp)
173 {
174 	*temp = GET_WPT_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TEMP));
175 
176 	return 0;
177 }
178 
179 /* Cool the PCH when it's overheat in .suspend_noirq phase */
180 static int pch_wpt_suspend(struct pch_thermal_device *ptd)
181 {
182 	u8 tsel;
183 	int pch_delay_cnt = 0;
184 	u16 pch_thr_temp, pch_cur_temp;
185 
186 	/* Shutdown the thermal sensor if it is not enabled by BIOS */
187 	if (!ptd->bios_enabled) {
188 		tsel = readb(ptd->hw_base + WPT_TSEL);
189 		writeb(tsel & 0xFE, ptd->hw_base + WPT_TSEL);
190 		return 0;
191 	}
192 
193 	/* Do not check temperature if it is not s2idle */
194 	if (pm_suspend_via_firmware())
195 		return 0;
196 
197 	/* Get the PCH temperature threshold value */
198 	pch_thr_temp = GET_PCH_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TSPM));
199 
200 	/* Get the PCH current temperature value */
201 	pch_cur_temp = GET_PCH_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TEMP));
202 
203 	/*
204 	 * If current PCH temperature is higher than configured PCH threshold
205 	 * value, run some delay loop with sleep to let the current temperature
206 	 * go down below the threshold value which helps to allow system enter
207 	 * lower power S0ix suspend state. Even after delay loop if PCH current
208 	 * temperature stays above threshold, notify the warning message
209 	 * which helps to indentify the reason why S0ix entry was rejected.
210 	 */
211 	while (pch_delay_cnt < delay_cnt) {
212 		if (pch_cur_temp < pch_thr_temp)
213 			break;
214 
215 		if (pm_wakeup_pending()) {
216 			dev_warn(&ptd->pdev->dev, "Wakeup event detected, abort cooling\n");
217 			return 0;
218 		}
219 
220 		pch_delay_cnt++;
221 		dev_dbg(&ptd->pdev->dev,
222 			"CPU-PCH current temp [%dC] higher than the threshold temp [%dC], sleep %d times for %d ms duration\n",
223 			pch_cur_temp, pch_thr_temp, pch_delay_cnt, delay_timeout);
224 		msleep(delay_timeout);
225 		/* Read the PCH current temperature for next cycle. */
226 		pch_cur_temp = GET_PCH_TEMP(WPT_TEMP_TSR & readw(ptd->hw_base + WPT_TEMP));
227 	}
228 
229 	if (pch_cur_temp >= pch_thr_temp)
230 		dev_warn(&ptd->pdev->dev,
231 			"CPU-PCH is hot [%dC] after %d ms delay. S0ix might fail\n",
232 			pch_cur_temp, pch_delay_cnt * delay_timeout);
233 	else {
234 		if (pch_delay_cnt)
235 			dev_info(&ptd->pdev->dev,
236 				"CPU-PCH is cool [%dC] after %d ms delay\n",
237 				pch_cur_temp, pch_delay_cnt * delay_timeout);
238 		else
239 			dev_info(&ptd->pdev->dev,
240 				"CPU-PCH is cool [%dC]\n",
241 				pch_cur_temp);
242 	}
243 
244 	return 0;
245 }
246 
247 static int pch_wpt_resume(struct pch_thermal_device *ptd)
248 {
249 	u8 tsel;
250 
251 	if (ptd->bios_enabled)
252 		return 0;
253 
254 	tsel = readb(ptd->hw_base + WPT_TSEL);
255 
256 	writeb(tsel | WPT_TSEL_ETS, ptd->hw_base + WPT_TSEL);
257 
258 	return 0;
259 }
260 
261 struct pch_dev_ops {
262 	int (*hw_init)(struct pch_thermal_device *ptd, int *nr_trips);
263 	int (*get_temp)(struct pch_thermal_device *ptd, int *temp);
264 	int (*suspend)(struct pch_thermal_device *ptd);
265 	int (*resume)(struct pch_thermal_device *ptd);
266 };
267 
268 
269 /* dev ops for Wildcat Point */
270 static const struct pch_dev_ops pch_dev_ops_wpt = {
271 	.hw_init = pch_wpt_init,
272 	.get_temp = pch_wpt_get_temp,
273 	.suspend = pch_wpt_suspend,
274 	.resume = pch_wpt_resume,
275 };
276 
277 static int pch_thermal_get_temp(struct thermal_zone_device *tzd, int *temp)
278 {
279 	struct pch_thermal_device *ptd = tzd->devdata;
280 
281 	return	ptd->ops->get_temp(ptd, temp);
282 }
283 
284 static void pch_critical(struct thermal_zone_device *tzd)
285 {
286 	dev_dbg(&tzd->device, "%s: critical temperature reached\n", tzd->type);
287 }
288 
289 static struct thermal_zone_device_ops tzd_ops = {
290 	.get_temp = pch_thermal_get_temp,
291 	.critical = pch_critical,
292 };
293 
294 enum board_ids {
295 	board_hsw,
296 	board_wpt,
297 	board_skl,
298 	board_cnl,
299 	board_cml,
300 	board_lwb,
301 	board_wbg,
302 };
303 
304 static const struct board_info {
305 	const char *name;
306 	const struct pch_dev_ops *ops;
307 } board_info[] = {
308 	[board_hsw] = {
309 		.name = "pch_haswell",
310 		.ops = &pch_dev_ops_wpt,
311 	},
312 	[board_wpt] = {
313 		.name = "pch_wildcat_point",
314 		.ops = &pch_dev_ops_wpt,
315 	},
316 	[board_skl] = {
317 		.name = "pch_skylake",
318 		.ops = &pch_dev_ops_wpt,
319 	},
320 	[board_cnl] = {
321 		.name = "pch_cannonlake",
322 		.ops = &pch_dev_ops_wpt,
323 	},
324 	[board_cml] = {
325 		.name = "pch_cometlake",
326 		.ops = &pch_dev_ops_wpt,
327 	},
328 	[board_lwb] = {
329 		.name = "pch_lewisburg",
330 		.ops = &pch_dev_ops_wpt,
331 	},
332 	[board_wbg] = {
333 		.name = "pch_wellsburg",
334 		.ops = &pch_dev_ops_wpt,
335 	},
336 };
337 
338 static int intel_pch_thermal_probe(struct pci_dev *pdev,
339 				   const struct pci_device_id *id)
340 {
341 	enum board_ids board_id = id->driver_data;
342 	const struct board_info *bi = &board_info[board_id];
343 	struct pch_thermal_device *ptd;
344 	int err;
345 	int nr_trips;
346 
347 	ptd = devm_kzalloc(&pdev->dev, sizeof(*ptd), GFP_KERNEL);
348 	if (!ptd)
349 		return -ENOMEM;
350 
351 	ptd->ops = bi->ops;
352 
353 	pci_set_drvdata(pdev, ptd);
354 	ptd->pdev = pdev;
355 
356 	err = pci_enable_device(pdev);
357 	if (err) {
358 		dev_err(&pdev->dev, "failed to enable pci device\n");
359 		return err;
360 	}
361 
362 	err = pci_request_regions(pdev, driver_name);
363 	if (err) {
364 		dev_err(&pdev->dev, "failed to request pci region\n");
365 		goto error_disable;
366 	}
367 
368 	ptd->hw_base = pci_ioremap_bar(pdev, 0);
369 	if (!ptd->hw_base) {
370 		err = -ENOMEM;
371 		dev_err(&pdev->dev, "failed to map mem base\n");
372 		goto error_release;
373 	}
374 
375 	err = ptd->ops->hw_init(ptd, &nr_trips);
376 	if (err)
377 		goto error_cleanup;
378 
379 	ptd->tzd = thermal_zone_device_register_with_trips(bi->name, ptd->trips,
380 							   nr_trips, 0, ptd,
381 							   &tzd_ops, NULL, 0, 0);
382 	if (IS_ERR(ptd->tzd)) {
383 		dev_err(&pdev->dev, "Failed to register thermal zone %s\n",
384 			bi->name);
385 		err = PTR_ERR(ptd->tzd);
386 		goto error_cleanup;
387 	}
388 	err = thermal_zone_device_enable(ptd->tzd);
389 	if (err)
390 		goto err_unregister;
391 
392 	return 0;
393 
394 err_unregister:
395 	thermal_zone_device_unregister(ptd->tzd);
396 error_cleanup:
397 	iounmap(ptd->hw_base);
398 error_release:
399 	pci_release_regions(pdev);
400 error_disable:
401 	pci_disable_device(pdev);
402 	dev_err(&pdev->dev, "pci device failed to probe\n");
403 	return err;
404 }
405 
406 static void intel_pch_thermal_remove(struct pci_dev *pdev)
407 {
408 	struct pch_thermal_device *ptd = pci_get_drvdata(pdev);
409 
410 	thermal_zone_device_unregister(ptd->tzd);
411 	iounmap(ptd->hw_base);
412 	pci_set_drvdata(pdev, NULL);
413 	pci_release_regions(pdev);
414 	pci_disable_device(pdev);
415 }
416 
417 static int intel_pch_thermal_suspend_noirq(struct device *device)
418 {
419 	struct pch_thermal_device *ptd = dev_get_drvdata(device);
420 
421 	return ptd->ops->suspend(ptd);
422 }
423 
424 static int intel_pch_thermal_resume(struct device *device)
425 {
426 	struct pch_thermal_device *ptd = dev_get_drvdata(device);
427 
428 	return ptd->ops->resume(ptd);
429 }
430 
431 static const struct pci_device_id intel_pch_thermal_id[] = {
432 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_HSW_1),
433 		.driver_data = board_hsw, },
434 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_HSW_2),
435 		.driver_data = board_hsw, },
436 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_WPT),
437 		.driver_data = board_wpt, },
438 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_SKL),
439 		.driver_data = board_skl, },
440 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_SKL_H),
441 		.driver_data = board_skl, },
442 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_CNL),
443 		.driver_data = board_cnl, },
444 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_CNL_H),
445 		.driver_data = board_cnl, },
446 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_CNL_LP),
447 		.driver_data = board_cnl, },
448 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_CML_H),
449 		.driver_data = board_cml, },
450 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_LWB),
451 		.driver_data = board_lwb, },
452 	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCH_THERMAL_DID_WBG),
453 		.driver_data = board_wbg, },
454 	{ 0, },
455 };
456 MODULE_DEVICE_TABLE(pci, intel_pch_thermal_id);
457 
458 static const struct dev_pm_ops intel_pch_pm_ops = {
459 	.suspend_noirq = intel_pch_thermal_suspend_noirq,
460 	.resume = intel_pch_thermal_resume,
461 };
462 
463 static struct pci_driver intel_pch_thermal_driver = {
464 	.name		= "intel_pch_thermal",
465 	.id_table	= intel_pch_thermal_id,
466 	.probe		= intel_pch_thermal_probe,
467 	.remove		= intel_pch_thermal_remove,
468 	.driver.pm	= &intel_pch_pm_ops,
469 };
470 
471 module_pci_driver(intel_pch_thermal_driver);
472 
473 MODULE_LICENSE("GPL v2");
474 MODULE_DESCRIPTION("Intel PCH Thermal driver");
475